Switch the ARM9 to using the Dcache in write-back mode. Avoid an
unknown problem with dcache_inv_range by using a wbinv for now (similarly for ARM10). When setting the ARM9 system control register, use the computed cpuctrlmask value (not 0xffffffff) so that the clocking-mode bits are not reset to FastBus mode (which isn't very fast).
This commit is contained in:
rearnsha
parent
f678f5ebbb
commit
8e61df4a12
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@ -1,4 +1,4 @@
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/* $NetBSD: cpufunc.c,v 1.65 2003/11/05 12:53:15 scw Exp $ */
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/* $NetBSD: cpufunc.c,v 1.66 2004/01/26 15:54:16 rearnsha Exp $ */
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/*
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* arm7tdmi support code Copyright (c) 2001 John Fremlin
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@ -46,7 +46,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.65 2003/11/05 12:53:15 scw Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.66 2004/01/26 15:54:16 rearnsha Exp $");
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#include "opt_compat_netbsd.h"
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#include "opt_cpuoptions.h"
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@ -425,17 +425,16 @@ struct cpu_functions arm9_cpufuncs = {
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/* Cache operations */
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arm9_cache_syncI, /* icache_sync_all */
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arm9_cache_syncI_rng, /* icache_sync_range */
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arm9_icache_sync_all, /* icache_sync_all */
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arm9_icache_sync_range, /* icache_sync_range */
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/* ...cache in write-though mode... */
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arm9_cache_flushD, /* dcache_wbinv_all */
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arm9_cache_flushD_rng, /* dcache_wbinv_range */
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arm9_cache_flushD_rng, /* dcache_inv_range */
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(void *)cpufunc_nullop, /* dcache_wb_range */
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arm9_dcache_wbinv_all, /* dcache_wbinv_all */
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arm9_dcache_wbinv_range, /* dcache_wbinv_range */
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/*XXX*/ arm9_dcache_wbinv_range, /* dcache_inv_range */
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arm9_dcache_wb_range, /* dcache_wb_range */
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arm9_cache_flushID, /* idcache_wbinv_all */
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arm9_cache_flushID_rng, /* idcache_wbinv_range */
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arm9_idcache_wbinv_all, /* idcache_wbinv_all */
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arm9_idcache_wbinv_range, /* idcache_wbinv_range */
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/* Other functions */
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@ -489,7 +488,7 @@ struct cpu_functions arm10_cpufuncs = {
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arm10_dcache_wbinv_all, /* dcache_wbinv_all */
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arm10_dcache_wbinv_range, /* dcache_wbinv_range */
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arm10_dcache_inv_range, /* dcache_inv_range */
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/*XXX*/ arm10_dcache_wbinv_range, /* dcache_inv_range */
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arm10_dcache_wb_range, /* dcache_wb_range */
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arm10_idcache_wbinv_all, /* idcache_wbinv_all */
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@ -972,7 +971,13 @@ set_cpufuncs()
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cpufuncs = arm9_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
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get_cachetype_cp15();
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pmap_pte_init_arm9();
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arm9_dcache_sets_inc = 1U << arm_dcache_l2_linesize;
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arm9_dcache_sets_max =
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(1U << (arm_dcache_l2_linesize + arm_dcache_l2_nsets)) -
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arm9_dcache_sets_inc;
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arm9_dcache_index_inc = 1U << (32 - arm_dcache_l2_assoc);
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arm9_dcache_index_max = 0U - arm9_dcache_index_inc;
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pmap_pte_init_generic();
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return 0;
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}
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#endif /* CPU_ARM9 */
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@ -1848,8 +1853,8 @@ arm9_setup(args)
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| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
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| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_ROM_ENABLE
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| CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE
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| CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE
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| CPU_CONTROL_CPCLK;
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| CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_VECRELOC
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| CPU_CONTROL_ROUNDROBIN;
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#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
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cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
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@ -1866,7 +1871,7 @@ arm9_setup(args)
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/* Set the control register */
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curcpu()->ci_ctrl = cpuctrl;
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cpu_control(0xffffffff, cpuctrl);
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cpu_control(cpuctrlmask, cpuctrl);
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}
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#endif /* CPU_ARM9 */
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@ -1891,7 +1896,7 @@ arm10_setup(args)
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int cpuctrl, cpuctrlmask;
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cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
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| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
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| CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_BPRD_ENABLE;
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cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
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@ -1,7 +1,7 @@
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/* $NetBSD: cpufunc_asm_arm9.S,v 1.2 2002/01/29 15:27:29 rearnsha Exp $ */
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/* $NetBSD: cpufunc_asm_arm9.S,v 1.3 2004/01/26 15:54:16 rearnsha Exp $ */
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/*
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* Copyright (c) 2001 ARM Limited
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* Copyright (c) 2001, 2004 ARM Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -41,12 +41,9 @@
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* addresses that are about to change.
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*/
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ENTRY(arm9_setttb)
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/*
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* Since we use the caches in write-through mode, we only have to
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* drain the write buffers and flush the caches.
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*/
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mcr p15, 0, r0, c7, c7, 0 /* flush I+D caches */
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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stmfd sp!, {r0, lr}
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bl _C_LABEL(arm9_idcache_wbinv_all)
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ldmfd sp!, {r0, lr}
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mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
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@ -62,54 +59,156 @@ ENTRY(arm9_tlb_flushID_SE)
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mov pc, lr
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/*
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* Cache functions
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* Cache operations. For the entire cache we use the set/index
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* operations.
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*/
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ENTRY(arm9_cache_flushID)
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mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
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s_max .req r0
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i_max .req r1
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s_inc .req r2
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i_inc .req r3
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ENTRY_NP(arm9_icache_sync_range)
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ldr ip, .Larm9_line_size
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cmp r1, #0x4000
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bcs .Larm9_icache_sync_all
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ldr ip, [ip]
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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.Larm9_sync_next:
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mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
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mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
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add r0, r0, ip
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subs r1, r1, ip
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bpl .Larm9_sync_next
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mov pc, lr
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ENTRY(arm9_cache_flushID_SE)
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mcr p15, 0, r0, c7, c5, 1 /* flush one entry from I cache */
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mcr p15, 0, r0, c7, c6, 1 /* flush one entry from D cache */
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ENTRY_NP(arm9_icache_sync_all)
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.Larm9_icache_sync_all:
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/*
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* We assume that the code here can never be out of sync with the
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* dcache, so that we can safely flush the Icache and fall through
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* into the Dcache cleaning code.
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*/
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mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
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/* Fall through to clean Dcache. */
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.Larm9_dcache_wb:
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ldr ip, .Larm9_cache_data
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ldmia ip, {s_max, i_max, s_inc, i_inc}
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.Lnext_set:
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orr ip, s_max, i_max
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.Lnext_index:
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mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
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sub ip, ip, i_inc
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tst ip, i_max /* Index 0 is last one */
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bne .Lnext_index /* Next index */
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mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
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subs s_max, s_max, s_inc
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bpl .Lnext_set /* Next set */
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mov pc, lr
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ENTRY(arm9_cache_flushI)
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mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
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mov pc, lr
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.Larm9_line_size:
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.word _C_LABEL(arm_pdcache_line_size)
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ENTRY(arm9_cache_flushI_SE)
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mcr p15, 0, r0, c7, c5, 1 /* flush one entry from I cache */
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ENTRY(arm9_dcache_wb_range)
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ldr ip, .Larm9_line_size
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cmp r1, #0x4000
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bcs .Larm9_dcache_wb
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ldr ip, [ip]
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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.Larm9_wb_next:
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mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
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add r0, r0, ip
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subs r1, r1, ip
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bpl .Larm9_wb_next
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mov pc, lr
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ENTRY(arm9_cache_flushD)
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mcr p15, 0, r0, c7, c6, 0 /* flush D cache */
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ENTRY(arm9_dcache_wbinv_range)
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ldr ip, .Larm9_line_size
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cmp r1, #0x4000
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bcs .Larm9_dcache_wbinv_all
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ldr ip, [ip]
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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.Larm9_wbinv_next:
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mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
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add r0, r0, ip
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subs r1, r1, ip
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bpl .Larm9_wbinv_next
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mov pc, lr
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ENTRY(arm9_cache_flushD_SE)
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mcr p15, 0, r0, c7, c6, 1 /* flush one entry from D cache */
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mov pc, lr
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ENTRY(arm9_cache_cleanID)
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mcr p15, 0, r0, c7, c10, 4
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mov pc, lr
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/*
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* Soft functions
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* Note, we must not invalidate everything. If the range is too big we
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* must use wb-inv of the entire cache.
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*/
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ENTRY(arm9_cache_syncI)
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mcr p15, 0, r0, c7, c7, 0 /* flush I+D caches */
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ENTRY(arm9_dcache_inv_range)
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ldr ip, .Larm9_line_size
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cmp r1, #0x4000
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bcs .Larm9_dcache_wbinv_all
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ldr ip, [ip]
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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.Larm9_inv_next:
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mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */
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add r0, r0, ip
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subs r1, r1, ip
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bpl .Larm9_inv_next
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mov pc, lr
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ENTRY_NP(arm9_cache_flushID_rng)
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b _C_LABEL(arm9_cache_flushID)
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ENTRY(arm9_idcache_wbinv_range)
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ldr ip, .Larm9_line_size
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cmp r1, #0x4000
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bcs .Larm9_idcache_wbinv_all
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ldr ip, [ip]
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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.Larm9_id_wbinv_next:
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mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
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mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
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add r0, r0, ip
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subs r1, r1, ip
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bpl .Larm9_id_wbinv_next
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mov pc, lr
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ENTRY_NP(arm9_cache_flushD_rng)
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/* Same as above, but D cache only */
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b _C_LABEL(arm9_cache_flushD)
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ENTRY_NP(arm9_idcache_wbinv_all)
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.Larm9_idcache_wbinv_all:
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/*
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* We assume that the code here can never be out of sync with the
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* dcache, so that we can safely flush the Icache and fall through
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* into the Dcache purging code.
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*/
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mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
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/* Fall through to purge Dcache. */
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ENTRY_NP(arm9_cache_syncI_rng)
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/* Similarly, for I cache sync */
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b _C_LABEL(arm9_cache_syncI)
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ENTRY(arm9_dcache_wbinv_all)
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.Larm9_dcache_wbinv_all:
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ldr ip, .Larm9_cache_data
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ldmia ip, {s_max, i_max, s_inc, i_inc}
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.Lnext_set_inv:
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orr ip, s_max, i_max
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.Lnext_index_inv:
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mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
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sub ip, ip, i_inc
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tst ip, i_max /* Index 0 is last one */
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bne .Lnext_index_inv /* Next index */
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mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
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subs s_max, s_max, s_inc
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bpl .Lnext_set_inv /* Next set */
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mov pc, lr
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.Larm9_cache_data:
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.word _C_LABEL(arm9_dcache_sets_max)
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/*
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* Context switch.
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@ -134,3 +233,24 @@ ENTRY(arm9_context_switch)
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nop
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nop
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mov pc, lr
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.bss
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/* XXX The following macros should probably be moved to asm.h */
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#define _DATA_OBJECT(x) .globl x; .type x,_ASM_TYPE_OBJECT; x:
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#define C_OBJECT(x) _DATA_OBJECT(_C_LABEL(x))
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/*
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* Parameters for the cache cleaning code. Note that the order of these
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* four variables is assumed in the code above. Hence the reason for
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* declaring them in the assembler file.
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*/
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.align 0
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C_OBJECT(arm9_dcache_sets_max)
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.space 4
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C_OBJECT(arm9_dcache_index_max)
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.space 4
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C_OBJECT(arm9_dcache_sets_inc)
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.space 4
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C_OBJECT(arm9_dcache_index_inc)
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.space 4
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@ -1,4 +1,4 @@
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/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */
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/* $NetBSD: cpufunc.h,v 1.30 2004/01/26 15:54:16 rearnsha Exp $ */
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/*
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* Copyright (c) 1997 Mark Brinicombe.
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@ -313,23 +313,25 @@ void arm9_setttb __P((u_int));
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void arm9_tlb_flushID_SE __P((u_int va));
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void arm9_cache_flushID __P((void));
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void arm9_cache_flushID_SE __P((u_int));
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void arm9_cache_flushI __P((void));
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void arm9_cache_flushI_SE __P((u_int));
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void arm9_cache_flushD __P((void));
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void arm9_cache_flushD_SE __P((u_int));
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void arm9_icache_sync_all __P((void));
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void arm9_icache_sync_range __P((vaddr_t, vsize_t));
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void arm9_cache_cleanID __P((void));
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void arm9_dcache_wbinv_all __P((void));
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void arm9_dcache_wbinv_range __P((vaddr_t, vsize_t));
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void arm9_dcache_inv_range __P((vaddr_t, vsize_t));
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void arm9_dcache_wb_range __P((vaddr_t, vsize_t));
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void arm9_cache_syncI __P((void));
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void arm9_cache_flushID_rng __P((vaddr_t, vsize_t));
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void arm9_cache_flushD_rng __P((vaddr_t, vsize_t));
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void arm9_cache_syncI_rng __P((vaddr_t, vsize_t));
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void arm9_idcache_wbinv_all __P((void));
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void arm9_idcache_wbinv_range __P((vaddr_t, vsize_t));
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void arm9_context_switch __P((void));
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void arm9_setup __P((char *string));
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extern unsigned arm9_dcache_sets_max;
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extern unsigned arm9_dcache_sets_inc;
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extern unsigned arm9_dcache_index_max;
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extern unsigned arm9_dcache_index_inc;
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#endif
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#ifdef CPU_ARM10
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Loading…
Reference in New Issue