Move the alignment fault enable/disable code into macroes to avoid
needless duplication. Additionally, merge AST handling into the same code. exception.S and the generic irq_dispatch.S routines have been updated to use the macroes. XXX: I have patches for the non-generic IRQ dispatch routines, but they need testing by someone with hardware.
This commit is contained in:
scw
parent
4101558b6e
commit
7a55b436b2
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@ -1,4 +1,4 @@
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/* $NetBSD: exception.S,v 1.11 2003/10/26 11:34:29 scw Exp $ */
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/* $NetBSD: exception.S,v 1.12 2003/10/30 08:57:24 scw Exp $ */
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/*
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* Copyright (c) 1994-1997 Mark Brinicombe.
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@ -46,9 +46,6 @@
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*/
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#include "opt_ipkdb.h"
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#include "opt_compat_netbsd.h"
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#include "opt_execfmt.h"
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#include "opt_multiprocessor.h"
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#include <machine/asm.h>
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#include <machine/cpu.h>
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#include <machine/frame.h>
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@ -57,46 +54,7 @@
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.text
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.align 0
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.Lastpending:
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.word _C_LABEL(astpending)
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#if defined(COMPAT_15) && defined(EXEC_AOUT)
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.Lcpufuncs:
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.word _C_LABEL(cpufuncs)
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#ifndef MULTIPROCESSOR
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.Lcurpcb:
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.word _C_LABEL(curpcb)
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.Lcpu_info_store:
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.word _C_LABEL(cpu_info_store)
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#define GET_CURPCB \
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ldr r1, .Lcurpcb ;\
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ldr r1, [r1]
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#define GET_CPUINFO \
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ldr r0, .Lcpu_info_store
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#else
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.Lcpu_info:
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.word _C_LABEL(cpu_info)
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#define GET_CURPCB \
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ldr r4, .Lcpu_info ;\
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bl _C_LABEL(cpu_number) ;\
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ldr r0, [r4, r0, lsl #2] ;\
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ldr r1, [r0, #CI_CURPCB]
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#define GET_CPUINFO /* nothing to do */
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#endif
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#define ENABLE_ALIGNMENT_FAULTS \
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GET_CURPCB ;\
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cmp r1, #0x00 /* curpcb NULL? ;\
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ldrne r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\
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tstne r1, #PCB_NOALIGNFLT ;\
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beq 1f /* Alignment faults already enabled */ ;\
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GET_CPUINFO ;\
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ldr r2, .Lcpufuncs ;\
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ldr r1, [r0, #CI_CTRL] /* Fetch control register */ ;\
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mov r0, #-1 ;\
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mov lr, pc ;\
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ldr pc, [r2, #CF_CONTROL] /* Enable alignment faults */ ;\
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1:
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#endif /* COMPAT_15 && EXEC_AOUT */
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AST_ALIGNMENT_FAULT_LOCALS
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/*
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* General exception exit handler
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@ -106,72 +64,15 @@
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* Interrupts are disabled at suitable points to avoid ASTs
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* being posted between testing and exit to user mode.
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*
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* This function uses PULLFRAMEFROMSVCANDEXIT thus should
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* This function uses PULLFRAMEFROMSVCANDEXIT and
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* DO_AST_AND_RESTORE_ALIGNMENT_FAULTS thus should
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* only be called if the exception handler used PUSHFRAMEINSVC
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* followed by ENABLE_ALIGNMENT_FAULTS.
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*/
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exception_exit:
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mrs r4, cpsr /* Get CPSR */
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ldr r0, [sp] /* Get the SPSR from stack */
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and r0, r0, #(PSR_MODE) /* Test for USR32 mode before the AST */
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teq r0, #(PSR_USR32_MODE)
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bne .Ldo_exit /* Not USR mode so no AST delivery */
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ldr r5, .Lastpending /* Get address of astpending */
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#if defined(COMPAT_15) && defined(EXEC_AOUT) && !defined(MULTIPROCESSOR)
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ldr r6, .Lcurpcb
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ldr r7, .Lcpu_info_store
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#endif
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Lexception_exit_loop:
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orr r0, r4, #(I32_bit) /* Block IRQs */
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msr cpsr_all, r0
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ldr r1, [r5] /* Do we have an AST pending */
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teq r1, #0x00000000
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bne .Ldo_ast
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#if defined(COMPAT_15) && defined(EXEC_AOUT)
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/* Disable alignment faults for the process, if necessary. */
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#ifdef MULTIPROCESSOR
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ldr r7, .Lcpu_info
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bl _C_LABEL(cpu_number)
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ldr r7, [r7, r0, lsl #2]
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ldr r1, [r7, #CI_CURPCB]
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#else
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ldr r1, [r6]
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#endif
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cmp r1, #0x00 /* curpcb NULL? */
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ldrne r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */
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tstne r1, #PCB_NOALIGNFLT
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beq 1f /* Keep alignment faults enabled */
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ldr r1, [r7, #CI_CTRL] /* Fetch control register */
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ldr r2, .Lcpufuncs
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mov r0, #-1
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bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable alignment faults */
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mov lr, pc
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ldr pc, [r2, #CF_CONTROL] /* Set the new control register value */
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1:
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#endif
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PULLFRAMEFROMSVCANDEXIT /* No AST so exit */
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.Ldo_ast:
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mov r1, #0x00000000 /* Clear ast pending */
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str r1, [r5]
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msr cpsr_all, r4 /* Restore interrupts */
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mov r0, sp /* arg 0 = trap frame */
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bl _C_LABEL(ast) /* call the AST handler */
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b Lexception_exit_loop /* Try and exit again */
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.Ldo_exit:
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orr r0, r4, #(I32_bit) /* Disable interrupts */
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msr cpsr_all, r0
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PULLFRAMEFROMSVCANDEXIT /* Restore the trap frame and exit */
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DO_AST_AND_RESTORE_ALIGNMENT_FAULTS
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PULLFRAMEFROMSVCANDEXIT
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/*
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* reset_entry:
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@ -194,65 +95,15 @@ Lreset_panicmsg:
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*/
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ASENTRY_NP(swi_entry)
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PUSHFRAME
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#if defined(COMPAT_15) && defined(EXEC_AOUT)
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ENABLE_ALIGNMENT_FAULTS
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#endif
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mov r0, sp /* Pass the frame to any function */
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bl _C_LABEL(swi_handler) /* It's a SWI ! */
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ldr r5, .Lastpending /* Get address of astpending */
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mrs r4, cpsr /* Get CPSR */
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#if defined(COMPAT_15) && defined(EXEC_AOUT) && !defined(MULTIPROCESSOR)
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ldr r6, .Lcurpcb
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ldr r7, .Lcpu_info_store
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#endif
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.Lswi_exit_loop:
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orr r0, r4, #(I32_bit) /* Disable IRQs */
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msr cpsr_all, r0
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ldr r1, [r5] /* Do we have an AST pending */
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teq r1, #0x00000000
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bne .Ldo_swi_ast
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#if defined(COMPAT_15) && defined(EXEC_AOUT)
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/* Disable alignment faults for the process, if necessary. */
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#ifdef MULTIPROCESSOR
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ldr r7, .Lcpu_info
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bl _C_LABEL(cpu_number)
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ldr r7, [r7, r0, lsl #2]
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ldr r1, [r7, #CI_CURPCB]
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#else
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ldr r1, [r6]
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#endif
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cmp r1, #0x00 /* curpcb NULL? */
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ldrne r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */
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tstne r1, #PCB_NOALIGNFLT
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beq 1f /* Keep alignment faults enabled */
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ldr r1, [r7, #CI_CTRL] /* Fetch control register */
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ldr r2, .Lcpufuncs
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mov r0, #-1
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bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable alignment faults */
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mov lr, pc
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ldr pc, [r2, #CF_CONTROL] /* Set the new control register value */
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1:
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#endif
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DO_AST_AND_RESTORE_ALIGNMENT_FAULTS
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PULLFRAME
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movs pc, lr /* Exit */
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.Ldo_swi_ast:
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mov r1, #0x00000000 /* Clear ast pending */
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str r1, [r5]
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msr cpsr_all, r4 /* Restore interrupts */
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mov r0, sp /* arg 0 = trap frame */
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bl _C_LABEL(ast) /* call the AST handler */
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b .Lswi_exit_loop /* Try and exit again */
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/*
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* prefetch_abort_entry:
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*
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@ -262,17 +113,13 @@ ASENTRY_NP(prefetch_abort_entry)
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sub lr, lr, #0x00000004 /* Adjust the lr */
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PUSHFRAMEINSVC
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#if defined(COMPAT_15) && defined(EXEC_AOUT)
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ENABLE_ALIGNMENT_FAULTS
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#endif
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mov r0, sp /* pass the stack pointer as r0 */
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adr lr, exception_exit
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ldr r1, Lprefetch_abort_handler_address
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adr lr, exception_exit
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mov r0, sp /* pass the stack pointer as r0 */
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ldr pc, [r1]
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Lprefetch_abort_handler_address:
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.word _C_LABEL(prefetch_abort_handler_address)
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@ -301,19 +148,11 @@ ASENTRY_NP(data_abort_entry)
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PUSHFRAMEINSVC /* Push trap frame and switch */
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/* to SVC32 mode */
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#if defined(COMPAT_15) && defined(EXEC_AOUT)
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and r0, r0, #(PSR_MODE) /* Test for USR32 mode (r0 = spsr_all)*/
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teq r0, #(PSR_USR32_MODE)
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bne 99f /* Not USR mode so skip AFLT check */
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ENABLE_ALIGNMENT_FAULTS
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99:
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#endif
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mov r0, sp /* pass the stack pointer as r0 */
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adr lr, exception_exit
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ldr r1, Ldata_abort_handler_address
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adr lr, exception_exit
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mov r0, sp /* pass the stack pointer as r0 */
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ldr pc, [r1]
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Ldata_abort_handler_address:
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@ -417,38 +256,11 @@ ASENTRY_NP(undefined_entry)
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* Now to IPKDB.
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*/
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.Lgoipkdb:
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#if defined(COMPAT_15) && defined(EXEC_AOUT)
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ENABLE_ALIGNMENT_FAULTS
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#endif
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mov r0, sp
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bl _C_LABEL(ipkdb_trap_glue)
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ldr r1, .Lipkdb_trap_return
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str r0,[r1]
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#if defined(COMPAT_15) && defined(EXEC_AOUT)
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#ifdef MULTIPROCESSOR
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ldr r7, .Lcpu_info
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bl _C_LABEL(cpu_number)
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ldr r7, [r7, r0, lsl #2]
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ldr r1, [r7, #CI_CURPCB]
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#else
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ldr r6, .Lcurpcb
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ldr r7, .Lcpu_info_store
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ldr r1, [r6]
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#endif
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cmp r1, #0x00 /* curpcb NULL? */
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ldrne r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */
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tstne r1, #PCB_NOALIGNFLT
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beq 1f /* Keep alignment faults enabled */
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ldr r1, [r7, #CI_CTRL] /* Fetch control register */
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ldr r2, .Lcpufuncs
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mov r0, #-1
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bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable alignment faults */
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mov lr, pc
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ldr pc, [r2, #CF_CONTROL] /* Set the new control register value */
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1:
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#endif
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/*
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* Have to load all registers from the stack.
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*
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@ -530,17 +342,11 @@ Lundefined_handler_indirection:
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ENTRY_NP(undefinedinstruction_bounce)
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PUSHFRAMEINSVC
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#if defined(COMPAT_15) && defined(EXEC_AOUT)
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and r0, r0, #(PSR_MODE) /* Test for USR32 mode (r0 = spsr_all)*/
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teq r0, #(PSR_USR32_MODE)
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bne 99f /* Not USR mode so skip AFLT check */
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ENABLE_ALIGNMENT_FAULTS
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99:
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#endif
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mov r0, sp
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bl _C_LABEL(undefinedinstruction)
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b exception_exit
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mov r0, sp
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adr lr, exception_exit
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b _C_LABEL(undefinedinstruction)
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.data
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.align 0
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@ -1,4 +1,4 @@
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/* $NetBSD: irq_dispatch.S,v 1.4 2003/10/26 11:34:29 scw Exp $ */
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/* $NetBSD: irq_dispatch.S,v 1.5 2003/10/30 08:57:24 scw Exp $ */
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/*
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* Copyright (c) 2002 Fujitsu Component Limited
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@ -73,10 +73,6 @@
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#include <machine/cpu.h>
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#include <machine/frame.h>
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#include "opt_compat_netbsd.h"
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#include "opt_execfmt.h"
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#include "opt_multiprocessor.h"
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#include "opt_arm_intr_impl.h"
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#ifdef ARM_INTR_IMPL
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#include ARM_INTR_IMPL
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@ -88,44 +84,6 @@
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#error ARM_IRQ_HANDLER not defined
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#endif
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#if defined(COMPAT_15) && defined(EXEC_AOUT)
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.Lcpufuncs:
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.word _C_LABEL(cpufuncs)
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#ifndef MULTIPROCESSOR
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.Lcurpcb:
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.word _C_LABEL(curpcb)
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.Lcpu_info_store:
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.word _C_LABEL(cpu_info_store)
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#define GET_CURPCB \
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ldr r1, .Lcurpcb ;\
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ldr r1, [r1]
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#define GET_CPUINFO \
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ldr r0, .Lcpu_info_store
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#else
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.Lcpu_info:
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.word _C_LABEL(cpu_info)
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#define GET_CURPCB \
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ldr r4, .Lcpu_info ;\
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bl _C_LABEL(cpu_number) ;\
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ldr r0, [r4, r0, lsl #2] ;\
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ldr r1, [r0, #CI_CURPCB]
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#define GET_CPUINFO /* nothing to do */
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#endif
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#define ENABLE_ALIGNMENT_FAULTS \
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GET_CURPCB ;\
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cmp r1, #0x00 /* curpcb NULL? */ ;\
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ldrne r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\
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tstne r1, #PCB_NOALIGNFLT ;\
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beq 1f /* Alignment faults already enabled */ ;\
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GET_CPUINFO ;\
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ldr r2, .Lcpufuncs ;\
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ldr r1, [r0, #CI_CTRL] /* Fetch control register */ ;\
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mov r0, #-1 ;\
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mov lr, pc ;\
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ldr pc, [r2, #CF_CONTROL] /* Enable alignment faults */ ;\
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1:
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#endif /* COMPAT_15 && EXEC_AOUT */
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/*
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* irq_entry:
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* Main entry point for the IRQ vector. This is a generic version
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@ -133,23 +91,16 @@
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*/
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.text
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.align 0
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.Lastpending:
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.word _C_LABEL(astpending)
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.Lcurrent_intr_depth:
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.word _C_LABEL(current_intr_depth)
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AST_ALIGNMENT_FAULT_LOCALS
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ASENTRY_NP(irq_entry)
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sub lr, lr, #0x00000004 /* Adjust the lr */
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PUSHFRAMEINSVC /* Push an interrupt frame */
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#if defined(COMPAT_15) && defined(EXEC_AOUT)
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and r0, r0, #(PSR_MODE) /* Test for USR32 mode (r0 = spsr_all)*/
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teq r0, #(PSR_USR32_MODE)
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bne 99f /* Not USR mode so skip AFLT check */
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ENABLE_ALIGNMENT_FAULTS
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99:
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#endif
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/*
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* Increment the interrupt nesting depth and call the interrupt
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@ -174,66 +125,10 @@ ASENTRY_NP(irq_entry)
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*/
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str r6, [r5]
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/*
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* If we're returning to user mode, check for pending ASTs.
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*/
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ldr r0, [sp] /* Get the SPSR from stack */
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and r0, r0, #(PSR_MODE) /* Test for USR32 mode before the IRQ */
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teq r0, #(PSR_USR32_MODE)
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bne .Lirq_do_exit /* Nope, get out now */
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ldr r5, .Lastpending
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#if defined(COMPAT_15) && defined(EXEC_AOUT) && !defined(MULTIPROCESSOR)
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ldr r6, .Lcurpcb
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ldr r7, .Lcpu_info_store
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#endif
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.Lirq_ast_loop:
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ldr r1, [r5] /* Do we have an AST pending? */
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teq r1, #0x00000000
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bne .Lirq_do_ast /* Yup. Go deal with it */
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#if defined(COMPAT_15) && defined(EXEC_AOUT)
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/* Disable alignment faults for the process, if necessary. */
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#ifdef MULTIPROCESSOR
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ldr r7, .Lcpu_info
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bl _C_LABEL(cpu_number)
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ldr r7, [r7, r0, lsl #2]
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ldr r1, [r7, #CI_CURPCB]
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#else
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ldr r1, [r6]
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#endif
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cmp r1, #0x00 /* curpcb NULL? */
|
||||
ldrne r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */
|
||||
tstne r1, #PCB_NOALIGNFLT
|
||||
beq 1f /* Keep alignment faults enabled */
|
||||
ldr r1, [r7, #CI_CTRL] /* Fetch control register */
|
||||
ldr r2, .Lcpufuncs
|
||||
mov r0, #-1
|
||||
bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable alignment faults */
|
||||
mov lr, pc
|
||||
ldr pc, [r2, #CF_CONTROL] /* Set the new control register value */
|
||||
1:
|
||||
#endif
|
||||
|
||||
.Lirq_do_exit:
|
||||
DO_AST_AND_RESTORE_ALIGNMENT_FAULTS
|
||||
PULLFRAMEFROMSVCANDEXIT
|
||||
movs pc, lr /* Exit */
|
||||
|
||||
.Lirq_do_ast:
|
||||
mov r1, #0x00000000
|
||||
str r1, [r5] /* Clear astpending */
|
||||
|
||||
mrs r4, cpsr /* save CPSR */
|
||||
bic r0, r4, #(I32_bit) /* Enable IRQs */
|
||||
msr cpsr_c, r0
|
||||
|
||||
mov r0, sp
|
||||
bl _C_LABEL(ast) /* ast(frame) */
|
||||
|
||||
msr cpsr_c, r4 /* Disable IRQs */
|
||||
b .Lirq_ast_loop /* Check for more ASTs */
|
||||
|
||||
.bss
|
||||
.align 0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: frame.h,v 1.6 2003/10/23 08:59:10 scw Exp $ */
|
||||
/* $NetBSD: frame.h,v 1.7 2003/10/30 08:57:24 scw Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1994-1997 Mark Brinicombe.
|
||||
|
|
@ -106,6 +106,161 @@ void validate_trapframe __P((trapframe_t *, int));
|
|||
|
||||
#else /* _LOCORE */
|
||||
|
||||
#include "opt_compat_netbsd.h"
|
||||
#include "opt_execfmt.h"
|
||||
#include "opt_multiprocessor.h"
|
||||
|
||||
/*
|
||||
* AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS
|
||||
* These are used in order to support dynamic enabling/disabling of
|
||||
* alignment faults when executing old a.out ARM binaries.
|
||||
*/
|
||||
#if defined(COMPAT_15) && defined(EXEC_AOUT)
|
||||
#ifndef MULTIPROCESSOR
|
||||
|
||||
/*
|
||||
* Local variables needed by the AST/Alignment Fault macroes
|
||||
*/
|
||||
#define AST_ALIGNMENT_FAULT_LOCALS \
|
||||
.Laflt_astpending: ;\
|
||||
.word _C_LABEL(astpending) ;\
|
||||
.Laflt_cpufuncs: ;\
|
||||
.word _C_LABEL(cpufuncs) ;\
|
||||
.Laflt_curpcb: ;\
|
||||
.word _C_LABEL(curpcb) ;\
|
||||
.Laflt_cpu_info_store: ;\
|
||||
.word _C_LABEL(cpu_info_store)
|
||||
|
||||
#define GET_CURPCB_ENTER \
|
||||
ldr r1, .Laflt_curpcb ;\
|
||||
ldr r1, [r1]
|
||||
|
||||
#define GET_CPUINFO_ENTER \
|
||||
ldr r0, .Laflt_cpu_info_store
|
||||
|
||||
#define GET_CURPCB_EXIT \
|
||||
ldr r1, .Laflt_curpcb ;\
|
||||
ldr r2, .Laflt_cpu_info_store ;\
|
||||
ldr r1, [r1]
|
||||
|
||||
#else /* !MULTIPROCESSOR */
|
||||
|
||||
#define AST_ALIGNMENT_FAULT_LOCALS \
|
||||
.Laflt_astpending: ;\
|
||||
.word _C_LABEL(astpending) ;\
|
||||
.Laflt_cpufuncs: ;\
|
||||
.word _C_LABEL(cpufuncs) ;\
|
||||
.Laflt_cpu_info: ;\
|
||||
.word _C_LABEL(cpu_info)
|
||||
|
||||
#define GET_CURPCB_ENTER \
|
||||
ldr r4, .Laflt_cpu_info ;\
|
||||
bl _C_LABEL(cpu_number) ;\
|
||||
ldr r0, [r4, r0, lsl #2] ;\
|
||||
ldr r1, [r0, #CI_CURPCB]
|
||||
|
||||
#define GET_CPUINFO_ENTER /* nothing to do */
|
||||
|
||||
#define GET_CURPCB_EXIT \
|
||||
ldr r7, .Laflt_cpu_info ;\
|
||||
bl _C_LABEL(cpu_number) ;\
|
||||
ldr r2, [r7, r0, lsl #2] ;\
|
||||
ldr r1, [r2, #CI_CURPCB]
|
||||
#endif /* MULTIPROCESSOR */
|
||||
|
||||
/*
|
||||
* This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at
|
||||
* the top of interrupt/exception handlers.
|
||||
*
|
||||
* When invoked, r0 *must* contain the value of SPSR on the current
|
||||
* trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS
|
||||
* is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME.
|
||||
*/
|
||||
#define ENABLE_ALIGNMENT_FAULTS \
|
||||
and r0, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\
|
||||
teq r0, #(PSR_USR32_MODE) ;\
|
||||
bne 1f /* Not USR mode skip AFLT */ ;\
|
||||
GET_CURPCB_ENTER /* r1 = curpcb */ ;\
|
||||
cmp r1, #0x00 /* curpcb NULL? */ ;\
|
||||
ldrne r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\
|
||||
tstne r1, #PCB_NOALIGNFLT ;\
|
||||
beq 1f /* AFLTs already enabled */ ;\
|
||||
GET_CPUINFO_ENTER /* r0 = cpuinfo */ ;\
|
||||
ldr r2, .Laflt_cpufuncs ;\
|
||||
ldr r1, [r0, #CI_CTRL] /* Fetch control register */ ;\
|
||||
mov r0, #-1 ;\
|
||||
mov lr, pc ;\
|
||||
ldr pc, [r2, #CF_CONTROL] /* Enable alignment faults */ ;\
|
||||
1:
|
||||
|
||||
/*
|
||||
* This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or
|
||||
* PULLFRAME at the end of interrupt/exception handlers.
|
||||
*/
|
||||
#define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \
|
||||
mrs r4, cpsr /* save CPSR */ ;\
|
||||
ldr r0, [sp] /* Get the SPSR from stack */ ;\
|
||||
orr r4, r4, #(I32_bit) /* Disable IRQs */ ;\
|
||||
msr cpsr_c, r4 ;\
|
||||
and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\
|
||||
teq r0, #(PSR_USR32_MODE) ;\
|
||||
ldreq r5, .Laflt_astpending ;\
|
||||
bne 3f /* Nope, get out now */ ;\
|
||||
1: ldr r1, [r5] /* Pending AST? */ ;\
|
||||
teq r1, #0x00000000 ;\
|
||||
bne 2f /* Yup. Go deal with it */ ;\
|
||||
GET_CURPCB_EXIT /* r1 = curpcb, r2 = cpuinfo */ ;\
|
||||
cmp r1, #0x00 /* curpcb NULL? */ ;\
|
||||
ldrne r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\
|
||||
tstne r1, #PCB_NOALIGNFLT ;\
|
||||
beq 3f /* Keep AFLTs enabled */ ;\
|
||||
ldr r1, [r2, #CI_CTRL] /* Fetch control register */ ;\
|
||||
ldr r2, .Laflt_cpufuncs ;\
|
||||
mov r0, #-1 ;\
|
||||
bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable AFLTs */ ;\
|
||||
adr lr, 3f ;\
|
||||
ldr pc, [r2, #CF_CONTROL] /* Set new CTRL reg value */ ;\
|
||||
2: mov r1, #0x00000000 ;\
|
||||
str r1, [r5] /* Clear astpending */ ;\
|
||||
bic r0, r4, #(I32_bit) /* Enable IRQs */ ;\
|
||||
msr cpsr_c, r0 ;\
|
||||
mov r0, sp ;\
|
||||
bl _C_LABEL(ast) /* ast(frame) */ ;\
|
||||
msr cpsr_c, r4 /* Disable IRQs */ ;\
|
||||
b 1b /* Check for more ASTs */ ;\
|
||||
3:
|
||||
|
||||
#else /* !(COMPAT_15 && EXEC_AOUT) */
|
||||
|
||||
#define AST_ALIGNMENT_FAULT_LOCALS ;\
|
||||
.Laflt_astpending: ;\
|
||||
.word _C_LABEL(astpending)
|
||||
|
||||
#define ENABLE_ALIGNMENT_FAULTS /* nothing */
|
||||
|
||||
#define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \
|
||||
mrs r4, cpsr /* save CPSR */ ;\
|
||||
ldr r0, [sp] /* Get the SPSR from stack */ ;\
|
||||
orr r4, r4, #(I32_bit) /* Disable IRQs */ ;\
|
||||
msr cpsr_c, r4 ;\
|
||||
and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\
|
||||
teq r0, #(PSR_USR32_MODE) ;\
|
||||
ldreq r5, .Laflt_astpending ;\
|
||||
bne 2f /* Nope, get out now */ ;\
|
||||
1: ldr r1, [r5] /* Pending AST? */ ;\
|
||||
teq r1, #0x00000000 ;\
|
||||
beq 2f /* Nope. Just bail */ ;\
|
||||
mov r1, #0x00000000 ;\
|
||||
str r1, [r5] /* Clear astpending */ ;\
|
||||
bic r0, r4, #(I32_bit) /* Enable IRQs */ ;\
|
||||
msr cpsr_c, r0 ;\
|
||||
mov r0, sp ;\
|
||||
bl _C_LABEL(ast) /* ast(frame) */ ;\
|
||||
msr cpsr_c, r4 /* Disable IRQs */ ;\
|
||||
b 1b /* Check for more ASTs */ ;\
|
||||
2:
|
||||
#endif /* COMPAT_15 && EXEC_AOUT */
|
||||
|
||||
/*
|
||||
* ASM macros for pushing and pulling trapframes from the stack
|
||||
*
|
||||
|
|
@ -129,7 +284,7 @@ void validate_trapframe __P((trapframe_t *, int));
|
|||
stmia r0, {r13-r14}^; /* Push the user mode registers */ \
|
||||
mov r0, r0; /* NOP for previous instruction */ \
|
||||
mrs r0, spsr_all; /* Put the SPSR on the stack */ \
|
||||
str r0, [sp, #-4]!;
|
||||
str r0, [sp, #-4]!
|
||||
|
||||
/*
|
||||
* PULLFRAME - macro to pull a trap frame from the stack in the current mode
|
||||
|
|
@ -142,7 +297,7 @@ void validate_trapframe __P((trapframe_t *, int));
|
|||
ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
|
||||
mov r0, r0; /* NOP for previous instruction */ \
|
||||
add sp, sp, #(4*17); /* Adjust the stack pointer */ \
|
||||
ldr lr, [sp], #0x0004; /* Pull the return address */
|
||||
ldr lr, [sp], #0x0004 /* Pull the return address */
|
||||
|
||||
/*
|
||||
* PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode
|
||||
|
|
|
|||
Loading…
Reference in New Issue