various bug fixes. Now SMDK2410 evboard boots up to single user mode
using install ramdisk.
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bsh
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490a557f57
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3410ad1777
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@ -1,4 +1,4 @@
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/* $NetBSD: s3c2410_intr.c,v 1.1 2003/07/31 19:49:42 bsh Exp $ */
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/* $NetBSD: s3c2410_intr.c,v 1.2 2003/08/04 12:41:44 bsh Exp $ */
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/*
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* Copyright (c) 2003 Genetec corporation. All rights reserved.
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@ -35,7 +35,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: s3c2410_intr.c,v 1.1 2003/07/31 19:49:42 bsh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: s3c2410_intr.c,v 1.2 2003/08/04 12:41:44 bsh Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -80,13 +80,7 @@ static const int si_to_ipl[SI_NQUEUES] = {
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IPL_SOFTSERIAL, /* SI_SOFTSERIAL */
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};
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/*
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* Clearing interrupt pending bits affects some built-in
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* peripherals. For example, IIC starts transmitting next data when
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* its interrupt pending bit is cleared.
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* We need to leave those bits to peripheral handlers.
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*/
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#define PENDING_CLEAR_MASK (~(1<<S3C24X0_INT_IIC))
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#define PENDING_CLEAR_MASK (~0)
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/*
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* called from irq_entry.
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@ -101,23 +95,31 @@ s3c2410_irq_handler(struct clockframe *frame)
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saved_spl_level = current_spl_level;
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#ifdef DIAGNOSTIC
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if (current_intr_depth > 10)
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panic("nested intr too deep");
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#endif
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while ((irqbits = icreg(INTCTL_INTPND)) != 0) {
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/* XXX: Use INTOFFSET register */
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/* Note: Only one bit in INTPND register is set */
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for (irqno = ICU_LEN-1; irqno >= 0; --irqno)
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if (irqbits & (1<<irqno))
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break;
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irqno = icreg(INTCTL_INTOFFSET);
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if (irqno < 0)
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#ifdef DIAGNOSTIC
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if (__predict_false((irqbits & (1<<irqno)) == 0)) {
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/* This shouldn't happen */
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printf("INTOFFSET=%d, INTPND=%x\n", irqno, irqbits);
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break;
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}
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#endif
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/* raise spl to stop interrupts of lower priorities */
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if (saved_spl_level < handler[irqno].level)
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s3c2xx0_setipl(handler[irqno].level);
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/* clear pending bit */
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icreg(INTCTL_SRCPND) = PENDING_CLEAR_MASK & (1 << irqno);
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icreg(INTCTL_INTPND) = PENDING_CLEAR_MASK & (1 << irqno);
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enable_interrupts(I32_bit); /* allow nested interrupts */
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@ -129,11 +131,13 @@ s3c2410_irq_handler(struct clockframe *frame)
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/* restore spl to that was when this interrupt happen */
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s3c2xx0_setipl(saved_spl_level);
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}
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if (get_pending_softint())
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s3c2xx0_do_pending(1);
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}
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/*
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@ -142,19 +146,23 @@ s3c2410_irq_handler(struct clockframe *frame)
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static int
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cascade_irq_handler(void *cookie)
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{
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int index = (int)cookie;
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int index = (int)cookie - 1;
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uint32_t irqbits;
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int irqno, i;
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int save = disable_interrupts(I32_bit);
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irqbits = icreg(INTCTL_SUBSRCPND) & (0x07 << (3*index));
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KASSERT(0 <= index && index <= 3);
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irqbits = icreg(INTCTL_SUBSRCPND) &
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~icreg(INTCTL_INTSUBMSK) & (0x07 << (3*index));
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for (irqno = 3*index; irqbits; ++irqno) {
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if ((irqbits & (1<<irqno)) == 0)
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continue;
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/* clear pending bit */
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icreg(INTCTL_SRCPND) = PENDING_CLEAR_MASK & (1 << irqno);
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irqbits &= ~(1<<irqno);
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icreg(INTCTL_SUBSRCPND) = (1 << irqno);
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/* allow nested interrupts. SPL is already set
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* correctly by main handler. */
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@ -180,7 +188,7 @@ static const u_char s3c24x0_ist[] = {
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EXTINTR_BOTH,
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};
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const static uint8_t subirq_to_main[] = {
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static const uint8_t subirq_to_main[] = {
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S3C2410_INT_UART0,
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S3C2410_INT_UART0,
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S3C2410_INT_UART0,
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@ -213,24 +221,29 @@ s3c24x0_intr_establish(int irqno, int level, int type,
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if (irqno >= S3C2410_SUBIRQ_MIN) {
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/* cascaded interrupts. */
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int main_irqno;
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int i = (irqno - S3C2410_SUBIRQ_MIN);
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/* unmask it in submask register */
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icreg(INTCTL_INTSUBMSK) &= ~(1<<(irqno - S3C2410_SUBIRQ_MIN));
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main_irqno = subirq_to_main[i];
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restore_interrupts(save);
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main_irqno = subirq_to_main[irqno - S3C2410_SUBIRQ_MIN];
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/* establish main irq if first time */
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/* establish main irq if first time
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* be careful that cookie shouldn't be 0 */
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if (handler[main_irqno].func != cascade_irq_handler)
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s3c24x0_intr_establish(main_irqno, level, type,
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cascade_irq_handler, (void *)(irqno/3));
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cascade_irq_handler, (void *)((i/3) + 1));
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/* unmask it in submask register */
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icreg(INTCTL_INTSUBMSK) &= ~(1<<i);
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restore_interrupts(save);
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return &handler[irqno];
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}
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s3c2xx0_update_intr_masks(irqno, level);
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/*
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* set trigger type for external interrupts 0..3
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* TODO: handle EXTINT[4:23].
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*/
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if (irqno <= S3C24X0_INT_EXT(3)) {
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/*
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* Update external interrupt control
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@ -302,7 +315,11 @@ s3c2410_intr_init(struct s3c24x0_softc *sc)
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s3c2xx0_intr_mask_reg = (uint32_t *)(intctl_base + INTCTL_INTMSK);
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/* clear all pending interrupt */
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icreg(INTCTL_SRCPND) = 0xffffffff;
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icreg(INTCTL_SRCPND) = ~0;
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icreg(INTCTL_INTPND) = ~0;
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/* mask all sub interrupts */
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icreg(INTCTL_INTSUBMSK) = 0x7ff;
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init_interrupt_masks();
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@ -1,4 +1,4 @@
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/* $NetBSD: s3c24x0_clk.c,v 1.1 2003/07/31 19:49:43 bsh Exp $ */
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/* $NetBSD: s3c24x0_clk.c,v 1.2 2003/08/04 12:41:44 bsh Exp $ */
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/*
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* Copyright (c) 2003 Genetec corporation. All rights reserved.
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@ -30,7 +30,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: s3c24x0_clk.c,v 1.1 2003/07/31 19:49:43 bsh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: s3c24x0_clk.c,v 1.2 2003/08/04 12:41:44 bsh Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -270,7 +270,7 @@ cpu_initclocks(void)
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int prescaler, h;
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int pclk = s3c2xx0_softc->sc_pclk;
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bus_space_tag_t iot = sc->sc_sx.sc_iot;
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bus_space_handle_t ioh = ioh;
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bus_space_handle_t ioh = sc->sc_timer_ioh;
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uint32_t reg;
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stathz = STATHZ;
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@ -309,9 +309,9 @@ cpu_initclocks(void)
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bus_space_write_4(iot, ioh, TIMER_TB(3),
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((prescaler - 1) << 16) | (time_constant(stathz) - 1));
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s3c24x0_intr_establish(S3C24X0_INT_TIMER0, IPL_CLOCK,
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s3c24x0_intr_establish(S3C24X0_INT_TIMER4, IPL_CLOCK,
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IST_NONE, hardintr, 0);
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s3c24x0_intr_establish(S3C24X0_INT_TIMER1, IPL_STATCLOCK,
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s3c24x0_intr_establish(S3C24X0_INT_TIMER3, IPL_STATCLOCK,
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IST_NONE, statintr, 0);
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/* set prescaler1 */
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@ -330,6 +330,7 @@ cpu_initclocks(void)
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/* start timers */
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reg = bus_space_read_4(iot, ioh, TIMER_TCON);
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reg &= ~(TCON_MASK(3)|TCON_MASK(4));
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/* load the time constant */
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bus_space_write_4(iot, ioh, TIMER_TCON, reg |
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TCON_MANUALUPDATE(3) | TCON_MANUALUPDATE(4));
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