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pci bus support

This commit is contained in:
ichiro 2003-09-25 14:11:18 +00:00
parent a3b1a08d1e
commit 663ccee1cc
19 changed files with 1798 additions and 404 deletions
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12
sys/arch/arm/xscale/files.ixp425
View File

@ -1,4 +1,4 @@
# $NetBSD: files.ixp425,v 1.2 2003/06/01 01:49:56 ichiro Exp $
# $NetBSD: files.ixp425,v 1.3 2003/09/25 14:11:18 ichiro Exp $
#
# Configuration info for Intel IXP12x0 CPU support
#
@ -16,10 +16,12 @@ file arch/arm/xscale/ixp425_sip_io.c ixpsip
# IXP425 Processor CPU support
# IXP425 PCI bus
device ixpio: pcibus, bus_space_generic
file arch/arm/xscale/ixp425.c ixpio
file arch/arm/xscale/ixp425_io.c ixpio
#file arch/arm/xscale/ixp425_pci.c ixpio
#file arch/arm/xscale/ixp425_pci_dma.c ixpio
file arch/arm/xscale/ixp425.c ixpio
file arch/arm/xscale/ixp425_space.c ixpio
file arch/arm/xscale/ixp425_pci.c ixpio
file arch/arm/xscale/ixp425_pci_space.c ixpio
file arch/arm/xscale/ixp425_pci_dma.c ixpio
file arch/arm/xscale/ixp425_pci_asm.S ixpio
# clock device
device ixpclk

137
sys/arch/arm/xscale/ixp425.c
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@ -1,4 +1,4 @@
/* $NetBSD: ixp425.c,v 1.4 2003/07/02 11:02:28 ichiro Exp $ */
/* $NetBSD: ixp425.c,v 1.5 2003/09/25 14:11:18 ichiro Exp $ */
/*
* Copyright (c) 2003
@ -34,7 +34,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ixp425.c,v 1.4 2003/07/02 11:02:28 ichiro Exp $");
__KERNEL_RCSID(0, "$NetBSD: ixp425.c,v 1.5 2003/09/25 14:11:18 ichiro Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -48,36 +48,139 @@ __KERNEL_RCSID(0, "$NetBSD: ixp425.c,v 1.4 2003/07/02 11:02:28 ichiro Exp $");
#include <evbarm/ixdp425/ixdp425reg.h>
int ixp425_pcibus_print(void *, const char *);
static struct ixp425_softc *ixp425_softc;
int ixp425_pcibus_print(void *, const char *);
struct ixp425_softc *ixp425_softc;
void
ixp425_attach(struct ixp425_softc *sc)
{
struct pcibus_attach_args pba;
u_int32_t reg;
sc->sc_iot = &ixp425_bs_tag;
ixp425_softc = sc;
printf("\n");
#if 0
/*
* PCI bus reset
* Mapping for PCI CSR
*/
/* disable PCI command */
if (bus_space_map(sc->sc_iot, IXP425_PCI_HWBASE, IXP425_PCI_SIZE,
0, &sc->sc_pci_ioh))
panic("%s: unable to map PCI registers", sc->sc_dev.dv_xname);
/* XXX assert PCI reset Mode */
/*
* Mapping for GPIO Registers
*/
if (bus_space_map(sc->sc_iot, IXP425_GPIO_HWBASE, IXP425_GPIO_SIZE,
0, &sc->sc_gpio_ioh))
panic("%s: unable to map GPIO registers", sc->sc_dev.dv_xname);
/* We setup a 1:1 memory map of bus<->physical addresses */
/*
* PCI initialization
*/
/* PCI Reset Assert */
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg & ~(1U << GPIO_PCI_RESET));
/* PCI Clock Disable */
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg & ~GPCLKR_MUX14);
/*
* set GPIO Direction
* Output: PCI_CLK, PCI_RESET
* Input: PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD
*/
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER);
reg &= ~(1U << GPIO_PCI_CLK);
reg &= ~(1U << GPIO_PCI_RESET);
reg |= ((1U << GPIO_PCI_INTA) | (1U << GPIO_PCI_INTB) |
(1U << GPIO_PCI_INTC) | (1U << GPIO_PCI_INTD));
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER, reg);
/* clear ISR */
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPISR,
(1U << GPIO_PCI_INTA) | (1U << GPIO_PCI_INTB) |
(1U << GPIO_PCI_INTC) | (1U << GPIO_PCI_INTD));
/* wait 1ms to satisfy "minimum reset assertion time" of the PCI spec */
DELAY(1000);
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg |
(0xf << GPCLKR_CLK0DC_SHIFT) | (0xf << GPCLKR_CLK0TC_SHIFT));
/* PCI Clock Enable */
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg | GPCLKR_MUX14);
/*
* wait 100us to satisfy "minimum reset assertion time from clock stable
* requirement of the PCI spec
*/
DELAY(100);
/* PCI Reset deassert */
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg | (1U << GPIO_PCI_RESET));
/*
* AHB->PCI address translation
* PCI Memory Map allocation in 0x48000000 (64MB)
* see. IXP425_PCI_MEM_HWBASE
*/
PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b);
/*
* PCI->AHB address translation
* begin at the physical memory start + OFFSET
*/
#define AHB_OFFSET 0x10000000UL
PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE,
(AHB_OFFSET & 0xFF000000) +
((AHB_OFFSET & 0xFF000000) >> 8) +
((AHB_OFFSET & 0xFF000000) >> 16) +
((AHB_OFFSET & 0xFF000000) >> 24) +
0x00010203);
/* write Mapping registers PCI Configuration Registers */
/* Base Address 0 - 3 */
ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR0, AHB_OFFSET + 0x00000000);
ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR1, AHB_OFFSET + 0x01000000);
ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR2, AHB_OFFSET + 0x02000000);
ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR3, AHB_OFFSET + 0x03000000);
/* Base Address 4 */
ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR4, 0xffffffff);
/* Base Address 5 */
ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR5, 0x00000000);
/* assert some PCI errors */
PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_AHBE | ISR_PPE | ISR_PFE | ISR_PSE);
/*
* Set up byte lane swapping between little-endian PCI
* and the big-endian AHB bus
*/
PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE | CSR_PDS);
/*
* Enable bus mastering and I/O,memory access
*/
ixp425_pci_conf_reg_write(sc, PCI_COMMAND_STATUS_REG,
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
PCI_COMMAND_MASTER_ENABLE);
/*
* Initialize the bus space and DMA tags and the PCI chipset tag.
* Initialize the bus space tags.
*/
ixp425_io_bs_init(&sc->sc_pci_iot, sc);
ixp425_mem_bs_init(&sc->sc_pci_memt, sc);
/*
* Initialize the PCI chipset tags.
*/
ixp425_io_bs_init(&sc->ia_pci_iot, sc);
ixp425_mem_bs_init(&sc->ia_pci_memt, sc);
ixp425_pci_init(&sc->ia_pci_chipset, sc);
/*
@ -90,17 +193,17 @@ ixp425_attach(struct ixp425_softc *sc)
*/
pba.pba_busname = "pci";
pba.pba_pc = &sc->ia_pci_chipset;
pba.pba_iot = &sc->ia_pci_iot;
pba.pba_memt = &sc->ia_pci_memt;
pba.pba_iot = &sc->sc_pci_iot;
pba.pba_memt = &sc->sc_pci_memt;
pba.pba_dmat = &sc->ia_pci_dmat;
pba.pba_bus = 0; /* bus number = 0 */
pba.pba_bridgetag = NULL;
pba.pba_intrswiz = 0; /* XXX */
pba.pba_intrtag = 0;
pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED |
PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY |
PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY |
PCI_FLAGS_MWI_OKAY;
(void) config_found(&sc->sc_dev, &pba, ixp425_pcibus_print);
#endif
}
int

37
sys/arch/arm/xscale/ixp425_intr.c
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@ -1,4 +1,4 @@
/* $NetBSD: ixp425_intr.c,v 1.2 2003/06/16 20:00:58 thorpej Exp $ */
/* $NetBSD: ixp425_intr.c,v 1.3 2003/09/25 14:11:18 ichiro Exp $ */
/*
* Copyright (c) 2003
@ -68,7 +68,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ixp425_intr.c,v 1.2 2003/06/16 20:00:58 thorpej Exp $");
__KERNEL_RCSID(0, "$NetBSD: ixp425_intr.c,v 1.3 2003/09/25 14:11:18 ichiro Exp $");
#ifndef EVBARM_SPL_NOINLINE
#define EVBARM_SPL_NOINLINE
@ -92,6 +92,8 @@ __KERNEL_RCSID(0, "$NetBSD: ixp425_intr.c,v 1.2 2003/06/16 20:00:58 thorpej Exp
#include <arm/xscale/ixp425reg.h>
#include <arm/xscale/ixp425var.h>
#include <evbarm/ixdp425/ixdp425reg.h>
/* Interrupt handler queues. */
struct intrq intrq[NIRQ];
@ -460,6 +462,37 @@ ixp425_intr_dispatch(struct clockframe *frame)
* Disable all the interrupts that are pending. We will
* reenable them once they are processed and not masked.
*/
/* Clear GPIO interrupts pending for PCI(A..D) */
if (hwpend & (1U << PCI_INT_A)) {
#ifdef DEBUG
printf("ixp425_intr_dispatch: PCI_INT_A\n");
#endif
IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) =
(1U << GPIO_PCI_INTA);
}
if (hwpend & (1U << PCI_INT_B)) {
#ifdef DEBUG
printf("ixp425_intr_dispatch: PCI_INT_B\n");
#endif
IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) =
(1U << GPIO_PCI_INTB);
}
if (hwpend & (1U << PCI_INT_C)) {
#ifdef DEBUG
printf("ixp425_intr_dispatch: PCI_INT_C\n");
#endif
IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) =
(1U << GPIO_PCI_INTC);
}
if (hwpend & (1U << PCI_INT_D)) {
#ifdef DEBUG
printf("ixp425_intr_dispatch: PCI_INT_D\n");
#endif
IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) =
(1U << GPIO_PCI_INTD);
}
intr_enabled &= ~hwpend;
ixp425_set_intrmask();

322
sys/arch/arm/xscale/ixp425_io.c
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@ -1,322 +0,0 @@
/* $NetBSD: ixp425_io.c,v 1.2 2003/06/01 21:42:26 ichiro Exp $ */
/*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Ichiro FUKUHARA.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ixp425_io.c,v 1.2 2003/06/01 21:42:26 ichiro Exp $");
/*
* bus_space I/O functions for ixp425
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/queue.h>
#include <uvm/uvm.h>
#include <machine/bus.h>
#include <arm/xscale/ixp425reg.h>
#include <arm/xscale/ixp425var.h>
/* Proto types for all the bus_space structure functions */
bs_protos(ixp425);
bs_protos(ixp425_io);
bs_protos(ixp425_mem);
bs_protos(generic);
bs_protos(generic_armv4);
bs_protos(bs_notimpl);
struct bus_space ixp425_bs_tag = {
/* cookie */
(void *) 0,
/* mapping/unmapping */
NULL,
NULL,
ixp425_bs_subregion,
/* allocation/deallocation */
NULL,
NULL,
/* get kernel virtual address */
ixp425_bs_vaddr,
/* mmap bus space for userland */
ixp425_bs_mmap,
/* barrier */
ixp425_bs_barrier,
/* read (single) */
generic_bs_r_1,
generic_armv4_bs_r_2,
generic_bs_r_4,
bs_notimpl_bs_r_8,
/* read multiple */
generic_bs_rm_1,
generic_armv4_bs_rm_2,
generic_bs_rm_4,
bs_notimpl_bs_rm_8,
/* read region */
bs_notimpl_bs_rr_1,
generic_armv4_bs_rr_2,
generic_bs_rr_4,
bs_notimpl_bs_rr_8,
/* write (single) */
generic_bs_w_1,
generic_armv4_bs_w_2,
generic_bs_w_4,
bs_notimpl_bs_w_8,
/* write multiple */
generic_bs_wm_1,
generic_armv4_bs_wm_2,
generic_bs_wm_4,
bs_notimpl_bs_wm_8,
/* write region */
bs_notimpl_bs_wr_1,
generic_armv4_bs_wr_2,
generic_bs_wr_4,
bs_notimpl_bs_wr_8,
/* set multiple */
bs_notimpl_bs_sm_1,
bs_notimpl_bs_sm_2,
bs_notimpl_bs_sm_4,
bs_notimpl_bs_sm_8,
/* set region */
bs_notimpl_bs_sr_1,
generic_armv4_bs_sr_2,
generic_bs_sr_4,
bs_notimpl_bs_sr_8,
/* copy */
bs_notimpl_bs_c_1,
generic_armv4_bs_c_2,
bs_notimpl_bs_c_4,
bs_notimpl_bs_c_8,
};
void
ixp425_bs_init(bus_space_tag_t bs, void *cookie)
{
*bs = ixp425_bs_tag;
bs->bs_cookie = cookie;
}
void
ixp425_io_bs_init(bus_space_tag_t bs, void *cookie)
{
*bs = ixp425_bs_tag;
bs->bs_cookie = cookie;
bs->bs_map = ixp425_io_bs_map;
bs->bs_unmap = ixp425_io_bs_unmap;
bs->bs_alloc = ixp425_io_bs_alloc;
bs->bs_free = ixp425_io_bs_free;
bs->bs_vaddr = ixp425_io_bs_vaddr;
}
void
ixp425_mem_bs_init(bus_space_tag_t bs, void *cookie)
{
*bs = ixp425_bs_tag;
bs->bs_cookie = cookie;
bs->bs_map = ixp425_mem_bs_map;
bs->bs_unmap = ixp425_mem_bs_unmap;
bs->bs_alloc = ixp425_mem_bs_alloc;
bs->bs_free = ixp425_mem_bs_free;
bs->bs_mmap = ixp425_mem_bs_mmap;
}
/* mem bus space functions */
int
ixp425_mem_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int cacheable,
bus_space_handle_t *bshp)
{
paddr_t pa, endpa;
vaddr_t va;
#if 0
if ((bpa + size) >= IXP425_PCI_MEM_VBASE + IXP425_PCI_MEM_SIZE)
return (EINVAL);
#endif
/*
* PCI MEM space is mapped same address as real memory
* see. PCI_ADDR_EXT
*/
pa = trunc_page(bpa);
endpa = round_page(bpa + size);
/* Get some VM. */
va = uvm_km_valloc(kernel_map, endpa - pa);
if (va == 0)
return(ENOMEM);
/* Store the bus space handle */
*bshp = va + (bpa & PAGE_MASK);
/* Now map the pages */
for(; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
pmap_enter(pmap_kernel(), va, pa,
VM_PROT_READ | VM_PROT_WRITE,
VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED);
}
pmap_update(pmap_kernel());
return(0);
}
void
ixp425_mem_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
{
vaddr_t startva, endva;
startva = trunc_page(bsh);
endva = round_page(bsh + size);
uvm_km_free(kernel_map, startva, endva - startva);
}
int
ixp425_mem_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable,
bus_addr_t *bpap, bus_space_handle_t *bshp)
{
panic("ixp425_mem_bs_alloc(): Help!");
}
void
ixp425_mem_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
{
panic("ixp425_mem_bs_free(): Help!");
}
paddr_t
ixp425_mem_bs_mmap(void *t, bus_addr_t addr, off_t off, int prot, int flags)
{
/* Not supported. */
return (-1);
}
/* I/O bus space functions */
int
ixp425_io_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int cacheable,
bus_space_handle_t *bshp)
{
if ((bpa + size) >= IXP425_IO_VBASE)
return (EINVAL);
/*
* PCI I/O space is mapped at virtual address of each evaluation board.
* Translate the bus address(0x0) to the virtual address(0x54000000).
*/
*bshp = bpa + IXP425_IO_VBASE;
return(0);
}
void
ixp425_io_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
{
/*
* Temporary implementation
*/
}
int
ixp425_io_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable,
bus_addr_t *bpap, bus_space_handle_t *bshp)
{
panic("ixp425_io_bs_alloc(): Help!");
}
void
ixp425_io_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
{
panic("ixp425_io_bs_free(): Help!");
}
void *
ixp425_io_bs_vaddr(void *t, bus_space_handle_t bsh)
{
/* Not supported. */
return (NULL);
}
/* Common routines */
int
ixp425_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
bus_size_t size, bus_space_handle_t *nbshp)
{
*nbshp = bsh + offset;
return (0);
}
void *
ixp425_bs_vaddr(void *t, bus_space_handle_t bsh)
{
return ((void *)bsh);
}
paddr_t
ixp425_bs_mmap(void *t, bus_addr_t addr, off_t off, int prot, int flags)
{
/* Not supported. */
return (-1);
}
void
ixp425_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
bus_size_t len, int flags)
{
/* NULL */
}
/* End of ixp425_io.c */

265
sys/arch/arm/xscale/ixp425_pci.c Normal file
View File

@ -0,0 +1,265 @@
/* $NetBSD: ixp425_pci.c,v 1.1 2003/09/25 14:11:18 ichiro Exp $ */
/*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Ichiro FUKUHARA.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ixp425_pci.c,v 1.1 2003/09/25 14:11:18 ichiro Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/extent.h>
#include <sys/malloc.h>
#include <uvm/uvm_extern.h>
#include <machine/bus.h>
#include <arm/xscale/ixp425reg.h>
#include <arm/xscale/ixp425var.h>
#include <evbarm/ixdp425/ixdp425reg.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pciconf.h>
#include "opt_pci.h"
#include "pci.h"
void ixp425_pci_attach_hook(struct device *, struct device *,
struct pcibus_attach_args *);
int ixp425_pci_bus_maxdevs(void *, int);
void ixp425_pci_decompose_tag(void *, pcitag_t, int *, int *, int *);
void ixp425_pci_conf_setup(void *, struct ixp425_softc *, pcitag_t, int);
void ixp425_pci_conf_write(void *, pcitag_t, int, pcireg_t);
pcitag_t ixp425_pci_make_tag(void *, int, int, int);
pcireg_t ixp425_pci_conf_read(void *, pcitag_t, int);
#define MAX_PCI_DEVICES 32
void
ixp425_pci_init(pci_chipset_tag_t pc, void *cookie)
{
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
struct ixp425_softc *sc = cookie;
struct extent *ioext, *memext;
#endif
pc->pc_conf_v = cookie;
pc->pc_attach_hook = ixp425_pci_attach_hook;
pc->pc_bus_maxdevs = ixp425_pci_bus_maxdevs;
pc->pc_make_tag = ixp425_pci_make_tag;
pc->pc_decompose_tag = ixp425_pci_decompose_tag;
pc->pc_conf_read = ixp425_pci_conf_read;
pc->pc_conf_write = ixp425_pci_conf_write;
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
ioext = extent_create("pciio", 0, IXP425_PCI_IO_SIZE - 1,
M_DEVBUF, NULL, 0, EX_NOWAIT);
/* PCI MEM space is mapped same address as real memory */
memext = extent_create("pcimem", IXP425_PCI_MEM_VBASE,
IXP425_PCI_MEM_VBASE +
IXP425_PCI_MEM_SIZE - 1,
M_DEVBUF, NULL, 0, EX_NOWAIT);
printf("%s: configuring PCI bus\n", sc->sc_dev.dv_xname);
pci_configure_bus(pc, ioext, memext, NULL, 0 /* XXX bus = 0 */,
arm_dcache_align);
extent_destroy(ioext);
extent_destroy(memext);
#endif
}
void
pci_conf_interrupt(pci_chipset_tag_t pc, int a, int b, int c, int d, int *p)
{
}
void
ixp425_pci_attach_hook(struct device *parent, struct device *self,
struct pcibus_attach_args *pba)
{
/* Nothing to do. */
}
int
ixp425_pci_bus_maxdevs(void *v, int busno)
{
return(MAX_PCI_DEVICES);
}
pcitag_t
ixp425_pci_make_tag(void *v, int bus, int device, int function)
{
#ifdef PCI_DEBUG
printf("ixp425_pci_make_tag(v=%p, bus=%d, device=%d, function=%d)\n",
v, bus, device, function);
#endif
return ((bus << 16) | (device << 11) | (function << 8));
}
void
ixp425_pci_decompose_tag(void *v, pcitag_t tag, int *busp, int *devicep,
int *functionp)
{
#ifdef PCI_DEBUG
printf("ixp425_pci_decompose_tag(v=%p, tag=0x%08lx, bp=%x, dp=%x, fp=%x)\n",
v, tag, (int)busp, (int)devicep, (int)functionp);
#endif
if (busp != NULL)
*busp = (tag >> 16) & 0xff;
if (devicep != NULL)
*devicep = (tag >> 11) & 0x1f;
if (functionp != NULL)
*functionp = (tag >> 8) & 0x7;
}
void
ixp425_pci_conf_setup(void *v, struct ixp425_softc *sc, pcitag_t tag, int offset)
{
int bus, device, function;
ixp425_pci_decompose_tag(v, tag, &bus, &device, &function);
if (bus == 0) {
if (device == 0 && function == 0) {
PCI_CSR_WRITE_4(sc, PCI_NP_AD, (offset & ~3));
} else {
/* configuration type 0 */
PCI_CSR_WRITE_4(sc, PCI_NP_AD, (1U << (32 - device)) |
(function << 8) | (offset & ~3));
}
} else {
/* configuration type 1 */
PCI_CSR_WRITE_4(sc, PCI_NP_AD,
(bus << 16) | (device << 11) |
(function << 8) | (offset & ~3) | 1);
}
}
/* read/write PCI Non-Pre-fetch Data */
pcireg_t
ixp425_pci_conf_read(void *v, pcitag_t tag, int offset)
{
struct ixp425_softc *sc = v;
u_int32_t data;
pcireg_t rv;
int s;
#define PCI_NP_HAVE_BUG
#ifdef PCI_NP_HAVE_BUG
int i;
#endif
PCI_CONF_LOCK(s);
ixp425_pci_conf_setup(v, sc, tag, offset);
#ifdef PCI_DEBUG
printf("ixp425_pci_conf_read: tag=%lx,offset=%x\n",
tag, offset);
#endif
#ifdef PCI_NP_HAVE_BUG
/* PCI NP Bug workaround */
for (i = 0; i < 8; i++) {
PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_READ);
rv = PCI_CSR_READ_4(sc, PCI_NP_RDATA);
rv = PCI_CSR_READ_4(sc, PCI_NP_RDATA);
}
#else
PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_READ);
rv = PCI_CSR_READ_4(sc, PCI_NP_RDATA);
#endif
/* check&clear PCI abort */
data = PCI_CSR_READ_4(sc, PCI_ISR);
if (data & ISR_PFE) {
PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE);
PCI_CONF_UNLOCK(s);
return -1;
} else {
PCI_CONF_UNLOCK(s);
return rv;
}
}
void
ixp425_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
{
struct ixp425_softc *sc = v;
u_int32_t data;
int s;
PCI_CONF_LOCK(s);
ixp425_pci_conf_setup(v, sc, tag, offset);
#ifdef PCI_DEBUG
printf("ixp425_pci_conf_write: tag=%lx offset=%x <- val=%x\n",
tag, offset, val);
#endif
PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_WRITE);
PCI_CSR_WRITE_4(sc, PCI_NP_WDATA, val);
/* check&clear PCI abort */
data = PCI_CSR_READ_4(sc, PCI_ISR);
if (data & ISR_PFE)
PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE);
PCI_CONF_UNLOCK(s);
}
/* read/write pci configuration data */
uint32_t
ixp425_pci_conf_reg_read(struct ixp425_softc *sc, uint32_t reg)
{
uint32_t data;
bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_READ));
data = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,
PCI_CRP_AD_RDATA);
return data;
}
void
ixp425_pci_conf_reg_write(struct ixp425_softc *sc, uint32_t reg,
uint32_t data)
{
bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_WRITE));
bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
PCI_CRP_AD_WDATA, data);
}

100
sys/arch/arm/xscale/ixp425_pci_asm.S Normal file
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/* $NetBSD: ixp425_pci_asm.S,v 1.1 2003/09/25 14:11:18 ichiro Exp $ */
/*
* Copyright (c) 2003 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arm/asm.h>
#include <arm/cpuconf.h>
/*
* Bus space functions for IXP425 PCI space access. We have to swizzle
* the address for 1 and 2 byte accesses when in big-endian mode.
*/
/*
* read single
*/
ENTRY(ixp425_pci_mem_bs_r_1)
#ifdef __ARMEB__
add r1, r1, r2
eor r1, r1, #0x3
ldrb r0, [r1]
#else
ldrb r0, [r1, r2]
#endif /* __ARMEB__ */
mov pc, lr
ENTRY(ixp425_pci_mem_bs_r_2)
#ifdef __ARMEB__
add r1, r1, r2
eor r1, r1, #0x2
ldrh r0, [r1]
#else
ldrh r0, [r1, r2]
#endif /* __ARMEB__ */
mov pc, lr
ENTRY(ixp425_pci_mem_bs_r_4)
ldr r0, [r1, r2]
mov pc, lr
/*
* write single
*/
ENTRY(ixp425_pci_mem_bs_w_1)
#ifdef __ARMEB__
add r1, r1, r2
eor r1, r1, #0x3
strb r3, [r1]
#else
strb r3, [r1, r2]
#endif /* __ARMEB__ */
mov pc, lr
ENTRY(ixp425_pci_mem_bs_w_2)
#ifdef __ARMEB__
add r1, r1, r2
eor r1, r1, #0x2
strh r3, [r1]
#else
strh r3, [r1, r2]
#endif /* __ARMEB__ */
mov pc, lr
ENTRY(ixp425_pci_mem_bs_w_4)
str r3, [r1, r2]
mov pc, lr

85
sys/arch/arm/xscale/ixp425_pci_dma.c Normal file
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/* $NetBSD: ixp425_pci_dma.c,v 1.1 2003/09/25 14:11:18 ichiro Exp $ */
/*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Ichiro FUKUHARA.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ixp425_pci_dma.c,v 1.1 2003/09/25 14:11:18 ichiro Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <sys/mbuf.h>
#include <uvm/uvm_extern.h>
#define _ARM32_BUS_DMA_PRIVATE
#include <machine/bus.h>
#include <arm/xscale/ixp425reg.h>
#include <arm/xscale/ixp425var.h>
void
ixp425_pci_dma_init(struct ixp425_softc *sc)
{
extern paddr_t physical_start, physical_end;
bus_dma_tag_t dmat = &sc->ia_pci_dmat;
struct arm32_dma_range *dr = &sc->ia_pci_dma_range;
dmat->_ranges = dr;
dmat->_nranges = 1;
dr->dr_sysbase = physical_start;
dr->dr_busbase = PCI_MAPREG_MEM_ADDR(IXP425_PCI_MEM_VBASE +
physical_start);
dr->dr_busbase = physical_start;
dr->dr_len = physical_end - physical_start;
dmat->_dmamap_create = _bus_dmamap_create;
dmat->_dmamap_destroy = _bus_dmamap_destroy;
dmat->_dmamap_load = _bus_dmamap_load;
dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf;
dmat->_dmamap_load_uio = _bus_dmamap_load_uio;
dmat->_dmamap_load_raw = _bus_dmamap_load_raw;
dmat->_dmamap_unload = _bus_dmamap_unload;
dmat->_dmamap_sync_pre = _bus_dmamap_sync;
dmat->_dmamap_sync_post = NULL;
dmat->_dmamem_alloc = _bus_dmamem_alloc;
dmat->_dmamem_free = _bus_dmamem_free;
dmat->_dmamem_map = _bus_dmamem_map;
dmat->_dmamem_unmap = _bus_dmamem_unmap;
dmat->_dmamem_mmap = _bus_dmamem_mmap;
}

456
sys/arch/arm/xscale/ixp425_pci_space.c Normal file
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/* $NetBSD: ixp425_pci_space.c,v 1.1 2003/09/25 14:11:18 ichiro Exp $ */
/*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Ichiro FUKUHARA.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ixp425_pci_space.c,v 1.1 2003/09/25 14:11:18 ichiro Exp $");
/*
* bus_space PCI functions for ixp425
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/queue.h>
#include <uvm/uvm.h>
#include <machine/bus.h>
#include <arm/xscale/ixp425reg.h>
#include <arm/xscale/ixp425var.h>
/*
* Macros to read/write registers
*/
#define CSR_READ_4(x) *(__volatile uint32_t *) \
(IXP425_PCI_CSR_BASE + (x))
#define CSR_WRITE_4(x, v) *(__volatile uint32_t *) \
(IXP425_PCI_CSR_BASE + (x)) = (v)
/* Proto types for all the bus_space structure functions */
bs_protos(ixp425_pci);
bs_protos(ixp425_pci_io);
bs_protos(ixp425_pci_mem);
bs_protos(bs_notimpl);
/* special I/O functions */
#if 1 /* XXX */
inline u_int8_t _pci_io_bs_r_1(void *, bus_space_handle_t, bus_size_t);
inline u_int16_t _pci_io_bs_r_2(void *, bus_space_handle_t, bus_size_t);
inline u_int32_t _pci_io_bs_r_4(void *, bus_space_handle_t, bus_size_t);
inline void _pci_io_bs_w_1(void *, bus_space_handle_t, bus_size_t, u_int8_t);
inline void _pci_io_bs_w_2(void *, bus_space_handle_t, bus_size_t, u_int16_t);
inline void _pci_io_bs_w_4(void *, bus_space_handle_t, bus_size_t, u_int32_t);
#endif
struct bus_space ixp425_pci_bs_tag_template = {
/* cookie */
(void *) 0,
/* mapping/unmapping */
NULL,
NULL,
ixp425_pci_bs_subregion,
/* allocation/deallocation */
NULL,
NULL,
/* get kernel virtual address */
NULL,
/* mmap bus space for userland */
ixp425_pci_bs_mmap,
/* barrier */
ixp425_pci_bs_barrier,
/* read (single) */
bs_notimpl_bs_r_1,
bs_notimpl_bs_r_2,
bs_notimpl_bs_r_4,
bs_notimpl_bs_r_8,
/* read multiple */
bs_notimpl_bs_rm_1,
bs_notimpl_bs_rm_2,
bs_notimpl_bs_rm_4,
bs_notimpl_bs_rm_8,
/* read region */
bs_notimpl_bs_rr_1,
bs_notimpl_bs_rr_2,
bs_notimpl_bs_rr_4,
bs_notimpl_bs_rr_8,
/* write (single) */
bs_notimpl_bs_w_1,
bs_notimpl_bs_w_2,
bs_notimpl_bs_w_4,
bs_notimpl_bs_w_8,
/* write multiple */
bs_notimpl_bs_wm_1,
bs_notimpl_bs_wm_2,
bs_notimpl_bs_wm_4,
bs_notimpl_bs_wm_8,
/* write region */
bs_notimpl_bs_wr_1,
bs_notimpl_bs_wr_2,
bs_notimpl_bs_wr_4,
bs_notimpl_bs_wr_8,
/* set multiple */
bs_notimpl_bs_sm_1,
bs_notimpl_bs_sm_2,
bs_notimpl_bs_sm_4,
bs_notimpl_bs_sm_8,
/* set region */
bs_notimpl_bs_sr_1,
bs_notimpl_bs_sr_2,
bs_notimpl_bs_sr_4,
bs_notimpl_bs_sr_8,
/* copy */
bs_notimpl_bs_c_1,
bs_notimpl_bs_c_2,
bs_notimpl_bs_c_4,
bs_notimpl_bs_c_8,
};
void
ixp425_io_bs_init(bus_space_tag_t bs, void *cookie)
{
*bs = ixp425_pci_bs_tag_template;
bs->bs_cookie = cookie;
bs->bs_map = ixp425_pci_io_bs_map;
bs->bs_unmap = ixp425_pci_io_bs_unmap;
bs->bs_alloc = ixp425_pci_io_bs_alloc;
bs->bs_free = ixp425_pci_io_bs_free;
bs->bs_vaddr = ixp425_pci_io_bs_vaddr;
/* read (single) */
bs->bs_r_1 = _pci_io_bs_r_1;
bs->bs_r_2 = _pci_io_bs_r_2;
bs->bs_r_4 = _pci_io_bs_r_4;
/* write (single) */
bs->bs_w_1 = _pci_io_bs_w_1;
bs->bs_w_2 = _pci_io_bs_w_2;
bs->bs_w_4 = _pci_io_bs_w_4;
}
void
ixp425_mem_bs_init(bus_space_tag_t bs, void *cookie)
{
*bs = ixp425_pci_bs_tag_template;
bs->bs_cookie = cookie;
bs->bs_map = ixp425_pci_mem_bs_map;
bs->bs_unmap = ixp425_pci_mem_bs_unmap;
bs->bs_alloc = ixp425_pci_mem_bs_alloc;
bs->bs_free = ixp425_pci_mem_bs_free;
bs->bs_vaddr = ixp425_pci_mem_bs_vaddr;
/* read (single) */
bs->bs_r_1 = ixp425_pci_mem_bs_r_1;
bs->bs_r_2 = ixp425_pci_mem_bs_r_2;
bs->bs_r_4 = ixp425_pci_mem_bs_r_4;
/* write (single) */
bs->bs_w_1 = ixp425_pci_mem_bs_w_1;
bs->bs_w_2 = ixp425_pci_mem_bs_w_2;
bs->bs_w_4 = ixp425_pci_mem_bs_w_4;
}
/* common routine */
int
ixp425_pci_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
bus_size_t size, bus_space_handle_t *nbshp)
{
*nbshp = bsh + offset;
return (0);
}
void
ixp425_pci_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
bus_size_t len, int flags)
{
/* NULL */
}
paddr_t
ixp425_pci_bs_mmap(void *t, bus_addr_t addr, off_t off, int prot, int flags)
{
/* Not supported. */
return (-1);
}
/* io bs */
int
ixp425_pci_io_bs_map(void *t, bus_addr_t bpa, bus_size_t size,
int cacheable, bus_space_handle_t *bshp)
{
*bshp = bpa;
return (0);
}
void
ixp425_pci_io_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
{
/* Nothing to do. */
}
int
ixp425_pci_io_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable,
bus_addr_t *bpap, bus_space_handle_t *bshp)
{
panic("ixp425_pci_io_bs_alloc(): not implemented\n");
}
void
ixp425_pci_io_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
{
panic("ixp425_pci_io_bs_free(): not implemented\n");
}
void *
ixp425_pci_io_bs_vaddr(void *t, bus_space_handle_t bsh)
{
/* Not supported. */
return (NULL);
}
/* special I/O functions */
#if 1 /* _pci_io_bs_{rw}_{124} */
inline u_int8_t
_pci_io_bs_r_1(void *v, bus_space_handle_t ioh, bus_size_t off)
{
u_int32_t data, n, be;
int s;
n = (ioh + off) % 4;
be = (0xf & ~(1U << n)) << NP_CBE_SHIFT;
PCI_CONF_LOCK(s);
CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ);
data = CSR_READ_4(PCI_NP_RDATA);
if (CSR_READ_4(PCI_ISR) & ISR_PFE)
CSR_WRITE_4(PCI_ISR, ISR_PFE);
PCI_CONF_UNLOCK(s);
return data >> (8 * n);
}
inline u_int16_t
_pci_io_bs_r_2(void *v, bus_space_handle_t ioh, bus_size_t off)
{
u_int32_t data, n, be;
int s;
n = (ioh + off) % 4;
be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT;
PCI_CONF_LOCK(s);
CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ);
data = CSR_READ_4(PCI_NP_RDATA);
if (CSR_READ_4(PCI_ISR) & ISR_PFE)
CSR_WRITE_4(PCI_ISR, ISR_PFE);
PCI_CONF_UNLOCK(s);
return data >> (8 * n);
}
inline u_int32_t
_pci_io_bs_r_4(void *v, bus_space_handle_t ioh, bus_size_t off)
{
u_int32_t data;
int s;
PCI_CONF_LOCK(s);
CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
CSR_WRITE_4(PCI_NP_CBE, COMMAND_NP_IO_READ);
data = CSR_READ_4(PCI_NP_RDATA);
if (CSR_READ_4(PCI_ISR) & ISR_PFE)
CSR_WRITE_4(PCI_ISR, ISR_PFE);
PCI_CONF_UNLOCK(s);
return data;
}
inline void
_pci_io_bs_w_1(void *v, bus_space_handle_t ioh, bus_size_t off,
u_int8_t val)
{
u_int32_t data, n, be;
int s;
n = (ioh + off) % 4;
be = (0xf & ~(1U << n)) << NP_CBE_SHIFT;
data = val << (8 * n);
PCI_CONF_LOCK(s);
CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_WRITE);
CSR_WRITE_4(PCI_NP_WDATA, data);
if (CSR_READ_4(PCI_ISR) & ISR_PFE)
CSR_WRITE_4(PCI_ISR, ISR_PFE);
PCI_CONF_UNLOCK(s);
}
inline void
_pci_io_bs_w_2(void *v, bus_space_handle_t ioh, bus_size_t off,
u_int16_t val)
{
u_int32_t data, n, be;
int s;
n = (ioh + off) % 4;
be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT;
data = val << (8 * n);
PCI_CONF_LOCK(s);
CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_WRITE);
CSR_WRITE_4(PCI_NP_WDATA, data);
if (CSR_READ_4(PCI_ISR) & ISR_PFE)
CSR_WRITE_4(PCI_ISR, ISR_PFE);
PCI_CONF_UNLOCK(s);
}
inline void
_pci_io_bs_w_4(void *v, bus_space_handle_t ioh, bus_size_t off,
u_int32_t val)
{
int s;
PCI_CONF_LOCK(s);
CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
CSR_WRITE_4(PCI_NP_CBE, COMMAND_NP_IO_WRITE);
CSR_WRITE_4(PCI_NP_WDATA, val);
if (CSR_READ_4(PCI_ISR) & ISR_PFE)
CSR_WRITE_4(PCI_ISR, ISR_PFE);
PCI_CONF_UNLOCK(s);
}
#endif /* _pci_io_bs_{rw}_{124} */
/* mem bs */
int
ixp425_pci_mem_bs_map(void *t, bus_addr_t bpa, bus_size_t size,
int cacheable, bus_space_handle_t *bshp)
{
const struct pmap_devmap *pd;
paddr_t startpa;
paddr_t endpa;
paddr_t pa;
paddr_t offset;
vaddr_t va;
pt_entry_t *pte;
if ((pd = pmap_devmap_find_pa(bpa, size)) != NULL) {
/* Device was statically mapped. */
*bshp = pd->pd_va + (bpa - pd->pd_pa);
return 0;
}
endpa = round_page(bpa + size);
offset = bpa & PAGE_MASK;
startpa = trunc_page(bpa);
/* Get some VM. */
if ((va = uvm_km_valloc(kernel_map, endpa - startpa)) == 0)
return ENOMEM;
/* Store the bus space handle */
*bshp = va + offset;
/* Now map the pages */
for (pa = startpa; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE);
pte = vtopte(va);
*pte &= ~L2_S_CACHE_MASK;
PTE_SYNC(pte);
}
pmap_update(pmap_kernel());
return(0);
}
void
ixp425_pci_mem_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
{
vaddr_t va;
vaddr_t endva;
if (pmap_devmap_find_va(bsh, size) != NULL) {
/* Device was statically mapped; nothing to do. */
return;
}
endva = round_page(bsh + size);
va = trunc_page(bsh);
pmap_kremove(va, endva - va);
uvm_km_free(kernel_map, va, endva - va);
}
int
ixp425_pci_mem_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable,
bus_addr_t *bpap, bus_space_handle_t *bshp)
{
panic("ixp425_mem_bs_alloc(): not implemented\n");
}
void
ixp425_pci_mem_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
{
panic("ixp425_mem_bs_free(): not implemented\n");
}
void *
ixp425_pci_mem_bs_vaddr(void *t, bus_space_handle_t bsh)
{
return ((void *)bsh);
}
/* End of ixp425_pci_space.c */

238
sys/arch/arm/xscale/ixp425_space.c Normal file
View File

@ -0,0 +1,238 @@
/* $NetBSD: ixp425_space.c,v 1.1 2003/09/25 14:11:18 ichiro Exp $ */
/*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Ichiro FUKUHARA.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ixp425_space.c,v 1.1 2003/09/25 14:11:18 ichiro Exp $");
/*
* bus_space I/O functions for ixp425
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/queue.h>
#include <uvm/uvm.h>
#include <machine/bus.h>
#include <arm/xscale/ixp425reg.h>
#include <arm/xscale/ixp425var.h>
/* Proto types for all the bus_space structure functions */
bs_protos(ixp425);
bs_protos(generic);
bs_protos(generic_armv4);
bs_protos(bs_notimpl);
struct bus_space ixp425_bs_tag = {
/* cookie */
(void *) 0,
/* mapping/unmapping */
ixp425_bs_map,
ixp425_bs_unmap,
ixp425_bs_subregion,
/* allocation/deallocation */
ixp425_bs_alloc,
ixp425_bs_free,
/* get kernel virtual address */
ixp425_bs_vaddr,
/* mmap bus space for userland */
ixp425_bs_mmap,
/* barrier */
ixp425_bs_barrier,
/* read (single) */
generic_bs_r_1,
generic_armv4_bs_r_2,
generic_bs_r_4,
bs_notimpl_bs_r_8,
/* read multiple */
generic_bs_rm_1,
generic_armv4_bs_rm_2,
generic_bs_rm_4,
bs_notimpl_bs_rm_8,
/* read region */
bs_notimpl_bs_rr_1,
generic_armv4_bs_rr_2,
generic_bs_rr_4,
bs_notimpl_bs_rr_8,
/* write (single) */
generic_bs_w_1,
generic_armv4_bs_w_2,
generic_bs_w_4,
bs_notimpl_bs_w_8,
/* write multiple */
generic_bs_wm_1,
generic_armv4_bs_wm_2,
generic_bs_wm_4,
bs_notimpl_bs_wm_8,
/* write region */
bs_notimpl_bs_wr_1,
generic_armv4_bs_wr_2,
generic_bs_wr_4,
bs_notimpl_bs_wr_8,
/* set multiple */
bs_notimpl_bs_sm_1,
bs_notimpl_bs_sm_2,
bs_notimpl_bs_sm_4,
bs_notimpl_bs_sm_8,
/* set region */
bs_notimpl_bs_sr_1,
generic_armv4_bs_sr_2,
generic_bs_sr_4,
bs_notimpl_bs_sr_8,
/* copy */
bs_notimpl_bs_c_1,
generic_armv4_bs_c_2,
bs_notimpl_bs_c_4,
bs_notimpl_bs_c_8,
};
int
ixp425_bs_map(void *t, bus_addr_t bpa, bus_size_t size,
int cacheable, bus_space_handle_t *bshp)
{
const struct pmap_devmap *pd;
paddr_t startpa;
paddr_t endpa;
paddr_t pa;
paddr_t offset;
vaddr_t va;
pt_entry_t *pte;
if ((pd = pmap_devmap_find_pa(bpa, size)) != NULL) {
/* Device was statically mapped. */
*bshp = pd->pd_va + (bpa - pd->pd_pa);
return 0;
}
endpa = round_page(bpa + size);
offset = bpa & PAGE_MASK;
startpa = trunc_page(bpa);
/* Get some VM. */
if ((va = uvm_km_valloc(kernel_map, endpa - startpa)) == 0)
return ENOMEM;
/* Store the bus space handle */
*bshp = va + offset;
/* Now map the pages */
for (pa = startpa; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE);
pte = vtopte(va);
*pte &= ~L2_S_CACHE_MASK;
PTE_SYNC(pte);
}
pmap_update(pmap_kernel());
return(0);
}
void
ixp425_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
{
vaddr_t va;
vaddr_t endva;
if (pmap_devmap_find_va(bsh, size) != NULL) {
/* Device was statically mapped; nothing to do. */
return;
}
endva = round_page(bsh + size);
va = trunc_page(bsh);
pmap_kremove(va, endva - va);
uvm_km_free(kernel_map, va, endva - va);
}
int
ixp425_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable,
bus_addr_t *bpap, bus_space_handle_t *bshp)
{
panic("ixp425_bs_alloc(): not implemented\n");
}
void
ixp425_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
{
panic("ixp425_bs_free(): not implemented\n");
}
int
ixp425_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
bus_size_t size, bus_space_handle_t *nbshp)
{
*nbshp = bsh + offset;
return (0);
}
void *
ixp425_bs_vaddr(void *t, bus_space_handle_t bsh)
{
return ((void *)bsh);
}
paddr_t
ixp425_bs_mmap(void *t, bus_addr_t addr, off_t off, int prot, int flags)
{
/* Not supported. */
return (-1);
}
void
ixp425_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
bus_size_t len, int flags)
{
/* NULL */
}
/* End of ixp425_space.c */

73
sys/arch/arm/xscale/ixp425reg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: ixp425reg.h,v 1.9 2003/07/02 14:03:52 ichiro Exp $ */
/* $NetBSD: ixp425reg.h,v 1.10 2003/09/25 14:11:18 ichiro Exp $ */
/*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
@ -300,6 +300,33 @@
(1 << IXP425_INT_bit29) | \
(1 << IXP425_INT_bit22)))
/*
* GPIO
*/
#define IXP425_GPIO_HWBASE IXP425_IO_HWBASE + IXP425_GPIO_OFFSET
#define IXP425_GPIO_VBASE IXP425_IO_VBASE + IXP425_GPIO_OFFSET
/* 0xf0004000 */
#define IXP425_GPIO_SIZE 0x00000020UL
#define IXP425_GPIO_GPOUTR 0x00
#define IXP425_GPIO_GPOER 0x04
#define IXP425_GPIO_GPINR 0x08
#define IXP425_GPIO_GPISR 0x0c
#define IXP425_GPIO_GPIT1R 0x10
#define IXP425_GPIO_GPIT2R 0x14
#define IXP425_GPIO_GPCLKR 0x18
# define GPCLKR_MUX14 (1U << 8)
# define GPCLKR_CLK0TC_SHIFT 4
# define GPCLKR_CLK0DC_SHIFT 0
/* GPIO Output */
#define GPOUT_ON 0x1
#define GPOUT_OFF 0x0
/* GPIO direction */
#define GPOER_INPUT 0x1
#define GPOER_OUTPUT 0x0
/*
* Expansion Bus
*/
@ -394,16 +421,39 @@
/* PCI_INTERRUPT_REG 0x3c */
#define PCI_RTOTTO 0x40
/* PCI Controller CSR Base Address */
#define IXP425_PCI_CSR_BASE IXP425_PCI_VBASE
/* PCI Memory Space */
#define IXP425_PCI_MEM_HWBASE 0x48000000UL /* VA == PA */
#define IXP425_PCI_MEM_VBASE IXP425_PCI_MEM_HWBASE
#define IXP425_PCI_MEM_SIZE 0x04000000UL /* 64MB */
/* PCI I/O Space */
#define IXP425_PCI_IO_HWBASE 0x90000000UL
#define IXP425_PCI_IO_VBASE IXP425_PCI_IO_HWBASE
#define IXP425_PCI_IO_SIZE 0x00100000UL /* 1Mbyte */
/* PCI Controller Configuration Offset */
#define PCI_NP_AD 0x00
#define PCI_NP_CBE 0x04
# define NP_CBE_SHIFT 4
#define PCI_NP_WDATA 0x08
#define PCI_NP_RDATA 0x0c
#define PCI_CRP_AD_CBE 0x10
#define PCI_CRP_AD_WDATA 0x14
#define PCI_CRP_AD_RDATA 0x18
#define PCI_CSR 0x1c
# define CSR_PRST (1U << 16)
# define CSR_IC (1U << 15)
# define CSR_ABE (1U << 4)
# define CSR_PDS (1U << 3)
# define CSR_ADS (1U << 2)
#define PCI_ISR 0x20
# define ISR_AHBE (1U << 3)
# define ISR_PPE (1U << 2)
# define ISR_PFE (1U << 1)
# define ISR_PSE (1U << 0)
#define PCI_INTEN 0x24
#define PCI_DMACTRL 0x28
#define PCI_AHBMEMBASE 0x2c
@ -424,16 +474,19 @@
#define PCI_PTADMA1_PCIADDR 0x68
#define PCI_PTADMA1_LENGTH 0x6c
/* PCI target(T)/initiator(I) Interface Commands */
#define COMMAND_IA 0x0 /* Interrupt Acknowledge (I)*/
#define COMMAND_SC 0x1 /* Special Cycle (I)*/
#define COMMAND_IO_READ 0x2 /* I/O Read (T)(I) */
#define COMMAND_IO_WRITE 0x3 /* I/O Write (T)(I) */
#define COMMAND_MEM_READ 0x6 /* Memory Read (T)(I) */
#define COMMAND_MEM_WRITE 0x7 /* Memory Write (T)(I) */
#define COMMAND_CONF_READ 0xa /* Configuration Read (T)(I) */
#define COMMAND_CONF_WRITE 0xb /* Configuration Write (T)(I) */
/* PCI target(T)/initiator(I) Interface Commands for PCI_NP_CBE register */
#define COMMAND_NP_IA 0x0 /* Interrupt Acknowledge (I)*/
#define COMMAND_NP_SC 0x1 /* Special Cycle (I)*/
#define COMMAND_NP_IO_READ 0x2 /* I/O Read (T)(I) */
#define COMMAND_NP_IO_WRITE 0x3 /* I/O Write (T)(I) */
#define COMMAND_NP_MEM_READ 0x6 /* Memory Read (T)(I) */
#define COMMAND_NP_MEM_WRITE 0x7 /* Memory Write (T)(I) */
#define COMMAND_NP_CONF_READ 0xa /* Configuration Read (T)(I) */
#define COMMAND_NP_CONF_WRITE 0xb /* Configuration Write (T)(I) */
/* PCI Controller Configuration Commands for PCI_CRP_AD_CBE */
#define COMMAND_CRP_READ 0x0
#define COMMAND_CRP_WRITE (1U << 16)
/*
* SDRAM Configuration Register
*/

51
sys/arch/arm/xscale/ixp425var.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: ixp425var.h,v 1.3 2003/07/02 11:02:29 ichiro Exp $ */
/* $NetBSD: ixp425var.h,v 1.4 2003/09/25 14:11:18 ichiro Exp $ */
/*
* Copyright (c) 2003
@ -44,6 +44,23 @@
#include <dev/pci/pcivar.h>
#define PCI_CSR_WRITE_4(sc, reg, data) \
bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, \
reg, data);
#define PCI_CSR_READ_4(sc, reg) \
bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, reg);
#define GPIO_CONF_WRITE_4(sc, reg, data) \
bus_space_write_4(sc->sc_iot, sc->sc_gpio_ioh, \
reg, data);
#define GPIO_CONF_READ_4(sc, reg) \
bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, reg);
#define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit)
#define PCI_CONF_UNLOCK(s) restore_interrupts((s))
struct ixp425_softc {
struct device sc_dev;
bus_space_tag_t sc_iot;
@ -52,21 +69,23 @@ struct ixp425_softc {
u_int32_t sc_intrmask;
/* Handles for the various subregions. */
/* PCI address */
bus_space_handle_t sc_pci_ioh; /* PCI CSR */
bus_space_handle_t sc_conf0_ioh; /* PCI Configuration 0 */
bus_space_handle_t sc_conf1_ioh; /* PCI Configuration 1 */
/* I/O window vaddr */
bus_space_handle_t sc_pci_ioh; /* PCI mem handler */
bus_space_handle_t sc_gpio_ioh; /* GPIOs handler */
/* Bus space, DMA, and PCI tags for the PCI bus */
struct bus_space ia_pci_iot;
struct bus_space ia_pci_memt;
struct bus_space sc_pci_iot;
struct bus_space sc_pci_memt;
struct arm32_bus_dma_tag ia_pci_dmat;
struct arm32_pci_chipset ia_pci_chipset;
/* DMA window info for PCI DMA. */
struct arm32_dma_range ia_pci_dma_range;
/* GPIO configuration */
u_int32_t sc_gpio_out;
u_int32_t sc_gpio_oe;
u_int32_t sc_gpio_intr1;
u_int32_t sc_gpio_intr2;
};
/*
@ -103,19 +122,25 @@ struct pmap_ent {
int cache;
};
extern struct ixp425_softc *ixp425_softc;
extern struct bus_space ixpsip_bs_tag;
extern struct bus_space ixp425_bs_tag;
void ixp425_bs_init(bus_space_tag_t, void *);
void ixp425_pci_init(pci_chipset_tag_t, void *);
void ixp425_pci_dma_init(struct ixp425_softc *);
void ixp425_io_bs_init(bus_space_tag_t, void *);
void ixp425_mem_bs_init(bus_space_tag_t, void *);
void ixp425_pci_init(pci_chipset_tag_t, void *);
void ixp425_pci_conf_reg_write(struct ixp425_softc *, uint32_t, uint32_t);
uint32_t ixp425_pci_conf_reg_read(struct ixp425_softc *, uint32_t);
void ixp425_attach(struct ixp425_softc *);
void ixp425_icu_init(void);
void ixp425_intr_init(void);
void *ixp425_intr_establish(int, int, int (*)(void *), void *);
void ixp425_intr_disestablish(void *);
#if XXX
void ixp425_expbus_init(void);
#endif
#endif /* _IXP425VAR_H_ */

243
sys/arch/evbarm/conf/IXDP425 Normal file
View File

@ -0,0 +1,243 @@
# $NetBSD: IXDP425,v 1.1 2003/09/25 14:11:18 ichiro Exp $
#
# ZAO425 -- Intel IXP425
#
include "arch/evbarm/conf/std.ixdp425"
#options INCLUDE_CONFIG_FILE # embed config file in kernel binary
# estimated number of users
maxusers 32
# Standard system options
options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
# CPU options
# For XScale systems
options CPU_XSCALE_IXP425 # Support the XScale core
makeoptions CPUFLAGS="-mcpu=xscale"
# Architecture options
options XSCALE_CACHE_READ_WRITE_ALLOCATE
#options HZ=512
# Board Type
makeoptions BOARDTYPE="ixdp425"
# File systems
file-system FFS # UFS
#file-system LFS # log-structured file system
file-system MFS # memory file system
file-system NFS # Network file system
#file-system ADOSFS # AmigaDOS-compatible file system
#file-system EXT2FS # second extended file system (linux)
#file-system CD9660 # ISO 9660 + Rock Ridge file system
#file-system MSDOSFS # MS-DOS file system
file-system FDESC # /dev/fd
file-system KERNFS # /kern
file-system NULLFS # loopback file system
#file-system PORTAL # portal filesystem (still experimental)
file-system PROCFS # /proc
#file-system UMAPFS # NULLFS + uid and gid remapping
#file-system UNION # union file system
# File system options
#options QUOTA # UFS quotas
#options FFS_EI # FFS Endian Independant support
options NFSSERVER
options SOFTDEP
# Networking options
#options GATEWAY # packet forwarding
options INET # IP + ICMP + TCP + UDP
options INET6 # IPV6
#options IPSEC # IP security
#options IPSEC_ESP # IP security (encryption part; define w/ IPSEC)
#options IPSEC_DEBUG # debug for IP security
#options MROUTING # IP multicast routing
#options NS # XNS
#options NSIP # XNS tunneling over IP
#options ISO,TPIP # OSI
#options EON # OSI tunneling over IP
#options CCITT,LLC,HDLC # X.25
#options NETATALK # AppleTalk networking
#options PFIL_HOOKS # pfil(9) packet filter hooks
#options PPP_BSDCOMP # BSD-Compress compression support for PPP
#options PPP_DEFLATE # Deflate compression support for PPP
#options PPP_FILTER # Active filter support for PPP (requires bpf)
#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
options NFS_BOOT_BOOTP
options NFS_BOOT_DHCP
#options NFS_BOOT_BOOTPARAM
# Compatibility options
#options COMPAT_43 # 4.3BSD compatibility.
options COMPAT_16 # NetBSD 1.6 compatibility.
options COMPAT_15 # NetBSD 1.5 compatibility.
options COMPAT_14 # NetBSD 1.4 compatibility.
#options COMPAT_13 # NetBSD 1.3 compatibility.
#options COMPAT_12 # NetBSD 1.2 compatibility.
#options COMPAT_11 # NetBSD 1.1 compatibility.
#options COMPAT_10 # NetBSD 1.0 compatibility.
#options COMPAT_09 # NetBSD 0.9 compatibility.
#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended.
# Shared memory options
options SYSVMSG # System V-like message queues
options SYSVSEM # System V-like semaphores
#options SEMMNI=10 # number of semaphore identifiers
#options SEMMNS=60 # number of semaphores in system
#options SEMUME=10 # max number of undo entries per process
#options SEMMNU=30 # number of undo structures in system
options SYSVSHM # System V-like memory sharing
options SHMMAXPGS=1024 # 1024 pages is the default
# Device options
#options MEMORY_DISK_HOOKS # boottime setup of ramdisk
#options MEMORY_DISK_ROOT_SIZE=3400 # Size in blocks
#options MEMORY_DISK_IS_ROOT # use memory disk as root
# Console options. The default console is speed is 115200 baud.
options CONSPEED=115200 # Console speed
options CONUNIT=0 # Console port number
# Miscellaneous kernel options
options KTRACE # system call tracing, a la ktrace(1)
options IRQSTATS # manage IRQ statistics
#options LKM # loadable kernel modules
#options KMEMSTATS # kernel memory statistics
#options SCSIVERBOSE # Verbose SCSI errors
options PCIVERBOSE # Verbose PCI descriptions
options MIIVERBOSE # Verbose MII autoconfuration messages
#options PCI_CONFIG_DUMP # verbosely dump PCI config space
#options DDB_KEYCODE=0x40
options USERCONF # userconf(4) support
#options PIPE_SOCKETPAIR # smaller, but slower pipe(2)
# Development and Debugging options
#options PERFCTRS # performance counters
options DIAGNOSTIC # internally consistency checks
#options DEBUG
#options PMAP_DEBUG # Enable pmap_debug_level code
#options IPKDB # remote kernel debugging
options VERBOSE_INIT_ARM # verbose bootstraping messages
options DDB # in-kernel debugger
options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
#makeoptions DEBUG="-g" # compile full symbol table
options SYMTAB_SPACE=210000
config netbsd root on ? type ?
# The main bus device
mainbus0 at root
# The boot cpu
cpu0 at mainbus?
# IXP425 slow peripheral
ixpsip0 at mainbus?
#Timer
ixpclk* at ixpsip? addr 0xc8005000 size 0x30
# Status LEDs
ixdpled* at ixpsip? addr 0x52000000 size 0x1000
# On-board device support
ixpcom0 at ixpsip? addr 0xc8000000 size 0x1000 index 0
ixpcom1 at ixpsip? addr 0xc8001000 size 0x1000 index 1
# IXP425 fast bus
ixpio0 at mainbus?
# PCI bus
pci0 at ixpio? bus ?
#
# Networking devices
#
an* at pci? dev ? function ? # Aironet PC4500/PC4800 (802.11)
bge* at pci? dev ? function ? # Broadcom 570x gigabit Ethernet
en* at pci? dev ? function ? # ENI/Adaptec ATM
ep* at pci? dev ? function ? # 3Com 3c59x
epic* at pci? dev ? function ? # SMC EPIC/100 Ethernet
esh* at pci? dev ? function ? # Essential HIPPI card
ex* at pci? dev ? function ? # 3Com 90x[BC]
fpa* at pci? dev ? function ? # DEC DEFPA FDDI
fxp* at pci? dev ? function ? # Intel EtherExpress PRO 10+/100B
gsip* at pci? dev ? function ? # NS83820 Gigabit Ethernet
le* at pci? dev ? function ? # PCnet-PCI Ethernet
lmc* at pci? dev ? function ? # Lan Media Corp SSI/HSSI/DS3
mtd* at pci? dev ? function ? # Myson MTD803 3-in-1 Ethernet
ne* at pci? dev ? function ? # NE2000-compatible Ethernet
ntwoc* at pci? dev ? function ? # Riscom/N2 PCI Sync Serial
pcn* at pci? dev ? function ? # AMD PCnet-PCI Ethernet
rtk* at pci? dev ? function ? # Realtek 8129/8139
sf* at pci? dev ? function ? # Adaptec AIC-6915 Ethernet
sip* at pci? dev ? function ? # SiS 900/DP83815 Ethernet
ste* at pci? dev ? function ? # Sundance ST-201 Ethernet
stge* at pci? dev ? function ? # Sundance/Tamarack TC9021 Gigabit
ti* at pci? dev ? function ? # Alteon ACEnic gigabit Ethernet
tl* at pci? dev ? function ? # ThunderLAN-based Ethernet
tlp* at pci? dev ? function ? # DECchip 21x4x and clones
vr* at pci? dev ? function ? # VIA Rhine Fast Ethernet
wi* at pci? dev ? function ? # Intersil Prism Mini-PCI (802.11b)
wm* at pci? dev ? function ? # Intel 82543/82544 gigabit
# MII/PHY support
acphy* at mii? phy ? # Altima AC101 and AMD Am79c874 PHYs
amhphy* at mii? phy ? # AMD 79c901 Ethernet PHYs
bmtphy* at mii? phy ? # Broadcom BCM5201 and BCM5202 PHYs
brgphy* at mii? phy ? # Broadcom BCM5400-family PHYs
dmphy* at mii? phy ? # Davicom DM9101 PHYs
exphy* at mii? phy ? # 3Com internal PHYs
gentbi* at mii? phy ? # Generic Ten-Bit 1000BASE-[CLS]X PHYs
glxtphy* at mii? phy ? # Level One LXT-1000 PHYs
gphyter* at mii? phy ? # NS83861 Gig-E PHY
icsphy* at mii? phy ? # Integrated Circuit Systems ICS189x
inphy* at mii? phy ? # Intel 82555 PHYs
iophy* at mii? phy ? # Intel 82553 PHYs
lxtphy* at mii? phy ? # Level One LXT-970 PHYs
makphy* at mii? phy ? # Marvell Semiconductor 88E1000 PHYs
nsphy* at mii? phy ? # NS83840 PHYs
nsphyter* at mii? phy ? # NS83843 PHYs
pnaphy* at mii? phy ? # generic HomePNA PHYs
qsphy* at mii? phy ? # Quality Semiconductor QS6612 PHYs
sqphy* at mii? phy ? # Seeq 80220/80221/80223 PHYs
tlphy* at mii? phy ? # ThunderLAN PHYs
tqphy* at mii? phy ? # TDK Semiconductor PHYs
urlphy* at mii? phy ? # Realtek RTL8150L internal PHYs
ukphy* at mii? phy ? # generic unknown PHYs
# Pseudo-Devices
# disk/mass storage pseudo-devices
#pseudo-device md 1 # memory disk device (ramdisk)
pseudo-device vnd 4 # disk-like interface to files
# network pseudo-devices
pseudo-device bpfilter 4 # Berkeley packet filter
pseudo-device loop # network loopback
pseudo-device kttcp # network loopback
# miscellaneous pseudo-devices
pseudo-device pty # pseudo-terminals
pseudo-device rnd # /dev/random and in-kernel generator
pseudo-device clockctl # user control of clock subsystem
pseudo-device ksyms # /dev/ksyms
# data mover pseudo-devices
#pseudo-device swdmover # softare dmover(9) back-end
#pseudo-device dmoverio # /dev/dmover dmover(9) interface

81
sys/arch/evbarm/conf/ZAO425
View File

@ -1,4 +1,4 @@
# $NetBSD: ZAO425,v 1.9 2003/09/13 13:30:07 chris Exp $
# $NetBSD: ZAO425,v 1.10 2003/09/25 14:11:18 ichiro Exp $
#
# ZAO425 -- Intel IXP425
#
@ -132,7 +132,7 @@ options DIAGNOSTIC # internally consistency checks
#options DEBUG
#options PMAP_DEBUG # Enable pmap_debug_level code
#options IPKDB # remote kernel debugging
#options VERBOSE_INIT_ARM # verbose bootstraping messages
options VERBOSE_INIT_ARM # verbose bootstraping messages
options DDB # in-kernel debugger
options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
#makeoptions DEBUG="-g" # compile full symbol table
@ -162,6 +162,83 @@ ixpcom1 at ixpsip? addr 0xc8001000 size 0x1000 index 1
# IXP425 fast bus
ixpio0 at mainbus?
# PCI bus
pci0 at ixpio? bus ?
#
# Networking devices
#
an* at pci? dev ? function ? # Aironet PC4500/PC4800 (802.11)
bge* at pci? dev ? function ? # Broadcom 570x gigabit Ethernet
en* at pci? dev ? function ? # ENI/Adaptec ATM
ep* at pci? dev ? function ? # 3Com 3c59x
epic* at pci? dev ? function ? # SMC EPIC/100 Ethernet
esh* at pci? dev ? function ? # Essential HIPPI card
ex* at pci? dev ? function ? # 3Com 90x[BC]
fpa* at pci? dev ? function ? # DEC DEFPA FDDI
fxp* at pci? dev ? function ? # Intel EtherExpress PRO 10+/100B
gsip* at pci? dev ? function ? # NS83820 Gigabit Ethernet
le* at pci? dev ? function ? # PCnet-PCI Ethernet
lmc* at pci? dev ? function ? # Lan Media Corp SSI/HSSI/DS3
mtd* at pci? dev ? function ? # Myson MTD803 3-in-1 Ethernet
ne* at pci? dev ? function ? # NE2000-compatible Ethernet
ntwoc* at pci? dev ? function ? # Riscom/N2 PCI Sync Serial
pcn* at pci? dev ? function ? # AMD PCnet-PCI Ethernet
rtk* at pci? dev ? function ? # Realtek 8129/8139
sf* at pci? dev ? function ? # Adaptec AIC-6915 Ethernet
sip* at pci? dev ? function ? # SiS 900/DP83815 Ethernet
ste* at pci? dev ? function ? # Sundance ST-201 Ethernet
stge* at pci? dev ? function ? # Sundance/Tamarack TC9021 Gigabit
ti* at pci? dev ? function ? # Alteon ACEnic gigabit Ethernet
tl* at pci? dev ? function ? # ThunderLAN-based Ethernet
tlp* at pci? dev ? function ? # DECchip 21x4x and clones
vr* at pci? dev ? function ? # VIA Rhine Fast Ethernet
wi* at pci? dev ? function ? # Intersil Prism Mini-PCI (802.11b)
wm* at pci? dev ? function ? # Intel 82543/82544 gigabit
# MII/PHY support
acphy* at mii? phy ? # Altima AC101 and AMD Am79c874 PHYs
amhphy* at mii? phy ? # AMD 79c901 Ethernet PHYs
bmtphy* at mii? phy ? # Broadcom BCM5201 and BCM5202 PHYs
brgphy* at mii? phy ? # Broadcom BCM5400-family PHYs
dmphy* at mii? phy ? # Davicom DM9101 PHYs
exphy* at mii? phy ? # 3Com internal PHYs
gentbi* at mii? phy ? # Generic Ten-Bit 1000BASE-[CLS]X PHYs
glxtphy* at mii? phy ? # Level One LXT-1000 PHYs
gphyter* at mii? phy ? # NS83861 Gig-E PHY
icsphy* at mii? phy ? # Integrated Circuit Systems ICS189x
inphy* at mii? phy ? # Intel 82555 PHYs
iophy* at mii? phy ? # Intel 82553 PHYs
lxtphy* at mii? phy ? # Level One LXT-970 PHYs
makphy* at mii? phy ? # Marvell Semiconductor 88E1000 PHYs
nsphy* at mii? phy ? # NS83840 PHYs
nsphyter* at mii? phy ? # NS83843 PHYs
pnaphy* at mii? phy ? # generic HomePNA PHYs
qsphy* at mii? phy ? # Quality Semiconductor QS6612 PHYs
sqphy* at mii? phy ? # Seeq 80220/80221/80223 PHYs
tlphy* at mii? phy ? # ThunderLAN PHYs
tqphy* at mii? phy ? # TDK Semiconductor PHYs
urlphy* at mii? phy ? # Realtek RTL8150L internal PHYs
ukphy* at mii? phy ? # generic unknown PHYs
# CardBus bridge support
#cbb* at pci? dev ? function ?
#cardslot* at cbb?
# CardBus bus support
#cardbus* at cardslot?
#pcmcia* at cardslot?
# PCI USB controllers
#ohci* at pci? dev ? function ? # Open Host Controller
# USB bus support
#usb* at ohci?
# USB Hubs
#uhub* at usb?
#uhub* at uhub? port ? configuration ? interface ?
# Pseudo-Devices
# disk/mass storage pseudo-devices

13
sys/arch/evbarm/conf/files.ixdp425
View File

@ -1,4 +1,4 @@
# $NetBSD: files.ixdp425,v 1.3 2003/05/31 01:16:31 ichiro Exp $
# $NetBSD: files.ixdp425,v 1.4 2003/09/25 14:11:18 ichiro Exp $
#
# Intel IXP425 networkproccesor board configuration info
#
@ -33,3 +33,14 @@ file arch/evbarm/ixdp425/ixdp425_led.c ixdpled needs-flag
# "device" declaration in files.evbarm (because of needs-flag)
attach ixpcom at ixpsip with ixpcom_ixdp
file arch/evbarm/ixdp425/ixpcom_ixdp425.c ixpcom_ixdp
#
# Machine-independent CardBus drivers
#
# XXX dev/pcmcia needs fdc
#device fdc {drive = -1}
#include "dev/pcmcia/files.pcmcia"
#file arch/evbarm/ixdp425/rbus_machdep.c cardbus

4
sys/arch/evbarm/conf/std.ixdp425
View File

@ -1,4 +1,4 @@
# $NetBSD: std.ixdp425,v 1.3 2003/05/24 01:59:32 ichiro Exp $
# $NetBSD: std.ixdp425,v 1.4 2003/09/25 14:11:18 ichiro Exp $
#
# standard NetBSD/evbarm for IXDP425 options
@ -22,4 +22,4 @@ makeoptions BOARDMKFRAG="${THISARM}/conf/mk.ixdp425"
options ARM_INTR_IMPL="<arch/arm/xscale/ixp425_intr.h>"
# We need to configure the PCI bus.
#options PCI_NETBSD_CONFIGURE
options PCI_NETBSD_CONFIGURE

28
sys/arch/evbarm/ixdp425/ixdp425_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: ixdp425_machdep.c,v 1.6 2003/07/15 00:25:05 lukem Exp $ */
/* $NetBSD: ixdp425_machdep.c,v 1.7 2003/09/25 14:11:18 ichiro Exp $ */
/*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
@ -70,7 +70,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ixdp425_machdep.c,v 1.6 2003/07/15 00:25:05 lukem Exp $");
__KERNEL_RCSID(0, "$NetBSD: ixdp425_machdep.c,v 1.7 2003/09/25 14:11:18 ichiro Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@ -314,6 +314,7 @@ cpu_reboot(int howto, char *bootstr)
/* Static device mappings. */
static const struct pmap_devmap ixp425_devmap[] = {
/* Physical/Virtual address for I/O space */
{
IXP425_IO_VBASE,
IXP425_IO_HWBASE,
@ -322,6 +323,7 @@ static const struct pmap_devmap ixp425_devmap[] = {
PTE_NOCACHE,
},
/* Expansion Bus */
{
IXP425_EXP_VBASE,
IXP425_EXP_HWBASE,
@ -329,7 +331,8 @@ static const struct pmap_devmap ixp425_devmap[] = {
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
/* IXP425 PCI Configuration */
{
IXP425_PCI_VBASE,
IXP425_PCI_HWBASE,
@ -338,6 +341,15 @@ static const struct pmap_devmap ixp425_devmap[] = {
PTE_NOCACHE,
},
/* PCI Memory Space */
{
IXP425_PCI_MEM_VBASE,
IXP425_PCI_MEM_HWBASE,
IXP425_PCI_MEM_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
{
0,
0,
@ -398,7 +410,12 @@ initarm(void *arg)
/* XXX overwrite bootconfig to hardcoded values */
bootconfig.dramblocks = 1;
bootconfig.dram[0].address = 0x10000000;
/* XXX */
#if BOARDTYPE == zao425
bootconfig.dram[0].pages = 0x04000000 / PAGE_SIZE; /* SDRAM 64MB */
#elif BOARDTYPE == ixdp425
bootconfig.dram[0].pages = 0x10000000 / PAGE_SIZE; /* SDRAM 256MB */
#endif
kerneldatasize = (u_int32_t)&end - (u_int32_t)KERNEL_TEXT_BASE;
@ -441,7 +458,6 @@ initarm(void *arg)
freemempos = 0x10000000;
#ifdef VERBOSE_INIT_ARM
printf("CP15 Register1 = 0x%08x\n", cpu_get_control());
printf("physical_start = 0x%08lx, physical_end = 0x%08lx\n",
physical_start, physical_end);
#endif
@ -761,13 +777,15 @@ initarm(void *arg)
void
consinit(void)
{
extern struct bus_space ixpsip_bs_tag;
static int consinit_called;
if (consinit_called != 0)
return;
consinit_called = 1;
pmap_devmap_register(ixp425_devmap);
if (ixdp_ixp4xx_comcnattach(&ixpsip_bs_tag, comcnunit,
comcnspeed, FREQ, comcnmode))
panic("can't init serial console (UART%d)", comcnunit);

10
sys/arch/evbarm/ixdp425/ixdp425_mainbus.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: ixdp425_mainbus.c,v 1.2 2003/05/24 01:59:32 ichiro Exp $ */
/* $NetBSD: ixdp425_mainbus.c,v 1.3 2003/09/25 14:11:18 ichiro Exp $ */
/*
* Copyright (c) 2003
@ -34,7 +34,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ixdp425_mainbus.c,v 1.2 2003/05/24 01:59:32 ichiro Exp $");
__KERNEL_RCSID(0, "$NetBSD: ixdp425_mainbus.c,v 1.3 2003/09/25 14:11:18 ichiro Exp $");
/*
* front-end for the ixp425 NetworkProcessor.
@ -60,8 +60,6 @@ static void ixp425_mainbus_attach(struct device *, struct device *, void *);
CFATTACH_DECL(ixpio_mainbus, sizeof(struct ixp425_softc),
ixp425_mainbus_match, ixp425_mainbus_attach, NULL, NULL);
extern struct bus_space ixp425_bs_tag;
int
ixp425_mainbus_match(struct device *parent, struct cfdata *cf, void *aux)
{
@ -73,10 +71,6 @@ ixp425_mainbus_attach(struct device *parent, struct device *self, void *aux)
{
struct ixp425_softc *sc = (void *) self;
ixp425_bs_init(&ixp425_bs_tag, sc);
sc->sc_iot = &ixp425_bs_tag;
sc->sc_ioh = IXP425_IO_VBASE;
/*
* Initialize the interrupt part of our PCI chipset tag
*/

7
sys/arch/evbarm/ixdp425/ixdp425_pci.c
View File

@ -1,4 +1,5 @@
/* $NetBSD: ixdp425_pci.c,v 1.1 2003/05/24 01:59:32 ichiro Exp $ */
/* $NetBSD: ixdp425_pci.c,v 1.2 2003/09/25 14:11:18 ichiro Exp $ */
#define PCI_DEBUG
/*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
@ -33,7 +34,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ixdp425_pci.c,v 1.1 2003/05/24 01:59:32 ichiro Exp $");
__KERNEL_RCSID(0, "$NetBSD: ixdp425_pci.c,v 1.2 2003/09/25 14:11:18 ichiro Exp $");
/*
* IXDP425 PCI interrupt support.
@ -87,7 +88,7 @@ ixdp425_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
printf("ixdp425_pci_intr_map: v=%p, tag=%08lx intrpin=%d line=%d dev=%d\n",
v, intrtag, pin, line, dev);
#endif
switch (pin) {
case 1:
*ihp = PCI_INT_A;

40
sys/arch/evbarm/ixdp425/ixdp425reg.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: ixdp425reg.h,v 1.2 2003/05/24 01:59:32 ichiro Exp $ */
/* $NetBSD: ixdp425reg.h,v 1.3 2003/09/25 14:11:18 ichiro Exp $ */
/*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
@ -36,28 +36,40 @@
#define _IXDP425REG_H_
/*
* GPIO
* Interrupt & GPIO
*/
#if BOARDTYPE == ixdp425
#define PCI_CLK 14
#define PCI_RESET 13
#define PCI_INT_D IXP425_INT_GPIO_11
#define PCI_INT_C IXP425_INT_GPIO_10
#define PCI_INT_B IXP425_INT_GPIO_9
#define PCI_INT_A IXP425_INT_GPIO_8
/* GPIOs */
#define GPIO_PCI_CLK 14
#define GPIO_PCI_RESET 13
#define GPIO_PCI_INTA 11
#define GPIO_PCI_INTB 10
#define GPIO_PCI_INTC 9
#define GPIO_PCI_INTD 8
/* Interrupt */
#define PCI_INT_A IXP425_INT_GPIO_11
#define PCI_INT_B IXP425_INT_GPIO_10
#define PCI_INT_C IXP425_INT_GPIO_9
#define PCI_INT_D IXP425_INT_GPIO_8
#define I2C_SDA IXP425_INT_GPIO_7
#define I2C_SCL IXP425_INT_GPIO_6
#endif /* BOARDTYPE == ixdp425 */
#if BOARDTYPE == zao425 /* conf/ZAO425 */
#define PCI_CLK 14
#define PCI_RESET 13
/* GPIOs */
#define GPIO_PCI_CLK 14
#define GPIO_PCI_RESET 13
#define GPIO_PCI_INTA 11
#define GPIO_PCI_INTB 10
#define GPIO_PCI_INTC 9
#define GPIO_PCI_INTD 8
/* Interrupt */
#define MPCI_GPIO0 IXP425_INT_GPIO_12
#define PCI_INT_D IXP425_INT_GPIO_11
#define PCI_INT_C IXP425_INT_GPIO_10
#define PCI_INT_B IXP425_INT_GPIO_9
#define PCI_INT_A IXP425_INT_GPIO_8
#define PCI_INT_A IXP425_INT_GPIO_11
#define PCI_INT_B IXP425_INT_GPIO_10
#define PCI_INT_C IXP425_INT_GPIO_9
#define PCI_INT_D IXP425_INT_GPIO_8
#define I2C_SDA IXP425_INT_GPIO_7
#define I2C_SCL IXP425_INT_GPIO_6
#define MPCI_GPIO3 IXP425_INT_GPIO_5