Samsung's S3C2800 and S3C24[10]0 CPUs have same built-in UART block,
but there are very small diffs in register definitions. For that, add
new options SSCOM_S3C{2800,2410,2400} and include appropriate
s3c*reg.h.
SSCOM_S3C2410 is also needed for interrupt controller differences.
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@ -1,4 +1,4 @@
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# $NetBSD: files.s3c2xx0,v 1.4 2003/07/31 20:34:15 bsh Exp $
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# $NetBSD: files.s3c2xx0,v 1.5 2003/08/04 12:28:50 bsh Exp $
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#
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# Configuration info common to Samsung S3C2800/S3C24[10]0
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#
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@ -28,7 +28,6 @@ attach sscom at ssio
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file arch/arm/s3c2xx0/sscom.c sscom needs-flag
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defflag opt_sscom.h SSCOM0CONSOLE SSCOM1CONSOLE
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defparam opt_sscom.h SSCOM_FREQ # PCLK
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defflag opt_sscom.h SSCOM_S3C2410
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defflag opt_sscom.h SSCOM_S3C2410 SSCOM_S3C2400 SSCOM_S3C2800
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@ -1,8 +1,8 @@
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/* $NetBSD: s3c2800reg.h,v 1.2 2003/05/12 05:22:31 bsh Exp $ */
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/* $NetBSD: s3c2800reg.h,v 1.3 2003/08/04 12:28:50 bsh Exp $ */
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/*
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* Copyright (c) 2002 Fujitsu Component Limited
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* Copyright (c) 2002 Genetec Corporation
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* Copyright (c) 2002, 2003 Fujitsu Component Limited
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* Copyright (c) 2002, 2003 Genetec Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -239,6 +239,8 @@
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/* UART (Small diffs to S3C2400's UART) */
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#define UMCON_AFC (1<<1) /* auto flow control */
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#define UMSTAT_DCTS (1<<4) /* CTS change */
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#define ULCON_IR (1<<7)
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#define ULCON_PARITY_SHIFT 4
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/* Interrupt controller */
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#define INTCTL_IRQPND 0x0c /* IRQ pending */
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@ -1,8 +1,8 @@
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/* $NetBSD: s3c2xx0reg.h,v 1.2 2003/02/02 08:41:12 bsh Exp $ */
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/* $NetBSD: s3c2xx0reg.h,v 1.3 2003/08/04 12:28:50 bsh Exp $ */
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/*
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* Copyright (c) 2002 Fujitsu Component Limited
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* Copyright (c) 2002 Genetec Corporation
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* Copyright (c) 2002, 2003 Fujitsu Component Limited
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* Copyright (c) 2002, 2003 Genetec Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -40,9 +40,20 @@
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#define _ARM_S3C2XX0_S3C2XX0REG_H_
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/* UART */
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#define SSCOM_ULCON 0x00 /* UART line control */
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#define ULCON_IR (1<<7) /* Infra-Red mode */
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#define ULCON_PARITY_SHIFT 4 /* parity mode */
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/*
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* S3C2800, 2410 and 2400 have a common built-in UART block. However,
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* there are small diffs in bit position of some registers.
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* Following definitions can be foune in s3c{2800,24x0}reg.h for
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* that reason.
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*
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* ULCON_IR (Infra-red mode)
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* ULCON_PARITY_SHIFT (Parity mode bit position)
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* UMCON_AFC (Auto flow control)
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* UMSTAT_DCTS (CTS change)
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*/
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#define SSCOM_ULCON 0x00 /* UART line control */
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/* ULCON_PARITY_SHIFT and ULCON_IR is defined in s3c{2800,24x0}reg.h */
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#define ULCON_PARITY_NONE (0<<ULCON_PARITY_SHIFT)
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#define ULCON_PARITY_ODD (4<<ULCON_PARITY_SHIFT)
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#define ULCON_PARITY_EVEN (5<<ULCON_PARITY_SHIFT)
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@ -85,7 +96,7 @@
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#define UFCON_RXFIFO_RESET (1<<1)
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#define UFCON_FIFO_ENABLE (1<<0)
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#define SSCOM_UMCON 0x0c /* MODEM control */
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/* #define UMCON_AFC (1<<1) */
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/* UMCON_AFC is defined in s3c{2800,24x0}reg.h */
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#define UMCON_RTS (1<<0) /* Request to send */
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#define SSCOM_UTRSTAT 0x10 /* Status register */
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#define UTRSTAT_TXSHIFTER_EMPTY (1<<2)
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@ -105,8 +116,7 @@
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#define UFSTAT_RXCOUNT_SHIFT 0 /* RX FIFO count */
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#define UFSTAT_RXCOUNT (0x0f<<UFSTAT_RXCOUNT_SHIFT)
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#define SSCOM_UMSTAT 0x1c /* Modem status register */
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#define S3C2800_UMSTAT_DCTS (1<<1) /* Clear to send chage */
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#define S3C24X0_UMSTAT_DCTS (1<<2) /* Clear to send chage */
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/* UMSTAT_DCTS is defined in s3c{2800,24x0}reg.h */
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#define UMSTAT_CTS (1<<0) /* Clear to send */
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#if _BYTE_ORDER == _LITTLE_ENDIAN
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#define SSCOM_UTXH 0x20 /* Transmit data register */
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@ -1,4 +1,4 @@
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/* $NetBSD: sscom.c,v 1.9 2003/07/31 19:08:10 bsh Exp $ */
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/* $NetBSD: sscom.c,v 1.10 2003/08/04 12:28:50 bsh Exp $ */
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/*
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* Copyright (c) 2002, 2003 Fujitsu Component Limited
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@ -109,7 +109,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: sscom.c,v 1.9 2003/07/31 19:08:10 bsh Exp $");
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__KERNEL_RCSID(0, "$NetBSD: sscom.c,v 1.10 2003/08/04 12:28:50 bsh Exp $");
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#include "opt_sscom.h"
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#include "opt_ddb.h"
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@ -157,6 +157,11 @@ __KERNEL_RCSID(0, "$NetBSD: sscom.c,v 1.9 2003/07/31 19:08:10 bsh Exp $");
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#include <arm/s3c2xx0/s3c2xx0reg.h>
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#include <arm/s3c2xx0/s3c2xx0var.h>
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#if defined(SSCOM_S3C2410) || defined(SSCOM_S3C2400)
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#include <arm/s3c2xx0/s3c24x0reg.h>
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#elif defined(SSCOM_S3C2800)
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#include <arm/s3c2xx0/s3c2800reg.h>
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#endif
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#include <arm/s3c2xx0/sscom_var.h>
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#include <dev/cons.h>
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@ -1,4 +1,4 @@
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/* $NetBSD: sscom_var.h,v 1.4 2003/07/31 19:08:10 bsh Exp $ */
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/* $NetBSD: sscom_var.h,v 1.5 2003/08/04 12:28:49 bsh Exp $ */
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/*
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* Copyright (c) 2002, 2003 Fujitsu Component Limited
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@ -68,6 +68,7 @@
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#include "opt_multiprocessor.h"
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#include "opt_lockdebug.h"
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#include "opt_sscom.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -76,6 +77,11 @@
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#include <sys/callout.h>
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#include <machine/bus.h>
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#ifdef SSCOM_S3C2410
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#include <arm/s3c2xx0/s3c2410reg.h>
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#include <arm/s3c2xx0/s3c2410var.h>
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#endif
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/* Hardware flag masks */
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#define SSCOM_HW_FLOW 0x02
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#define SSCOM_HW_DEV_OK 0x04
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@ -199,20 +205,55 @@ struct sscom_uart_info {
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#define sscom_getc(iot,ioh) bus_space_read_1((iot), (ioh), SSCOM_URXH)
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#define sscom_geterr(iot,ioh) bus_space_read_1((iot), (ioh), SSCOM_UERSTAT)
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#define sscom_enable_rxint(sc) (s3c2xx0_unmask_interrupts(1<<sc->sc_rx_irqno), \
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(sc->sc_hwflags |= SSCOM_HW_RXINT))
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#define sscom_disable_rxint(sc) (s3c2xx0_mask_interrupts(1<<sc->sc_rx_irqno), \
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(sc->sc_hwflags &= ~SSCOM_HW_RXINT))
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#define sscom_enable_txint(sc) (s3c2xx0_unmask_interrupts(1<<sc->sc_tx_irqno), \
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(sc->sc_hwflags |= SSCOM_HW_TXINT))
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#define sscom_disable_txint(sc) (s3c2xx0_mask_interrupts(1<<sc->sc_tx_irqno), \
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(sc->sc_hwflags &= ~SSCOM_HW_TXINT))
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#define sscom_enable_txrxint(sc) \
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(s3c2xx0_unmask_interrupts((1<<sc->sc_tx_irqno)|(1<<sc->sc_rx_irqno)), \
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(sc->sc_hwflags |= (SSCOM_HW_TXINT|SSCOM_HW_RXINT)))
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#define sscom_disable_txrxint(sc) \
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(s3c2xx0_mask_interrupts((1<<sc->sc_tx_irqno)|(1<<sc->sc_rx_irqno)), \
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(sc->sc_hwflags &= ~(SSCOM_HW_TXINT|SSCOM_HW_RXINT)))
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/*
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* we need to tweak interrupt controller to mask/unmask rxint and/or txint.
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*/
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#ifdef SSCOM_S3C2410
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/* RXINTn, TXINTn and ERRn interrupts are cascaded to UARTn irq. */
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#define _sscom_intbit(irqno) (1<<((irqno)-S3C2410_SUBIRQ_MIN))
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#define sscom_unmask_rxint(sc) \
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s3c2410_unmask_subinterrupts(_sscom_intbit((sc)->sc_rx_irqno))
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#define sscom_mask_rxint(sc) \
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s3c2410_mask_subinterrupts(_sscom_intbit((sc)->sc_rx_irqno))
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#define sscom_unmask_txint(sc) \
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s3c2410_unmask_subinterrupts(_sscom_intbit((sc)->sc_tx_irqno))
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#define sscom_mask_txint(sc) \
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s3c2410_mask_subinterrupts(_sscom_intbit((sc)->sc_tx_irqno))
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#define sscom_unmask_txrxint(sc) \
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s3c2410_unmask_subinterrupts(_sscom_intbit((sc)->sc_tx_irqno) | \
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_sscom_intbit((sc)->sc_rx_irqno))
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#define sscom_mask_txrxint(sc) \
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s3c2410_mask_subinterrupts(_sscom_intbit((sc)->sc_tx_irqno) | \
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_sscom_intbit((sc)->sc_rx_irqno))
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#else
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/* for S3C2800 and S3C2400 */
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#define sscom_unmask_rxint(sc) s3c2xx0_unmask_interrupts(1<<(sc)->sc_rx_irqno)
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#define sscom_mask_rxint(sc) s3c2xx0_mask_interrupts(1<<(sc)->sc_rx_irqno)
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#define sscom_unmask_txint(sc) s3c2xx0_unmask_interrupts(1<<(sc)->sc_tx_irqno)
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#define sscom_mask_txint(sc) s3c2xx0_mask_interrupts(1<<(sc)->sc_tx_irqno)
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#define sscom_unmask_txrxint(sc) \
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s3c2xx0_unmask_interrupts((1<<(sc)->sc_tx_irqno)|(1<<(sc)->sc_rx_irqno))
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#define sscom_mask_txrxint(sc) \
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s3c2xx0_mask_interrupts((1<<(sc)->sc_tx_irqno)|(1<<(sc)->sc_rx_irqno))
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#endif /* SSCOM_S3C2410 */
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#define sscom_enable_rxint(sc) \
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(sscom_unmask_rxint(sc), ((sc)->sc_hwflags |= SSCOM_HW_RXINT))
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#define sscom_disable_rxint(sc) \
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(sscom_mask_rxint(sc), ((sc)->sc_hwflags &= ~SSCOM_HW_RXINT))
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#define sscom_enable_txint(sc) \
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(sscom_unmask_txint(sc), ((sc)->sc_hwflags |= SSCOM_HW_TXINT))
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#define sscom_disable_txint(sc) \
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(sscom_mask_txint(sc),((sc)->sc_hwflags &= ~SSCOM_HW_TXINT))
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#define sscom_enable_txrxint(sc) \
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(sscom_unmask_txrxint(sc),((sc)->sc_hwflags |= (SSCOM_HW_TXINT|SSCOM_HW_RXINT)))
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#define sscom_disable_txrxint(sc) \
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(sscom_mask_txrxint(sc),((sc)->sc_hwflags &= ~(SSCOM_HW_TXINT|SSCOM_HW_RXINT)))
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int sscomspeed(long, long);
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