Samsung's S3C2800 and S3C24[10]0 CPUs have same built-in UART block,
but there are very small diffs in register definitions. For that, add
new options SSCOM_S3C{2800,2410,2400} and include appropriate
s3c*reg.h.
SSCOM_S3C2410 is also needed for interrupt controller differences.
This commit is contained in:
bsh
parent
b335250276
commit
1df8bfd121
|
|
@ -1,4 +1,4 @@
|
|||
# $NetBSD: files.s3c2xx0,v 1.4 2003/07/31 20:34:15 bsh Exp $
|
||||
# $NetBSD: files.s3c2xx0,v 1.5 2003/08/04 12:28:50 bsh Exp $
|
||||
#
|
||||
# Configuration info common to Samsung S3C2800/S3C24[10]0
|
||||
#
|
||||
|
|
@ -28,7 +28,6 @@ attach sscom at ssio
|
|||
file arch/arm/s3c2xx0/sscom.c sscom needs-flag
|
||||
defflag opt_sscom.h SSCOM0CONSOLE SSCOM1CONSOLE
|
||||
defparam opt_sscom.h SSCOM_FREQ # PCLK
|
||||
defflag opt_sscom.h SSCOM_S3C2410
|
||||
|
||||
defflag opt_sscom.h SSCOM_S3C2410 SSCOM_S3C2400 SSCOM_S3C2800
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
/* $NetBSD: s3c2800reg.h,v 1.2 2003/05/12 05:22:31 bsh Exp $ */
|
||||
/* $NetBSD: s3c2800reg.h,v 1.3 2003/08/04 12:28:50 bsh Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002 Fujitsu Component Limited
|
||||
* Copyright (c) 2002 Genetec Corporation
|
||||
* Copyright (c) 2002, 2003 Fujitsu Component Limited
|
||||
* Copyright (c) 2002, 2003 Genetec Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
|
@ -239,6 +239,8 @@
|
|||
/* UART (Small diffs to S3C2400's UART) */
|
||||
#define UMCON_AFC (1<<1) /* auto flow control */
|
||||
#define UMSTAT_DCTS (1<<4) /* CTS change */
|
||||
#define ULCON_IR (1<<7)
|
||||
#define ULCON_PARITY_SHIFT 4
|
||||
|
||||
/* Interrupt controller */
|
||||
#define INTCTL_IRQPND 0x0c /* IRQ pending */
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
/* $NetBSD: s3c2xx0reg.h,v 1.2 2003/02/02 08:41:12 bsh Exp $ */
|
||||
/* $NetBSD: s3c2xx0reg.h,v 1.3 2003/08/04 12:28:50 bsh Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002 Fujitsu Component Limited
|
||||
* Copyright (c) 2002 Genetec Corporation
|
||||
* Copyright (c) 2002, 2003 Fujitsu Component Limited
|
||||
* Copyright (c) 2002, 2003 Genetec Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
|
@ -40,9 +40,20 @@
|
|||
#define _ARM_S3C2XX0_S3C2XX0REG_H_
|
||||
|
||||
/* UART */
|
||||
#define SSCOM_ULCON 0x00 /* UART line control */
|
||||
#define ULCON_IR (1<<7) /* Infra-Red mode */
|
||||
#define ULCON_PARITY_SHIFT 4 /* parity mode */
|
||||
/*
|
||||
* S3C2800, 2410 and 2400 have a common built-in UART block. However,
|
||||
* there are small diffs in bit position of some registers.
|
||||
* Following definitions can be foune in s3c{2800,24x0}reg.h for
|
||||
* that reason.
|
||||
*
|
||||
* ULCON_IR (Infra-red mode)
|
||||
* ULCON_PARITY_SHIFT (Parity mode bit position)
|
||||
* UMCON_AFC (Auto flow control)
|
||||
* UMSTAT_DCTS (CTS change)
|
||||
*/
|
||||
|
||||
#define SSCOM_ULCON 0x00 /* UART line control */
|
||||
/* ULCON_PARITY_SHIFT and ULCON_IR is defined in s3c{2800,24x0}reg.h */
|
||||
#define ULCON_PARITY_NONE (0<<ULCON_PARITY_SHIFT)
|
||||
#define ULCON_PARITY_ODD (4<<ULCON_PARITY_SHIFT)
|
||||
#define ULCON_PARITY_EVEN (5<<ULCON_PARITY_SHIFT)
|
||||
|
|
@ -85,7 +96,7 @@
|
|||
#define UFCON_RXFIFO_RESET (1<<1)
|
||||
#define UFCON_FIFO_ENABLE (1<<0)
|
||||
#define SSCOM_UMCON 0x0c /* MODEM control */
|
||||
/* #define UMCON_AFC (1<<1) */
|
||||
/* UMCON_AFC is defined in s3c{2800,24x0}reg.h */
|
||||
#define UMCON_RTS (1<<0) /* Request to send */
|
||||
#define SSCOM_UTRSTAT 0x10 /* Status register */
|
||||
#define UTRSTAT_TXSHIFTER_EMPTY (1<<2)
|
||||
|
|
@ -105,8 +116,7 @@
|
|||
#define UFSTAT_RXCOUNT_SHIFT 0 /* RX FIFO count */
|
||||
#define UFSTAT_RXCOUNT (0x0f<<UFSTAT_RXCOUNT_SHIFT)
|
||||
#define SSCOM_UMSTAT 0x1c /* Modem status register */
|
||||
#define S3C2800_UMSTAT_DCTS (1<<1) /* Clear to send chage */
|
||||
#define S3C24X0_UMSTAT_DCTS (1<<2) /* Clear to send chage */
|
||||
/* UMSTAT_DCTS is defined in s3c{2800,24x0}reg.h */
|
||||
#define UMSTAT_CTS (1<<0) /* Clear to send */
|
||||
#if _BYTE_ORDER == _LITTLE_ENDIAN
|
||||
#define SSCOM_UTXH 0x20 /* Transmit data register */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: sscom.c,v 1.9 2003/07/31 19:08:10 bsh Exp $ */
|
||||
/* $NetBSD: sscom.c,v 1.10 2003/08/04 12:28:50 bsh Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002, 2003 Fujitsu Component Limited
|
||||
|
|
@ -109,7 +109,7 @@
|
|||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: sscom.c,v 1.9 2003/07/31 19:08:10 bsh Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: sscom.c,v 1.10 2003/08/04 12:28:50 bsh Exp $");
|
||||
|
||||
#include "opt_sscom.h"
|
||||
#include "opt_ddb.h"
|
||||
|
|
@ -157,6 +157,11 @@ __KERNEL_RCSID(0, "$NetBSD: sscom.c,v 1.9 2003/07/31 19:08:10 bsh Exp $");
|
|||
|
||||
#include <arm/s3c2xx0/s3c2xx0reg.h>
|
||||
#include <arm/s3c2xx0/s3c2xx0var.h>
|
||||
#if defined(SSCOM_S3C2410) || defined(SSCOM_S3C2400)
|
||||
#include <arm/s3c2xx0/s3c24x0reg.h>
|
||||
#elif defined(SSCOM_S3C2800)
|
||||
#include <arm/s3c2xx0/s3c2800reg.h>
|
||||
#endif
|
||||
#include <arm/s3c2xx0/sscom_var.h>
|
||||
#include <dev/cons.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: sscom_var.h,v 1.4 2003/07/31 19:08:10 bsh Exp $ */
|
||||
/* $NetBSD: sscom_var.h,v 1.5 2003/08/04 12:28:49 bsh Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2002, 2003 Fujitsu Component Limited
|
||||
|
|
@ -68,6 +68,7 @@
|
|||
|
||||
#include "opt_multiprocessor.h"
|
||||
#include "opt_lockdebug.h"
|
||||
#include "opt_sscom.h"
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
|
|
@ -76,6 +77,11 @@
|
|||
#include <sys/callout.h>
|
||||
#include <machine/bus.h>
|
||||
|
||||
#ifdef SSCOM_S3C2410
|
||||
#include <arm/s3c2xx0/s3c2410reg.h>
|
||||
#include <arm/s3c2xx0/s3c2410var.h>
|
||||
#endif
|
||||
|
||||
/* Hardware flag masks */
|
||||
#define SSCOM_HW_FLOW 0x02
|
||||
#define SSCOM_HW_DEV_OK 0x04
|
||||
|
|
@ -199,20 +205,55 @@ struct sscom_uart_info {
|
|||
#define sscom_getc(iot,ioh) bus_space_read_1((iot), (ioh), SSCOM_URXH)
|
||||
#define sscom_geterr(iot,ioh) bus_space_read_1((iot), (ioh), SSCOM_UERSTAT)
|
||||
|
||||
#define sscom_enable_rxint(sc) (s3c2xx0_unmask_interrupts(1<<sc->sc_rx_irqno), \
|
||||
(sc->sc_hwflags |= SSCOM_HW_RXINT))
|
||||
#define sscom_disable_rxint(sc) (s3c2xx0_mask_interrupts(1<<sc->sc_rx_irqno), \
|
||||
(sc->sc_hwflags &= ~SSCOM_HW_RXINT))
|
||||
#define sscom_enable_txint(sc) (s3c2xx0_unmask_interrupts(1<<sc->sc_tx_irqno), \
|
||||
(sc->sc_hwflags |= SSCOM_HW_TXINT))
|
||||
#define sscom_disable_txint(sc) (s3c2xx0_mask_interrupts(1<<sc->sc_tx_irqno), \
|
||||
(sc->sc_hwflags &= ~SSCOM_HW_TXINT))
|
||||
#define sscom_enable_txrxint(sc) \
|
||||
(s3c2xx0_unmask_interrupts((1<<sc->sc_tx_irqno)|(1<<sc->sc_rx_irqno)), \
|
||||
(sc->sc_hwflags |= (SSCOM_HW_TXINT|SSCOM_HW_RXINT)))
|
||||
#define sscom_disable_txrxint(sc) \
|
||||
(s3c2xx0_mask_interrupts((1<<sc->sc_tx_irqno)|(1<<sc->sc_rx_irqno)), \
|
||||
(sc->sc_hwflags &= ~(SSCOM_HW_TXINT|SSCOM_HW_RXINT)))
|
||||
/*
|
||||
* we need to tweak interrupt controller to mask/unmask rxint and/or txint.
|
||||
*/
|
||||
#ifdef SSCOM_S3C2410
|
||||
/* RXINTn, TXINTn and ERRn interrupts are cascaded to UARTn irq. */
|
||||
|
||||
#define _sscom_intbit(irqno) (1<<((irqno)-S3C2410_SUBIRQ_MIN))
|
||||
|
||||
#define sscom_unmask_rxint(sc) \
|
||||
s3c2410_unmask_subinterrupts(_sscom_intbit((sc)->sc_rx_irqno))
|
||||
#define sscom_mask_rxint(sc) \
|
||||
s3c2410_mask_subinterrupts(_sscom_intbit((sc)->sc_rx_irqno))
|
||||
#define sscom_unmask_txint(sc) \
|
||||
s3c2410_unmask_subinterrupts(_sscom_intbit((sc)->sc_tx_irqno))
|
||||
#define sscom_mask_txint(sc) \
|
||||
s3c2410_mask_subinterrupts(_sscom_intbit((sc)->sc_tx_irqno))
|
||||
#define sscom_unmask_txrxint(sc) \
|
||||
s3c2410_unmask_subinterrupts(_sscom_intbit((sc)->sc_tx_irqno) | \
|
||||
_sscom_intbit((sc)->sc_rx_irqno))
|
||||
#define sscom_mask_txrxint(sc) \
|
||||
s3c2410_mask_subinterrupts(_sscom_intbit((sc)->sc_tx_irqno) | \
|
||||
_sscom_intbit((sc)->sc_rx_irqno))
|
||||
|
||||
#else
|
||||
|
||||
/* for S3C2800 and S3C2400 */
|
||||
#define sscom_unmask_rxint(sc) s3c2xx0_unmask_interrupts(1<<(sc)->sc_rx_irqno)
|
||||
#define sscom_mask_rxint(sc) s3c2xx0_mask_interrupts(1<<(sc)->sc_rx_irqno)
|
||||
#define sscom_unmask_txint(sc) s3c2xx0_unmask_interrupts(1<<(sc)->sc_tx_irqno)
|
||||
#define sscom_mask_txint(sc) s3c2xx0_mask_interrupts(1<<(sc)->sc_tx_irqno)
|
||||
#define sscom_unmask_txrxint(sc) \
|
||||
s3c2xx0_unmask_interrupts((1<<(sc)->sc_tx_irqno)|(1<<(sc)->sc_rx_irqno))
|
||||
#define sscom_mask_txrxint(sc) \
|
||||
s3c2xx0_mask_interrupts((1<<(sc)->sc_tx_irqno)|(1<<(sc)->sc_rx_irqno))
|
||||
|
||||
#endif /* SSCOM_S3C2410 */
|
||||
|
||||
#define sscom_enable_rxint(sc) \
|
||||
(sscom_unmask_rxint(sc), ((sc)->sc_hwflags |= SSCOM_HW_RXINT))
|
||||
#define sscom_disable_rxint(sc) \
|
||||
(sscom_mask_rxint(sc), ((sc)->sc_hwflags &= ~SSCOM_HW_RXINT))
|
||||
#define sscom_enable_txint(sc) \
|
||||
(sscom_unmask_txint(sc), ((sc)->sc_hwflags |= SSCOM_HW_TXINT))
|
||||
#define sscom_disable_txint(sc) \
|
||||
(sscom_mask_txint(sc),((sc)->sc_hwflags &= ~SSCOM_HW_TXINT))
|
||||
#define sscom_enable_txrxint(sc) \
|
||||
(sscom_unmask_txrxint(sc),((sc)->sc_hwflags |= (SSCOM_HW_TXINT|SSCOM_HW_RXINT)))
|
||||
#define sscom_disable_txrxint(sc) \
|
||||
(sscom_mask_txrxint(sc),((sc)->sc_hwflags &= ~(SSCOM_HW_TXINT|SSCOM_HW_RXINT)))
|
||||
|
||||
|
||||
int sscomspeed(long, long);
|
||||
|
|
|
|||
Loading…
Reference in New Issue