Stanislav Shwartsman
42a0a178eb
disasm for XOP instructions
2011-10-30 08:58:49 +00:00
Stanislav Shwartsman
5cc04b9955
Implemented AMDs Buldozer XOP and TBM extensions.
...
XOP: few instructions are still missing, coming soon
BX_PANIC(("VPERMILPS_VpsHpsWpsVIbR: not implemented yet"));
BX_PANIC(("VPERMILPD_VpdHpdWpdVIbR: not implemented yet"));
BX_PANIC(("VPMADCSSWD_VdqHdqWdqVIbR: not implemented yet"));
BX_PANIC(("VPMADCSWD_VdqHdqWdqVIbR: not implemented yet"));
BX_PANIC(("VFRCZPS_VpsWpsR: not implemented yet"));
BX_PANIC(("VFRCZPD_VpdWpdR: not implemented yet"));
BX_PANIC(("VFRCZSS_VssWssR: not implemented yet"));
BX_PANIC(("VFRCZSD_VsdWsdR: not implemented yet"));
2011-10-19 20:54:04 +00:00
Stanislav Shwartsman
aad57310c2
disasm for FMA4, better dbg print SSE rounding control with MXCSR
2011-10-06 20:33:10 +00:00
Stanislav Shwartsman
e3dae7adb1
added disasm for avx fma instructions
2011-09-29 19:50:27 +00:00
Stanislav Shwartsman
8c7a60b3cb
fixed typo in sse4a disasm
2011-09-20 15:15:02 +00:00
Stanislav Shwartsman
50207eeb90
- Added support for AMD SSE4A emulation, the instructions can be enabled
...
using .bochsrc CPUID option.
2011-09-18 16:18:22 +00:00
Stanislav Shwartsman
e2f0880f1c
support more than 32-bit cpu features vector
2011-09-14 20:22:24 +00:00
Stanislav Shwartsman
3f230d115e
clean disasm opcodes.inc
2011-09-13 20:43:15 +00:00
Stanislav Shwartsman
cf56ffb6e0
BSF/BSR should stay, only F3 prefix change opcode
2011-08-31 21:13:50 +00:00
Stanislav Shwartsman
1f5e036695
lzcnt/tzcnt bmi instructions implemented
2011-08-31 20:43:47 +00:00
Stanislav Shwartsman
9693bacacb
syscall/sysret in legacy mode is supported in k6-2. preparing code to it ...
2011-08-30 20:41:00 +00:00
Stanislav Shwartsman
1328861175
typo fix
2011-08-28 21:41:54 +00:00
Stanislav Shwartsman
1dc8f56f06
disasm for AVX2 gather
2011-08-28 21:38:53 +00:00
Stanislav Shwartsman
44241a1e56
- Added support for AVX and AVX2 instructions emulation, to enable configure
...
with --enable-avx option. When compiled in, AVX still has to be enabled
using .bochsrc CPUID option. AVX2 FMA instructions still not implemented.
- Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
instructions support can be enabled using .bochsrc CPUID option.
2011-08-27 13:47:16 +00:00
Stanislav Shwartsman
d841e82d87
MOVBE instruction exists only in memory form
2011-08-25 21:20:50 +00:00
Stanislav Shwartsman
e796e6a96c
disasm avx2 new instructions (no gather yet)
2011-08-24 20:55:23 +00:00
Stanislav Shwartsman
638a834c4a
remove redundant code
2011-08-22 17:19:04 +00:00
Stanislav Shwartsman
ed9b8478b5
undo RDTSC commit
2011-08-17 21:13:06 +00:00
Stanislav Shwartsman
165e6f0fdf
separate TSC to uniq feature that can be disabled in CPU configuration
2011-08-17 20:57:44 +00:00
Stanislav Shwartsman
35ec48d17d
small fixes
2011-08-13 18:39:17 +00:00
Stanislav Shwartsman
8962cfddde
re-definition of x86-64 support, 1st step towards x86-64 enable/disable through .bochsrc
2011-08-12 18:04:56 +00:00
Stanislav Shwartsman
6344c6a719
Added P2 Klamath CPUID + some code reorg again
2011-08-11 18:06:09 +00:00
Stanislav Shwartsman
5ea65d1753
fix for disasm
2011-08-10 22:11:12 +00:00
Stanislav Shwartsman
d84dbcd02b
fixed *x86 ISA extensions that enable this instruction* in ia_opcodes.h
2011-07-31 20:09:04 +00:00
Stanislav Shwartsman
e48765a511
VMX fixed, cleanups
2011-07-29 20:22:35 +00:00
Stanislav Shwartsman
3f075d1ddf
disasm for invpcid
2011-06-10 12:49:52 +00:00
Stanislav Shwartsman
c262a1b442
disasm fix for AVX
2011-05-30 20:32:59 +00:00
Stanislav Shwartsman
04e9254e2c
AMD released new Vol4: 128 and 256 bit vector instructions, dropped SSE4A
2011-05-30 20:15:50 +00:00
Stanislav Shwartsman
5230bd27ee
added/fixed comments
2011-04-21 15:51:36 +00:00
Stanislav Shwartsman
024a1ace38
move X2APIC to be .bochsrc option, rework of the cpuid code
2011-04-21 13:27:42 +00:00
Volker Ruppert
c78026a9a2
- deleted executable properties from source files
2011-04-03 10:29:19 +00:00
Stanislav Shwartsman
7664c55b08
first fixups after AVX
...
(and for AVX)
2011-03-20 18:27:31 +00:00
Stanislav Shwartsman
7ced718040
implemented AVX instructions support
...
many changes - some cleanup will follow
please report ay found bugs !
2011-03-19 20:09:34 +00:00
Stanislav Shwartsman
00981cd7a6
Adding Id and Rev property to all files
2011-02-24 22:05:47 +00:00
Stanislav Shwartsman
4a8d69caf6
bugfix for x86-64 mode
2010-11-23 15:42:26 +00:00
Stanislav Shwartsman
9aa503cb9d
fixed warnings for win64 compilation
2010-11-23 14:59:36 +00:00
Stanislav Shwartsman
dc72673bb3
Fixed arpl disasm
2010-10-11 15:33:11 +00:00
Stanislav Shwartsman
7f7c249934
disasm and some cpuid code according to recently published AVX_319433-007.pdf document
2010-07-22 15:12:08 +00:00
Stanislav Shwartsman
ecde5ffea9
simplify disasm tables
2010-05-23 20:30:23 +00:00
Stanislav Shwartsman
2dbe559ad9
simpler disasm tables
2010-05-23 20:05:14 +00:00
Stanislav Shwartsman
8d8d1590f5
fetchdecide rework for AVX (0xF3 SSE prefix encoded as 2 in VEX)
2010-05-23 19:17:41 +00:00
Stanislav Shwartsman
6e1204cb84
Merged X2APIC + X2APIC virtualization
2010-04-08 15:50:39 +00:00
Stanislav Shwartsman
69517f9143
Fix PEXTRB/PEXTRW/PEXTRD/EXTRACTPS
2010-04-02 19:01:17 +00:00
Stanislav Shwartsman
2efb11f2bc
fixes
2010-03-30 18:12:19 +00:00
Stanislav Shwartsman
cceb0a5a17
invept/invvpid disasm
2010-03-26 10:39:40 +00:00
Stanislav Shwartsman
674724122a
bugfix
2010-03-21 20:03:17 +00:00
Stanislav Shwartsman
9147ac4b63
MOVMSKPD/PS fix
2010-03-19 14:43:13 +00:00
Stanislav Shwartsman
c4412bf357
movdq2q fix
2010-03-19 10:44:02 +00:00
Stanislav Shwartsman
0ead9fe8ae
new opcode grp
2010-03-07 08:08:40 +00:00
Stanislav Shwartsman
70dc124b3a
1st step of moving CPU options to runtime
2010-02-24 19:27:51 +00:00
