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1149 Commits

Author SHA1 Message Date
Stanislav Shwartsman
1b9e0081b4 fixed bugs in recently implemented load methods with fault suppression support 2019-12-19 21:36:13 +00:00
Stanislav Shwartsman
59cad2e156 AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come 2019-12-19 21:12:23 +00:00
Stanislav Shwartsman
2df60c3b3f AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come 2019-12-19 20:08:49 +00:00
Stanislav Shwartsman
eca847c8b3 fixed compilation error 2019-12-16 19:47:41 +00:00
Stanislav Shwartsman
895c4b75df rewritten xsave/xrestore implementation in generic way to simplify adding new xsave/xrestore extensions 2019-12-16 16:14:51 +00:00
Stanislav Shwartsman
bcfcaf3958 unify branch_far32 and branhc_far64 methods 2019-12-14 17:20:35 +00:00
Stanislav Shwartsman
e35fcd1782 clarify err message 2019-12-10 20:38:45 +00:00
Stanislav Shwartsman
4b66fecaad split Bochs CPU TLB to DTLB and ITLB to avoid aliasing conflicts between them. ~5% speedup measured 2019-12-09 18:37:02 +00:00
Stanislav Shwartsman
8befc3bf82 make separate class for TLB to be used in CPU class. preparation to DTLB and ITLB split of TLB structure 2019-12-09 16:49:51 +00:00
Stanislav Shwartsman
44b3ebeca2 remove BX_TRUE/BX_FALSE macros, use stdc++ true/false instead 2019-12-09 16:44:36 +00:00
Stanislav Shwartsman
12d228abde split vmx initialization to multiple methods for better code readability, improve VMX error messages 2019-12-08 20:46:51 +00:00
Stanislav Shwartsman
06d826755b increase max configurable msrs to 0x1000 again 2019-12-06 12:31:51 +00:00
Stanislav Shwartsman
0c75e0beaf extract xcr0_support bits calculation to a function 2019-12-06 09:23:28 +00:00
Stanislav Shwartsman
4e9e3f85de simplify code by merging two opcodes with similar behavior 2019-11-27 15:31:32 +00:00
Stanislav Shwartsman
d766cc8112 implemented SCA (Side-Channel-Attack) Prevention reporting and corresponding MSR registers, enabled for Icelake-U CPU definition 2019-10-26 20:09:30 +00:00
Stanislav Shwartsman
bb5ccc97c1 remove unused function parameter 2019-10-16 19:53:04 +00:00
Stanislav Shwartsman
9c61e9e9f5 remove unused function parameter 2019-10-16 19:48:21 +00:00
Stanislav Shwartsman
10c23b5d39 implement fasstring for 64-bit mode as well 2019-10-14 19:50:47 +00:00
Stanislav Shwartsman
ee3f1b91a3 allow fast string only for forward strings and simplify the code 2019-10-14 14:45:01 +00:00
Stanislav Shwartsman
f0245b5f2b introduce special handlers for zero-idiom instructions - ~1% speedup to simulation. infra for fast string emulation in 64-bit mode 2019-10-14 06:40:19 +00:00
Stanislav Shwartsman
2ae332cce8 patch by Luigu.B - significantly speedup multi-threaded guest simulation 2019-08-09 19:57:13 +00:00
Stanislav Shwartsman
4d10852c04 impemented recently published VP2INTERSECTD/Q instructions 2019-05-25 19:07:09 +00:00
Stanislav Shwartsman
f8ec18acd5 fix decode/disasm of AVX512-VBMI2 VPSH*D* opcodes 2019-01-27 18:52:03 +00:00
Stanislav Shwartsman
965bcc2606 support 64-bit in 'info tab' debugger command and also speed it up significantly 2018-08-14 08:09:09 +00:00
Stanislav Shwartsman
fd15b61d94 keep def of YMM/ZMM register even if AVX or EVEX are not compiled in and let reading/writing them to MEM 2018-04-04 19:31:56 +00:00
Stanislav Shwartsman
773f1b7e42 cleanup return value of all instruction handlers 2018-02-16 07:57:32 +00:00
Stanislav Shwartsman
2bca4cc310 improve debug print for SPP access 2018-01-27 21:25:46 +00:00
Stanislav Shwartsman
afc2ee6bfd Implemented SPP: EPT-Based Subpage Protection. Cleaned code duplication between FXSAVE/FXRSTORE and XSAVE/XRSTOR (save/restore of SSE code is the same) 2018-01-27 21:20:33 +00:00
Stanislav Shwartsman
ca034f0642 fixed disasm of sse insertps instruction 2017-12-21 18:18:10 +00:00
Stanislav Shwartsman
e086f7ba19 split INSERTPS opcode to reg and mem forms 2017-12-19 19:25:40 +00:00
Stanislav Shwartsman
5dc5e01a12 disasm fixes and reorg of pinsr* opcodes 2017-12-16 18:34:20 +00:00
Stanislav Shwartsman
50a799ea11 split handlers for PINSRD/Q opcodes. fix disasm for MULX instruction 2017-12-13 20:18:59 +00:00
Stanislav Shwartsman
8a311515dd correctly decode VPEXTRB/W/D/Q - these opcodes allowed to be with VEX.L=0 only 
fixed disasm module compilation with no AVX enabled
remove duplicate opcode handlers
 2017-12-13 19:51:25 +00:00
Stanislav Shwartsman
596b3b6eb8 reduce CPU dependencies from fetchdecode module 2017-11-25 20:20:34 +00:00
Stanislav Shwartsman
8261a91ce9 implemented GFNI instructions 2017-10-21 19:57:12 +00:00
Stanislav Shwartsman
77a62a4dcd implemented (experimental, still untested) AVX512 VBMI2 extensions 2017-10-20 18:38:15 +00:00
Stanislav Shwartsman
ba1e5bbffa fixed accidentially broken XMM versions of AES instrructions 2017-10-19 20:25:05 +00:00
Stanislav Shwartsman
15ba88c195 implemented VAES/VPCLMULDQ instructions - VEX/EVEX extensions of AES/PCLMULQDQ 2017-10-19 19:12:55 +00:00
Stanislav Shwartsman
ac442009aa lazy flags code small refactoring 2017-10-15 22:01:32 +00:00
Stanislav Shwartsman
944f37b1f2 implemented AVX-512 BITALG instructions/bugfix for VPOPCNT instructions 2017-10-15 20:33:19 +00:00
Stanislav Shwartsman
0d190eec8e implemented AVX-512 VNNI instructions 2017-10-15 19:17:07 +00:00
Stanislav Shwartsman
1abfcd39ff implement FOPCODE and FDP deprecation CPU features 2017-05-05 20:56:13 +00:00
Stanislav Shwartsman
097310cd00 fixed integer overflow while computing shift flags, avoid using bx_bool while working with flags for more robust code 2017-03-30 21:53:39 +00:00
Stanislav Shwartsman
a673612784 fixed permission checks performed by CLFLUSH/CLFLUSHOPT/MONITOR* instructions 2017-03-28 18:52:53 +00:00
Stanislav Shwartsman
2b79061127 Implemented MONITORX/MWAITX instructions (AMD), enabled in Ryzen CPU model 2017-03-26 19:14:15 +00:00
Stanislav Shwartsman
411ea954b4 implemented CLZERO instruction from AMD Ryzen CPU 2017-03-25 20:12:31 +00:00
Stanislav Shwartsman
15d9b068a3 fix msvc warnings 2017-03-17 17:35:15 +00:00
Stanislav Shwartsman
3a033fa6db implemented xsaves/xrstors extensions (supported by Intel Skylake core and AMD Ryzen) 2017-03-15 21:44:15 +00:00
Stanislav Shwartsman
9bd99a604f implemented recently announced AVX-512 extension VPOPCNT 2016-12-17 13:47:45 +00:00
Stanislav Shwartsman
7a34f00f99 extracted fetchdecode into separated folder under cpu and also out of BX_CPU_C class into stand-alone module. Next step: wrap it up nicely and define clear interace to CPU model to minimize dependencies. Ideally I need fetchdecode to not include CPU at all 2016-06-12 21:23:48 +00:00
Stanislav Shwartsman
8824539630 fix code duplication in segload instr emulation 2016-06-01 20:11:54 +00:00
Stanislav Shwartsman
e24c7e403a take a funtion from BX_CPU_C:: into fetchdecode.cc standalone function 2016-04-30 19:13:15 +00:00
Stanislav Shwartsman
793ceb0d8c fix massive code dupliction between disasm, debugger and cpu by introducing new cpu decoder.h header 2016-04-29 21:01:28 +00:00
Stanislav Shwartsman
cc49b504b3 fix small issue on the way to Bochs decoder separation into stand-alone module 2016-04-26 12:46:44 +00:00
Stanislav Shwartsman
adc143684b implemented Intel architecture extensions published in recently published SDM 058: 
! Implemented UMIP: User Mode Instruction Prevention (don't allow execution of SLDT/SIDT/SGDT/STR/SMSW with CPL>0)
! Implemented RDPID instruction

Bugfixes in RDPKRU/WRPKRU instructions implementation (Protection Keys feature)
 2016-04-15 11:35:32 +00:00
Stanislav Shwartsman
e4832af5ab clean pkeys when not enabled to avoid side-effects 2016-03-19 21:15:56 +00:00
Stanislav Shwartsman
bcb36e81fa experimental implementation of protection keys paging extension published in SDM rev054. to enable configure with --enable-protection-keys 2016-03-02 20:44:42 +00:00
Stanislav Shwartsman
9308ad31c6 remove unused param from serveIcacheMiss 2016-02-22 19:57:24 +00:00
Stanislav Shwartsman
9557cafcef revertng commit #12854 because it broke MT simulation with debugger enabled. Until investigted. 2015-12-20 22:44:54 +00:00
Stanislav Shwartsman
a8a325f2f5 #define to enum or inline function convertion 2015-10-09 19:33:36 +00:00
Stanislav Shwartsman
9f77a6c3b0 full debugger support together with handler-chaining speedups optimization enabled (experimental) 
should speedup emulation with debugger enabled
 2015-10-09 05:28:47 +00:00
Stanislav Shwartsman
be4b73c6d2 extracted tlb specific code to tlb.h; extracted xsave cpuid leaf function to base cpuid class 2015-09-21 13:16:17 +00:00
Stanislav Shwartsman
f6af0443bb small optimization and elimination of several defines from cpu.h - replace by inline functions and const variables 2015-07-13 20:24:14 +00:00
Stanislav Shwartsman
5fe1423ab6 introducr new class for VMCS mapping so it can be customized per cpuid 2015-07-06 18:46:57 +00:00
Stanislav Shwartsman
c43ea147bf ~1% emulation speedup by skipping pageWriteStamp check for stack writes. 
For now the optimization is supported only when no SMP is compiled in because it doesn't handle cross-modifying code.

The current stack page will cache also current pageWriteStamp for that page and could skip pageWriteStamp access if possible.
Any code fetch access missing trace cache will invalidate current stack page.
Code fetch accesses from another SMP threads should do the same to support SMP.

Next step:
 - support SMP
 - support pageWriteStamp access skipping for all other memory writes from all segments
 2015-05-23 19:34:59 +00:00
Stanislav Shwartsman
b468316250 re-style old resolve macros after resolve function inlining 2015-05-16 21:06:59 +00:00
Stanislav Shwartsman
f0d7379908 remove BxResolveModrm member in BxInstruction_c class and inline resolve functions into instruction handlers instead. helps to remove indirect branch mispredictions (suggested by Vtune). measured speedup on Win7-64 boot is 5%, on other guests it might vary between 1% and 5% 2015-05-16 20:29:49 +00:00
Stanislav Shwartsman
9f18573740 Rename BX_CPU_CALL_METHODR to BX_CPU_RESOLVE_ADDR and introduce special cases BX_CPU_RESOLVE_ADDR_64 (for 64-bit mode only) and BX_CPU_RESOLVE_ADDR_32 (for 32-bit mode only) 2015-05-11 19:23:09 +00:00
Stanislav Shwartsman
b9b45f0d0d convert some defines to typed consts 2015-05-10 19:54:57 +00:00
Stanislav Shwartsman
0d79c5f986 Implemented Page Modification Logging VMX feature 2015-05-06 19:55:44 +00:00
Stanislav Shwartsman
c360ddf60c correctly report memory type for EPT page table accesses 
TODO: support memory type for guest physical access under EPT
TODO: support memory type for SVM nested paging 
TODO: check what happens when PAT is not enabled in CPU configuration
 2015-03-23 20:27:36 +00:00
Stanislav Shwartsman
a55c5e4eb8 correctly report memory type for page table accesses in x86 mode (not in EPT or SVM nested paging yet) 
TODO: support memory type with EPT / nested paging
TODO: check what happens when PAT is not enabled in CPU configuration
 2015-03-21 20:08:58 +00:00
Stanislav Shwartsman
e79185b0a0 refactor memtype methods 2015-03-02 20:51:59 +00:00
Stanislav Shwartsman
25b02dac4b code reorg before PAT memory type support 2015-02-28 14:01:11 +00:00
Stanislav Shwartsman
1e1c893041 introduce new 64bit packed register type and implement pat/mtrr and mmx registers through it 2015-02-23 21:17:33 +00:00
Stanislav Shwartsman
2bad0d0d12 fixed link error with debugger enabled, small speed optimization 2015-02-23 19:55:55 +00:00
Stanislav Shwartsman
0917d12e8b memory type report for physical accesses and RMW acccesses. todo: consider also pat 2015-02-22 21:26:26 +00:00
Stanislav Shwartsman
7a3e340e6d implement memory type calculation by mtrr. todo: memory type from page tables 2015-02-20 21:50:59 +00:00
Stanislav Shwartsman
e16c6eb30c preparations and interface definition for memory type support 2015-02-19 20:23:08 +00:00
Stanislav Shwartsman
ee3841ef07 fixed more compilation problems and code cleanup 2015-01-26 20:01:25 +00:00
Stanislav Shwartsman
9a70727814 fixed fault priority for memory accesses requiring alignment 2015-01-26 19:09:58 +00:00
Stanislav Shwartsman
74da7a7092 fixed compilation err 2015-01-26 15:34:52 +00:00
Stanislav Shwartsman
5e6955c5e7 Major rewrite of memory access methods to avoid massive code duplication and enable inlining of memory access methods 2015-01-25 20:55:10 +00:00
Stanislav Shwartsman
271f06026d fixed compilation err with SVM without VMX 2015-01-16 06:15:47 +00:00
Stanislav Shwartsman
3b237df41d Added far branch origin to bx_instr_far_branch instrumentation callback by user request 
Updated instrumentation examples
Fixed code duplication
 2015-01-11 20:45:39 +00:00
Stanislav Shwartsman
987e2ad223 Added definitions from recently published Intel Architecture 
Instruction Set Extensions Programming Reference rev22.
Implemented CLWB instruction
 2014-11-01 13:12:24 +00:00
Stanislav Shwartsman
cb18f1e0a1 more use of the clearflagsOSZAPC 2014-10-22 18:24:33 +00:00
Stanislav Shwartsman
1c027b17d7 some lazy flags handling optimizations 2014-10-22 17:49:12 +00:00
Stanislav Shwartsman
25ad64f75a rename one more mem access handler 2014-10-21 19:11:21 +00:00
Stanislav Shwartsman
ea91354b3b code reorg : take laddr calculation out of 64-bit memory handlers. this creates generic linear address memory handlers which now could be used elsewhere 2014-10-20 21:08:29 +00:00
Stanislav Shwartsman
841117c721 added more perfmon MSR defines into cpu.h 2014-10-15 15:21:38 +00:00
Stanislav Shwartsman
f8267ec3a7 rework in CPUID code (fixed code duplication). Re-enable perfmon reporting in CPUID because Win8/Win10 installation doesn't want to start without perfmon reported. TODO: implement basic perfmon support (at least only fixed counters) because win7-64 doesn't install with perfmon reported but not implemented 2014-10-15 08:04:38 +00:00
Stanislav Shwartsman
8d1e3b2ac1 Added statistics collection infrastructure in Bochs and 
implemented important CPU statistics which were used for Bochs CPU model performance analysis.
old statistics code from paging.cc and cpu.cc is replaced with new infrastructure.

In order to enale statitics collection in Bochs CPU:

- Enable statistics @ compilation time in cpu/cpustats.h
- Dump statistics periodically by adding -dumpstats N into Bochs command line
 2014-10-14 15:59:10 +00:00
Stanislav Shwartsman
1ef6c3139c removed duplication in XCHG instruction handlers 2014-10-12 19:31:14 +00:00
Stanislav Shwartsman
24cb334304 fixed large code duplication in write_new_stack methods 2014-10-12 18:59:10 +00:00
Stanislav Shwartsman
e2e6f5a62b Update CPUID defines after recently published 
Intel Architecture Instruction Set Extensions Programming Reference rev-021

Enable AVX-512 with all implemented extensions in generic CPUID when simd=AVX512 is supplied
implemented AVX512_IFMA532 instructions
implemented AVX512_VBMI instructions

still missing: VPMULTISHIFTQB - VBMI instruction (coming soon)
 2014-09-26 12:14:53 +00:00
Stanislav Shwartsman
5eb781e45f cleanup after cpu features interface rework 2014-08-31 19:22:41 +00:00
Stanislav Shwartsman
b6147d9de8 fixed debugger enabled code 2014-08-31 18:48:04 +00:00
Stanislav Shwartsman
9f57e70d5f Rewritten handling of supported CPUID features to be able to handle large amount of CPU extensions 
Now enable support for up to 128 CPU extensions and could easily extend it more
Also reduce memory footprint for bx_ia_opcodes.h arrays
 2014-08-31 18:39:18 +00:00
Stanislav Shwartsman
fb526a0670 implemented (not yet 100% correct) VREDUCE* AVX512 opcode 2014-08-08 19:12:18 +00:00