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b013b389ea
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1149 Commits

Author SHA1 Message Date
Shwartsman
b013b389ea fixed code duplication, extract some code to functions 
make special phy memory read methods which help to write cleaner code
 2023-11-26 18:25:54 +02:00
Shwartsman
ab629f16f6 remove redundant #if BX_SUPPORT_X86_64 around UINTR 
it is checked already in config.h
 2023-11-26 17:41:26 +02:00
Stanislav Shwartsman
280303d76c
initial code for UINTR implementation (#138) 
First step into implementing UINTR - User Level Interrupts ISA extension
To be continued

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Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-11-25 16:43:47 +02:00
Stanislav Shwartsman
c1c391a9c6 fix common code duplication by introducing new method get_Virtual_TSC() 
it computes TSC as needed for RDTSC(P) and RDMSR TSC taking into account VMX and SVM adjustments
replaces previous get_TSC_VMXAdjust(Bit64u0
 2023-11-25 15:00:39 +02:00
Shwartsman
4d08659621 Implement 'Tertiary VMEXEC Controls' for VMX 
Currently none of the controls were not enabled, all clear but infra is here
 2023-11-23 19:38:59 +02:00
Shwartsman
f4f41cffc4 fix code duplication and optimize code 2023-11-21 20:26:48 +02:00
Stanislav Shwartsman
f90fdbc353 add methods to query local apic state 2023-11-21 15:43:38 +02:00
Stanislav Shwartsman
c1c102ab04 coding style, cleanups and optimizations 2023-11-19 20:31:05 +02:00
Stanislav Shwartsman
a3fe8c2c8d introduce get_efer_allow_mask function to avoid placing that code directly in init.cc 2023-11-17 23:40:28 +02:00
Stanislav Shwartsman
9bda4eba28 introduce GET64_FROM_HI32_LO32 to form 64-bit integer from 2 32-bit 2023-11-17 23:31:38 +02:00
Stanislav Shwartsman
1ad2ee6d4c use isReadOK instead of magic arithmetic for system_read_* methods 
introduce system_write_qword as well
 2023-11-17 23:14:38 +02:00
Stanislav Shwartsman
60cc8020e8 Fixed VMCS_GUEST_PENDING_DBG_EXCEPTIONS saved on VMEXIT (should be cleared after most of VMEXITs) 2023-11-13 20:02:03 +02:00
Stanislav Shwartsman
8594972389 final resolution for issue #2 : address VEXPAND* and VPSHUFBITQMB instructions 2023-11-09 19:15:32 +02:00
Stanislav Shwartsman
b78e93c9e3 optimize handling of allowed_to_run_FPU_MMX instructios common block 
now checked at decode and not at every instruction
simpler code and also 1% faster winXP boot time as bonus
other x87 and mmx heavy guests may benefit even more
 2023-11-08 06:48:53 +02:00
Stanislav Shwartsman
7469bcb69a
measure host stack depth during simulation to avoid excessive chainin… (#119) 
…g depth

never allow beyong 64K stack
 2023-11-05 07:08:36 +02:00
Stanislav Shwartsman
18deee022f
make CPU to use C++ template for implementation of CPU methods (#115) 
this allow to remove a lot of code from CPU common methods
 2023-10-30 06:57:16 +02:00
Shwartsman
02c4f85a89 implemented proper masked load for VPMOVSX/ZX instructions + bugfix 2023-10-20 20:13:29 +03:00
Stanislav Shwartsman
ffa64461ab
implementation of AVX-NE-CONVERT ISA (#89) 
Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-10-14 14:55:12 +03:00
Stanislav Shwartsman
4a309478f9
SHA512 instructions implemented (#88) 
Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-10-10 21:33:16 +03:00
Stanislav Shwartsman
3234e9b88e
implemented AVX VNNI INT16 ISA extension (#87) 
Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-10-10 20:22:07 +03:00
Stanislav Shwartsman
44eea71f37
implemented SM3 instructions (#84) 
add rol/ror methods to scalar_arith.h and use in more places

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Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-10-07 21:34:04 +03:00
Stanislav Shwartsman
1dcae848d7 change nullptr to NULL to help some old hosts not supporting C++ standard 2023-08-20 19:40:08 +03:00
Stanislav Shwartsman
0e4524f38f Implemented CMPccXADD instructions 2022-10-08 20:04:22 +03:00
Stanislav Shwartsman
4aed72e0ef fix issue with AVX IFMA when EVEX is not compiled in 2022-10-02 23:07:05 +03:00
Stanislav Shwartsman
a56144833a add support for AVX encoded VNNI INT8 extensions 2022-10-02 23:00:46 +03:00
Stanislav Shwartsman
1e4f1624c8 remove trailing whitespace from source files 2022-08-23 21:46:04 +03:00
Satoshi Tanda
30ef7f4842
Fix dbg_xlate_linear2phy for NPT (#30) 2022-08-22 07:20:47 +03:00
Stanislav Shwartsman
c9d8413422 allow TLB caching of SPP paging writes 
it is possible that SPP-protected subpage block is allowing write but all others are not.
the TLB entry cannot be cached as writeOK based on SPP subblock check
 2022-08-14 21:09:18 +03:00
Stanislav Shwartsman
4d227d15fb remove instrument.h from bochs.h so it won't be included everywhere 
include it only where required
move PHY_ADDRESS reserved bits consts to cpu.h
 2022-07-30 22:35:43 +03:00
Stanislav Shwartsman
3f65841714
use boolean constants true/false instead of 0/1 (#26) 
* use boolean constants true/false instead of 0/1

* fix code comment

Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2022-07-30 18:38:22 +03:00
Stanislav Shwartsman
f44f4ae753
MBE (Mode Based Execution Control) emulation (#22) 
* MBE (Mode Based Execution Control) emulation
 2022-07-30 15:26:47 +03:00
Stanislav Shwartsman
fb09790846 dos2unix to all files 2022-07-30 14:31:16 +03:00
Stanislav Shwartsman
0cba8b66c9 more robust handling of SVM VMCB host ptr 2021-07-23 09:30:17 +00:00
Stanislav Shwartsman
c87ce2d11a fixed some MSVC wannings in CPU code 2021-02-08 13:06:44 +00:00
Stanislav Shwartsman
1765a06d01 move debug.h from bochs.h and include it only where required 2021-01-31 15:22:58 +00:00
Stanislav Shwartsman
c878933057 remove pc_system.h from bochs.h and include it only where required 
next step: same for gui.h
 2021-01-30 18:29:28 +00:00
Stanislav Shwartsman
1bf18b8aae ! CPUID: Added TigerLake CPU definition (features CET and CLWB support) 
- CPU code refactor, remove uses of bx_bool datatype and use C++ classic bool instead.
  This enable better compiler optimizations and reduce binary size
 2021-01-30 08:35:35 +00:00
Stanislav Shwartsman
bea432dacb fixed compilation with no debugger configured in 2021-01-02 14:04:35 +00:00
Stanislav Shwartsman
41ea50ba22 complete transition to new disasm, remove old disasm from source code 2021-01-02 13:43:10 +00:00
Stanislav Shwartsman
c6050a99d1 implemented AVX encoded VNNI instructions published in recent SDM - not tested yet 2020-10-03 09:23:28 +00:00
Stanislav Shwartsman
4023b640d6 Protection Keys: Implemented Supervisor-Mode Protection Keys (PKS) 2020-05-29 12:35:30 +00:00
Stanislav Shwartsman
b891789c3d implemented (experimental) TSC Adjust MSR 2020-05-21 19:58:16 +00:00
Stanislav Shwartsman
b69f2b052a extract calculation of MSR_IA32_XSS supported bits to a function 2020-01-03 19:33:16 +00:00
Stanislav Shwartsman
016aa349e5 handle supervisor-shadow-stack protection feature in the EPT 2019-12-29 20:40:18 +00:00
Stanislav Shwartsman
9458e25486 reverting commit 13737 and doing correct fix 2019-12-28 13:11:13 +00:00
Stanislav Shwartsman
5d7c6d46b0 fixed compilation after prev commit 2019-12-28 13:02:02 +00:00
Stanislav Shwartsman
1a0237e9af make order in AVX512 broadcast handlers, extract them into separate file 2019-12-21 20:07:03 +00:00
Stanislav Shwartsman
dd1ab303df rename function to correct English 2019-12-21 15:54:52 +00:00
Stanislav Shwartsman
723554d535 AVX512: Allow masked fault suppression for many AVX512 instructions - not all cases reviewed yet, more to come 2019-12-21 15:47:29 +00:00
Stanislav Shwartsman
f90e5f4f44 Add initial implementation of the CET (Control Flow Enforcement Technology) emulation according to SDM071 
Only missing items (to be added soon):
  - Supervisor Shadow Stack EPT Control is not implemented yet
  - SMM placing for SSP
Currently have to be added manually to some CPUID model, for example to ICL-U
To enable configure with --enable-cet
 2019-12-20 07:42:07 +00:00