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correctly decode VPEXTRB/W/D/Q - these opcodes allowed to be with VEX.L=0 only

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fixed disasm module compilation with no AVX enabled
remove duplicate opcode handlers
This commit is contained in:
Stanislav Shwartsman 2017-12-13 19:51:25 +00:00
parent 2f3c9d3c8c
commit 8a311515dd
9 changed files with 64 additions and 94 deletions
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2
bochs/cpu/cpu.h
View File

@ -2575,8 +2575,6 @@ public: // for now...
BX_SMF BX_INSF_TYPE PEXTRW_EwdVdqIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PEXTRD_EdVdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PEXTRD_EdVdqIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE EXTRACTPS_EdVpsIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE EXTRACTPS_EdVpsIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PINSRB_VdqHdqEbIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PINSRB_VdqHdqEbIbM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE INSERTPS_VpsHpsWssIb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);

24
bochs/cpu/decoder/disasm.cc
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@ -34,9 +34,7 @@ extern int fetchDecode32(const Bit8u *fetchPtr, bx_bool is_32, bxInstruction_c *
#if BX_SUPPORT_X86_64
extern int fetchDecode64(const Bit8u *fetchPtr, bxInstruction_c *i, unsigned remainingInPage);
#endif
#if BX_SUPPORT_EVEX
unsigned evex_displ8_compression(const bxInstruction_c *i, unsigned ia_opcode, unsigned src, unsigned type, unsigned vex_w);
#endif
// table of all Bochs opcodes
extern struct bxIAOpcodeTable BxOpcodesTable[];
@ -92,9 +90,11 @@ static const char *intel_segment_name[8] = {
"es", "cs", "ss", "ds", "fs", "gs", "??", "??"
};
#if BX_SUPPORT_AVX
static const char *intel_vector_reg_name[4] = {
"xmm", "ymm", "???", "zmm"
};
#endif
#if BX_SUPPORT_EVEX
static const char *rounding_mode[4] = {
@ -595,14 +595,22 @@ char* disasm(char *disbufptr, const bxInstruction_c *i, bx_address cs_base, bx_a
// special case: MOVLPS opcode in reg form is MOVHLPS
// MOVHPS opcode in reg form is MOVLHPS
if ((i->getIaOpcode() == BX_IA_MOVLPS_VpsMq ||
i->getIaOpcode() == BX_IA_V128_VMOVLPS_VpsHpsMq ||
i->getIaOpcode() == BX_IA_V512_VMOVLPS_VpsHpsMq) && i->modC0())
if (i->modC0() && (i->getIaOpcode() == BX_IA_MOVLPS_VpsMq
#if BX_SUPPORT_AVX
|| i->getIaOpcode() == BX_IA_V128_VMOVLPS_VpsHpsMq
|| i->getIaOpcode() == BX_IA_V512_VMOVLPS_VpsHpsMq
#endif
)) {
disbufptr = dis_sprintf(disbufptr, "%smovhlps ", (i->getVL() == BX_VL128) ? "v" : "");
else if ((i->getIaOpcode() == BX_IA_MOVHPS_VpsMq ||
i->getIaOpcode() == BX_IA_V128_VMOVHPS_VpsHpsMq ||
i->getIaOpcode() == BX_IA_V512_VMOVHPS_VpsHpsMq) && i->modC0())
}
else if (i->modC0() && (i->getIaOpcode() == BX_IA_MOVHPS_VpsMq
#if BX_SUPPORT_AVX
|| i->getIaOpcode() == BX_IA_V128_VMOVHPS_VpsHpsMq
|| i->getIaOpcode() == BX_IA_V512_VMOVHPS_VpsHpsMq
#endif
)) {
disbufptr = dis_sprintf(disbufptr, "%smovlhps ", (i->getVL() == BX_VL128) ? "v" : "");
}
else {
unsigned opname_len = strlen(opname);
for (n=0;n < opname_len; n++) {

30
bochs/cpu/decoder/fetchdecode32.cc
View File

@ -1493,7 +1493,6 @@ int decodeImmediate32(const Bit8u *iptr, unsigned &remain, bxInstruction_c *i, u
return 0;
}
#if BX_SUPPORT_EVEX
unsigned evex_displ8_compression(const bxInstruction_c *i, unsigned ia_opcode, unsigned src, unsigned type, unsigned vex_w)
{
if (src == BX_SRC_RM) {
@ -1510,22 +1509,22 @@ unsigned evex_displ8_compression(const bxInstruction_c *i, unsigned ia_opcode, u
}
// VMOVDDUP special case
if ((ia_opcode == BX_IA_V512_VMOVDDUP_VpdWpd ||
ia_opcode == BX_IA_V512_VMOVDDUP_VpdWpd_Kmask ||
ia_opcode == BX_IA_V256_VMOVDDUP_VpdWpd ||
ia_opcode == BX_IA_V128_VMOVDDUP_VpdWpd) && i->getVL() == BX_VL128) return 8;
#if BX_SUPPORT_EVEX
if ((ia_opcode == BX_IA_V512_VMOVDDUP_VpdWpd || ia_opcode == BX_IA_V512_VMOVDDUP_VpdWpd_Kmask) && (i->getVL() == BX_VL128))
return 8;
#endif
unsigned len = i->getVL();
if (len == BX_NO_VL) len = BX_VL128;
switch (type) {
case BX_VMM_FULL_VECTOR:
if (i->getEvexb()) { // broadcast
#if BX_SUPPORT_EVEX
if (i->getEvexb()) // broadcast
return (4 << vex_w);
}
else {
else
#endif
return (16 * len);
}
case BX_VMM_SCALAR_BYTE:
return 1;
@ -1543,19 +1542,23 @@ unsigned evex_displ8_compression(const bxInstruction_c *i, unsigned ia_opcode, u
return (4 << vex_w);
case BX_VMM_HALF_VECTOR:
if (i->getEvexb()) { // broadcast
#if BX_SUPPORT_EVEX
if (i->getEvexb()) // broadcast
return (4 << vex_w);
}
else {
else
#endif
return (8 * len);
}
case BX_VMM_QUARTER_VECTOR:
#if BX_SUPPORT_EVEX
BX_ASSERT(! i->getEvexb());
#endif
return (4 * len);
case BX_VMM_OCT_VECTOR:
#if BX_SUPPORT_EVEX
BX_ASSERT(! i->getEvexb());
#endif
return (2 * len);
case BX_VMM_VEC128:
@ -1567,7 +1570,6 @@ unsigned evex_displ8_compression(const bxInstruction_c *i, unsigned ia_opcode, u
return 1;
}
#endif
bx_bool assign_srcs(bxInstruction_c *i, unsigned ia_opcode, unsigned nnn, unsigned rm)
{

2
bochs/cpu/decoder/fetchdecode64.cc
View File

@ -925,7 +925,7 @@ static BxOpcodeDecodeDescriptor64 decode64_descriptor[] =
/* 0F 3A 13 */ { &decoder_ud64, NULL },
/* 0F 3A 14 */ { &decoder64_sse, BxOpcodeGroupSSE_0F3A14 },
/* 0F 3A 15 */ { &decoder64_sse, BxOpcodeGroupSSE_0F3A15 },
/* 0F 3A 16 */ { &decoder64_sse, BxOpcodeGroupSSE_0F3A16 },
/* 0F 3A 16 */ { &decoder64_sseq, BxOpcodeGroupSSE_0F3A16 },
/* 0F 3A 17 */ { &decoder64_sse, BxOpcodeGroupSSE_0F3A17 },
/* 0F 3A 18 */ { &decoder_ud64, NULL },
/* 0F 3A 19 */ { &decoder_ud64, NULL },

8
bochs/cpu/decoder/fetchdecode_evex.h
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@ -1900,13 +1900,13 @@ static const BxExtOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
/* 12 */ { 0, BX_IA_ERROR },
/* 13 k0 */ { 0, BX_IA_ERROR },
/* 13 */ { 0, BX_IA_ERROR },
/* 14 k0 */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VPEXTRB_EbdVdqIb },
/* 14 k0 */ { BxPrefixSSE66 | BxVexL0 | BxImmediate_Ib, BX_IA_V512_VPEXTRB_EbdVdqIb },
/* 14 */ { 0, BX_IA_ERROR }, // #UD
/* 15 k0 */ { BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VPEXTRW_EwdVdqIb },
/* 15 k0 */ { BxPrefixSSE66 | BxVexL0 | BxImmediate_Ib, BX_IA_V512_VPEXTRW_EwdVdqIb },
/* 15 */ { 0, BX_IA_ERROR }, // #UD
/* 16 k0 */ { BxPrefixSSE66 | BxAliasVexW64 | BxImmediate_Ib, BX_IA_V512_VPEXTRD_EdVdqIb },
/* 16 k0 */ { BxPrefixSSE66 | BxVexL0 | BxAliasVexW64 | BxImmediate_Ib, BX_IA_V512_VPEXTRD_EdVdqIb },
/* 16 */ { 0, BX_IA_ERROR }, // #UD
/* 17 k0 */ { BxPrefixSSE66 | BxVexW0 | BxImmediate_Ib, BX_IA_V512_VEXTRACTPS_EdVpsIb },
/* 17 k0 */ { BxPrefixSSE66 | BxVexL0 | BxVexW0 | BxImmediate_Ib, BX_IA_V512_VEXTRACTPS_EdVpsIb },
/* 17 */ { 0, BX_IA_ERROR }, // #UD
/* 18 k0 */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTF32x4_VpsHpsWpsIb },
/* 18 */ { BxAliasVexW | BxVexL1 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTF32x4_VpsHpsWpsIb_Kmask },

8
bochs/cpu/decoder/fetchdecode_opmap_0f3a.h
View File

@ -110,11 +110,17 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0F3A15[4] = {
};
// opcode 0F 3A 16
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0F3A16[4] = {
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0F3A16[] = {
/* -- */ { 0, BX_IA_ERROR },
/* 66 */ { BxImmediate_Ib, BX_IA_PEXTRD_EdVdqIb },
/* F3 */ { 0, BX_IA_ERROR },
/* F2 */ { 0, BX_IA_ERROR },
#if BX_SUPPORT_X86_64
/* -- */ { 0, BX_IA_ERROR },
/* 66 */ { BxImmediate_Ib, BX_IA_PEXTRQ_EqVdqIb },
/* F3 */ { 0, BX_IA_ERROR },
/* F2 */ { 0, BX_IA_ERROR },
#endif
};
// opcode 0F 3A 17

11
bochs/cpu/decoder/ia_opcodes.def
View File

@ -1245,7 +1245,10 @@ bx_define_opcode(BX_IA_PBLENDW_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PBLENDW
bx_define_opcode(BX_IA_PEXTRB_EbdVdqIb, &BX_CPU_C::PEXTRB_EbdVdqIbM, &BX_CPU_C::PEXTRB_EbdVdqIbR, BX_ISA_SSE4_1, OP_Ebd, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PEXTRW_EwdVdqIb, &BX_CPU_C::PEXTRW_EwdVdqIbM, &BX_CPU_C::PEXTRW_EwdVdqIbR, BX_ISA_SSE4_1, OP_Ewd, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PEXTRD_EdVdqIb, &BX_CPU_C::PEXTRD_EdVdqIbM, &BX_CPU_C::PEXTRD_EdVdqIbR, BX_ISA_SSE4_1, OP_Ed, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_EXTRACTPS_EdVpsIb, &BX_CPU_C::EXTRACTPS_EdVpsIbM, &BX_CPU_C::EXTRACTPS_EdVpsIbR, BX_ISA_SSE4_1, OP_Ed, OP_Vps, OP_Ib, OP_NONE, BX_PREPARE_SSE)
#if BX_SUPPORT_X86_64
bx_define_opcode(BX_IA_PEXTRQ_EqVdqIb, &BX_CPU_C::PEXTRQ_EqVdqIbM, &BX_CPU_C::PEXTRQ_EqVdqIbR, BX_ISA_SSE4_1, OP_Eq, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_SSE)
#endif
bx_define_opcode(BX_IA_EXTRACTPS_EdVpsIb, &BX_CPU_C::PEXTRD_EdVdqIbM, &BX_CPU_C::PEXTRD_EdVdqIbR, BX_ISA_SSE4_1, OP_Ed, OP_Vps, OP_Ib, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PINSRB_VdqEbIb, &BX_CPU_C::PINSRB_VdqHdqEbIbM, &BX_CPU_C::PINSRB_VdqHdqEbIbR, BX_ISA_SSE4_1, OP_Vdq, OP_Vdq, OP_Ew, OP_Ib, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_INSERTPS_VpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, BX_ISA_SSE4_1, OP_Vps, OP_Vps, OP_Wss, OP_Ib, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PINSRD_VdqEdIb, &BX_CPU_C::PINSRD_VdqHdqEdIbM, &BX_CPU_C::PINSRD_VdqHdqEdIbR, BX_ISA_SSE4_1, OP_Vdq, OP_Vdq, OP_Ed, OP_Ib, BX_PREPARE_SSE)
@ -1674,7 +1677,7 @@ bx_define_opcode(BX_IA_V128_VMOVHPD_MqVsd, &BX_CPU_C::MOVHPS_MqVps, &BX_CPU_C::B
bx_define_opcode(BX_IA_V128_VMOVLPD_VpdHpdMq, &BX_CPU_C::VMOVLPD_VpdHpdMq, &BX_CPU_C::BxError, BX_ISA_AVX, OP_Vpd, OP_Hpd, OP_Wsd, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVHPD_VpdHpdMq, &BX_CPU_C::VMOVHPD_VpdHpdMq, &BX_CPU_C::BxError, BX_ISA_AVX, OP_Vpd, OP_Hpd, OP_Wsd, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVDDUP_VpdWpd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMOVDDUP_VpdWpdR, BX_ISA_AVX, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMOVDDUP_VpdWpd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VMOVDDUP_VpdWpdR, BX_ISA_AVX, OP_Vpd, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VMOVDDUP_VpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVDDUP_VpdWpdR, BX_ISA_AVX, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMOVSLDUP_VpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VMOVSLDUP_VpsWpsR, BX_ISA_AVX, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_AVX)
@ -2032,7 +2035,7 @@ bx_define_opcode(BX_IA_V128_VPALIGNR_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_
bx_define_opcode(BX_IA_V256_VPALIGNR_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPALIGNR_VdqHdqWdqIbR, BX_ISA_AVX2, OP_Vdq, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VINSERTPS_VpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, BX_ISA_AVX, OP_Vps, OP_Hps, OP_Wss, OP_Ib, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VEXTRACTPS_EdVpsIb, &BX_CPU_C::EXTRACTPS_EdVpsIbM, &BX_CPU_C::EXTRACTPS_EdVpsIbR, BX_ISA_AVX, OP_Ed, OP_Vps, OP_Ib, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VEXTRACTPS_EdVpsIb, &BX_CPU_C::PEXTRD_EdVdqIbM, &BX_CPU_C::PEXTRD_EdVdqIbR, BX_ISA_AVX, OP_Ed, OP_Vps, OP_Ib, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPERM2F128_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERM2F128_VdqHdqWdqIbR, BX_ISA_AVX, OP_Vdq, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VINSERTF128_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF128_VdqHdqWdqIbR, BX_ISA_AVX, OP_Vdq, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VEXTRACTF128_WdqVdqIb, &BX_CPU_C::VEXTRACTF128_WdqVdqIbM, &BX_CPU_C::VEXTRACTF128_WdqVdqIbR, BX_ISA_AVX, OP_Wdq, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_AVX)
@ -2844,7 +2847,7 @@ bx_define_opcode(BX_IA_V512_VMOVQ_WqVq, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::MOV
bx_define_opcode(BX_IA_V512_VMOVQ_VqWq, &BX_CPU_C::MOVSD_VsdWsdM, &BX_CPU_C::MOVQ_VqWqR, BX_ISA_AVX512, OP_Vq, OP_mVpd64, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VINSERTPS_VpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVss, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTPS_EdVpsIb, &BX_CPU_C::EXTRACTPS_EdVpsIbM, &BX_CPU_C::EXTRACTPS_EdVpsIbR, BX_ISA_AVX512, OP_Ed, OP_Vps, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VEXTRACTPS_EdVpsIb, &BX_CPU_C::PEXTRD_EdVdqIbM, &BX_CPU_C::PEXTRD_EdVdqIbR, BX_ISA_AVX512, OP_Ed, OP_Vps, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VMOVLPS_VpsHpsMq, &BX_CPU_C::VMOVLPD_VpdHpdMq, &BX_CPU_C::VMOVHLPS_VpsHpsWps, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVHV, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VMOVHPS_VpsHpsMq, &BX_CPU_C::VMOVHPD_VpdHpdMq, &BX_CPU_C::VMOVLHPS_VpsHpsWps, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVHV, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)

2
bochs/cpu/decoder/instr.h
View File

@ -311,6 +311,8 @@ public:
BX_CPP_INLINE unsigned getVexW(void) const {
return modRMForm.Ib[2] & (1 << 4);
}
#else
BX_CPP_INLINE unsigned getVexW(void) const { return 0; }
#endif
#if BX_SUPPORT_EVEX

71
bochs/cpu/sse.cc
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003-2015 Stanislav Shwartsman
// Copyright (c) 2003-2017 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -304,19 +304,17 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRW_EwdVdqIbM(bxInstruction_c *
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRD_EdVdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
Bit32u result = op.xmm32u(i->Ib() & 3);
BX_WRITE_32BIT_REGZ(i->dst(), result);
BX_NEXT_INSTR(i);
}
#if BX_SUPPORT_X86_64
if (i->os64L()) /* 64 bit operand size mode */
{
Bit64u result = op.xmm64u(i->Ib() & 1);
BX_WRITE_64BIT_REG(i->dst(), result);
}
else
#endif
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRD_EdVdqIbM(bxInstruction_c *i)
{
Bit32u result = op.xmm32u(i->Ib() & 3);
BX_WRITE_32BIT_REGZ(i->dst(), result);
}
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
Bit32u result = op.xmm32u(i->Ib() & 3);
bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
write_virtual_dword(i->seg(), eaddr, result);
BX_NEXT_INSTR(i);
}
@ -325,69 +323,22 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRD_EdVdqIbR(bxInstruction_c *i
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRQ_EqVdqIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
Bit64u result = op.xmm64u(i->Ib() & 1);
BX_WRITE_64BIT_REG(i->dst(), result);
BX_NEXT_INSTR(i);
}
#endif
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRD_EdVdqIbM(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
#if BX_SUPPORT_X86_64
if (i->os64L()) /* 64 bit operand size mode */
{
Bit64u result = op.xmm64u(i->Ib() & 1);
write_linear_qword(i->seg(), get_laddr64(i->seg(), eaddr), result);
}
else
#endif
{
Bit32u result = op.xmm32u(i->Ib() & 3);
write_virtual_dword(i->seg(), eaddr, result);
}
BX_NEXT_INSTR(i);
}
#if BX_SUPPORT_X86_64
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PEXTRQ_EqVdqIbM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_RESOLVE_ADDR_64(i);
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
Bit64u result = op.xmm64u(i->Ib() & 1);
bx_address eaddr = BX_CPU_RESOLVE_ADDR_64(i);
write_linear_qword(i->seg(), get_laddr64(i->seg(), eaddr), result);
BX_NEXT_INSTR(i);
}
#endif
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::EXTRACTPS_EdVpsIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
Bit32u result = op.xmm32u(i->Ib() & 3);
BX_WRITE_32BIT_REGZ(i->dst(), result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::EXTRACTPS_EdVpsIbM(bxInstruction_c *i)
{
BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());
Bit32u result = op.xmm32u(i->Ib() & 3);
bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
write_virtual_dword(i->seg(), eaddr, result);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PINSRB_VdqHdqEbIbR(bxInstruction_c *i)
{
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->src1());