fix small issue on the way to Bochs decoder separation into stand-alone module
This commit is contained in:
Stanislav Shwartsman
parent
ca5882b310
commit
cc49b504b3
@ -4470,7 +4470,6 @@ public: // for now...
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#if BX_SUPPORT_EVEX
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BX_SMF unsigned evex_displ8_compression(bxInstruction_c *i, unsigned ia_opcode, unsigned type, unsigned vex_w);
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#endif
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BX_SMF Bit16u WalkOpcodeTables(const BxOpcodeInfo_t *op, Bit16u &attr, unsigned modrm, unsigned sse_prefix, unsigned osize, unsigned vex_vl, bx_bool vex_w);
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BX_SMF char* disasm(const Bit8u *opcode, bool is_32, bool is_64, char *disbufptr, bxInstruction_c *i, bx_address cs_base = 0, bx_address rip = 0);
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BX_SMF bxICacheEntry_c *serveICacheMiss(Bit32u eipBiased, bx_phy_address pAddr);
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@ -5735,90 +5734,4 @@ enum {
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};
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#endif
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// <TAG-DEFINES-DECODE-START>
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//
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// For decoding...
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//
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// If the BxImmediate mask is set, the lowest 4 bits of the attribute
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// specify which kinds of immediate data required by instruction.
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#define BxImmediate 0x000f // bits 3..0: any immediate
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#define BxImmediate_I1 0x0001 // imm8 = 1
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#define BxImmediate_Ib 0x0002 // 8 bit
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#define BxImmediate_Ib_SE 0x0003 // sign extend to operand size
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#define BxImmediate_Iw 0x0004 // 16 bit
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#define BxImmediate_Id 0x0005 // 32 bit
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#define BxImmediate_O 0x0006 // MOV_ALOd, mov_OdAL, mov_eAXOv, mov_OveAX
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#if BX_SUPPORT_X86_64
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#define BxImmediate_Iq 0x0007 // 64 bit override
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#endif
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#define BxImmediate_BrOff8 0x0008 // Relative branch offset byte
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#define BxImmediate_BrOff16 BxImmediate_Iw // Relative branch offset word, not encodable in 64-bit mode
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#define BxImmediate_BrOff32 BxImmediate_Id // Relative branch offset dword
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#define BxImmediate_Ib4 BxImmediate_Ib // Register encoded in Ib[7:4]
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#define BxImmediate_Ib5 BxImmediate_Ib
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// Lookup for opcode and attributes in another opcode tables
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// Totally 15 opcode groups supported
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#define BxGroupX 0x00f0 // bits 7..4: opcode groups definition
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#define BxPrefixSSE66 0x0010 // Group encoding: 0001, SSE_PREFIX_66 only
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#define BxPrefixSSEF3 0x0020 // Group encoding: 0010, SSE_PREFIX_F3 only
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#define BxPrefixSSEF2 0x0030 // Group encoding: 0011, SSE_PREFIX_F2 only
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#define BxPrefixSSE 0x0040 // Group encoding: 0100
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#define BxPrefixSSE2 0x0050 // Group encoding: 0101, do not allow SSE_PREFIX_F2 or SSE_PREFIX_F3
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#define BxPrefixSSE4 0x0060 // Group encoding: 0110
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#define BxPrefixSSEF2F3 0x0070 // Group encoding: 0111, ignore SSE_PREFIX_66
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#define BxGroupN 0x0080 // Group encoding: 1000
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#define BxSplitGroupN 0x0090 // Group encoding: 1001
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#define BxFPEscape 0x00A0 // Group encoding: 1010
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#define BxOSizeGrp 0x00B0 // Group encoding: 1011
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#define BxSplitMod11B 0x00C0 // Group encoding: 1100
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#define BxSplitVexVL 0x00D0 // Group encoding: 1101
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// The BxImmediate2 mask specifies kind of second immediate data
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// required by instruction.
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#define BxImmediate2 0x0300 // bits 8.9: any immediate
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#define BxImmediate_Ib2 0x0100
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#define BxImmediate_Iw2 0x0200
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#define BxImmediate_Id2 0x0300
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#define BxVexL0 0x0100 // bit 8 (aliased with imm2)
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#define BxVexL1 0x0200 // bit 9 (aliased with imm2)
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#define BxVexW0 0x0400 // bit 10
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#define BxVexW1 0x0800 // bit 11
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#define BxAlias 0x3000 // bits 12..13
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#define BxAliasSSE 0x1000 // Encoding 01: form final opcode using SSE prefix and current opcode
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#define BxAliasVexW 0x2000 // Encoding 10: form final opcode using VEX.W and current opcode
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#define BxAliasVexW64 0x3000 // Encoding 11: form final opcode using VEX.W and current opcode in 64-bit mode only
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#define BxLockable 0x4000 // bit 14
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#define BxGroup1 BxGroupN
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#define BxGroup1A BxGroupN
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#define BxGroup2 BxGroupN
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#define BxGroup3 BxGroupN
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#define BxGroup4 BxGroupN
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#define BxGroup5 BxGroupN
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#define BxGroup6 BxGroupN
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#define BxGroup7 BxFPEscape
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#define BxGroup8 BxGroupN
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#define BxGroup9 BxSplitGroupN
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#define BxGroup11 BxGroupN
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#define BxGroup12 BxGroupN
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#define BxGroup13 BxGroupN
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#define BxGroup14 BxGroupN
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#define BxGroup15 BxSplitGroupN
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#define BxGroup16 BxGroupN
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#define BxGroup17 BxGroupN
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#define BxGroup17A BxGroupN
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#define BxGroupFP BxSplitGroupN
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// <TAG-DEFINES-DECODE-END>
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#endif // #ifndef BX_CPU_H
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@ -170,6 +170,8 @@ bxIAOpcodeTable BxOpcodesTable[] = {
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};
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#undef bx_define_opcode
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extern Bit16u WalkOpcodeTables(const BxOpcodeInfo_t *OpcodeInfoPtr, Bit16u &attr, Bit32u fetchModeMask, unsigned modrm, unsigned sse_prefix, unsigned osize, unsigned vex_vl, bx_bool vex_w);
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/* ************************** */
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/* 512 entries for 16bit mode */
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/* 512 entries for 32bit mode */
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@ -1688,7 +1690,7 @@ modrm_done:
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}
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#endif
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ia_opcode = WalkOpcodeTables(OpcodeInfoPtr, attr, b2, sse_prefix, os_32, i->getVL(), vex_w);
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ia_opcode = WalkOpcodeTables(OpcodeInfoPtr, attr, fetchModeMask, b2, sse_prefix, os_32, i->getVL(), vex_w);
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}
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else {
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// Opcode does not require a MODRM byte.
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@ -2091,7 +2093,7 @@ unsigned BX_CPU_C::evex_displ8_compression(bxInstruction_c *i, unsigned ia_opcod
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}
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#endif
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Bit16u BX_CPU_C::WalkOpcodeTables(const BxOpcodeInfo_t *OpcodeInfoPtr, Bit16u &attr, unsigned modrm, unsigned sse_prefix, unsigned osize, unsigned vex_vl, bx_bool vex_w)
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Bit16u WalkOpcodeTables(const BxOpcodeInfo_t *OpcodeInfoPtr, Bit16u &attr, Bit32u fetchModeMask, unsigned modrm, unsigned sse_prefix, unsigned osize, unsigned vex_vl, bx_bool vex_w)
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{
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// Parse mod-nnn-rm and related bytes
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unsigned mod_mem = (modrm & 0xc0) != 0xc0;
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@ -2191,7 +2193,7 @@ Bit16u BX_CPU_C::WalkOpcodeTables(const BxOpcodeInfo_t *OpcodeInfoPtr, Bit16u &a
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#if BX_SUPPORT_AVX
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else {
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// VexW64 is ignored in 32-bit mode
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if (has_alias == BxAliasVexW || long64_mode()) {
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if (has_alias == BxAliasVexW || (fetchModeMask & BX_FETCH_MODE_IS64_MASK) != 0) {
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alias = vex_w;
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}
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}
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@ -24,6 +24,88 @@
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#ifndef BX_COMMON_FETCHDECODE_TABLES_H
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#define BX_COMMON_FETCHDECODE_TABLES_H
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//
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// Matadata for decoder...
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//
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// If the BxImmediate mask is set, the lowest 4 bits of the attribute
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// specify which kinds of immediate data required by instruction.
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#define BxImmediate 0x000f // bits 3..0: any immediate
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#define BxImmediate_I1 0x0001 // imm8 = 1
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#define BxImmediate_Ib 0x0002 // 8 bit
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#define BxImmediate_Ib_SE 0x0003 // sign extend to operand size
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#define BxImmediate_Iw 0x0004 // 16 bit
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#define BxImmediate_Id 0x0005 // 32 bit
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#define BxImmediate_O 0x0006 // MOV_ALOd, mov_OdAL, mov_eAXOv, mov_OveAX
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#if BX_SUPPORT_X86_64
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#define BxImmediate_Iq 0x0007 // 64 bit override
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#endif
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#define BxImmediate_BrOff8 0x0008 // Relative branch offset byte
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#define BxImmediate_BrOff16 BxImmediate_Iw // Relative branch offset word, not encodable in 64-bit mode
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#define BxImmediate_BrOff32 BxImmediate_Id // Relative branch offset dword
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#define BxImmediate_Ib4 BxImmediate_Ib // Register encoded in Ib[7:4]
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#define BxImmediate_Ib5 BxImmediate_Ib
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// Lookup for opcode and attributes in another opcode tables
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// Totally 15 opcode groups supported
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#define BxGroupX 0x00f0 // bits 7..4: opcode groups definition
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#define BxPrefixSSE66 0x0010 // Group encoding: 0001, SSE_PREFIX_66 only
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#define BxPrefixSSEF3 0x0020 // Group encoding: 0010, SSE_PREFIX_F3 only
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#define BxPrefixSSEF2 0x0030 // Group encoding: 0011, SSE_PREFIX_F2 only
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#define BxPrefixSSE 0x0040 // Group encoding: 0100
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#define BxPrefixSSE2 0x0050 // Group encoding: 0101, do not allow SSE_PREFIX_F2 or SSE_PREFIX_F3
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#define BxPrefixSSE4 0x0060 // Group encoding: 0110
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#define BxPrefixSSEF2F3 0x0070 // Group encoding: 0111, ignore SSE_PREFIX_66
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#define BxGroupN 0x0080 // Group encoding: 1000
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#define BxSplitGroupN 0x0090 // Group encoding: 1001
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#define BxFPEscape 0x00A0 // Group encoding: 1010
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#define BxOSizeGrp 0x00B0 // Group encoding: 1011
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#define BxSplitMod11B 0x00C0 // Group encoding: 1100
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#define BxSplitVexVL 0x00D0 // Group encoding: 1101
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// The BxImmediate2 mask specifies kind of second immediate data
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// required by instruction.
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#define BxImmediate2 0x0300 // bits 8.9: any immediate
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#define BxImmediate_Ib2 0x0100
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#define BxImmediate_Iw2 0x0200
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#define BxImmediate_Id2 0x0300
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#define BxVexL0 0x0100 // bit 8 (aliased with imm2)
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#define BxVexL1 0x0200 // bit 9 (aliased with imm2)
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#define BxVexW0 0x0400 // bit 10
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#define BxVexW1 0x0800 // bit 11
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#define BxAlias 0x3000 // bits 12..13
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#define BxAliasSSE 0x1000 // Encoding 01: form final opcode using SSE prefix and current opcode
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#define BxAliasVexW 0x2000 // Encoding 10: form final opcode using VEX.W and current opcode
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#define BxAliasVexW64 0x3000 // Encoding 11: form final opcode using VEX.W and current opcode in 64-bit mode only
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#define BxLockable 0x4000 // bit 14
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#define BxGroup1 BxGroupN
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#define BxGroup1A BxGroupN
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#define BxGroup2 BxGroupN
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#define BxGroup3 BxGroupN
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#define BxGroup4 BxGroupN
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#define BxGroup5 BxGroupN
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#define BxGroup6 BxGroupN
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#define BxGroup7 BxFPEscape
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#define BxGroup8 BxGroupN
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#define BxGroup9 BxSplitGroupN
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#define BxGroup11 BxGroupN
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#define BxGroup12 BxGroupN
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#define BxGroup13 BxGroupN
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#define BxGroup14 BxGroupN
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#define BxGroup15 BxSplitGroupN
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#define BxGroup16 BxGroupN
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#define BxGroup17 BxGroupN
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#define BxGroup17A BxGroupN
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#define BxGroupFP BxSplitGroupN
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enum {
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BX_ILLEGAL_OPCODE,
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BX_ILLEGAL_LOCK_PREFIX,
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@ -133,6 +133,8 @@ static unsigned sreg_mod1or2_base32[16] = {
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// table of all Bochs opcodes
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extern struct bxIAOpcodeTable BxOpcodesTable[];
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extern Bit16u WalkOpcodeTables(const BxOpcodeInfo_t *OpcodeInfoPtr, Bit16u &attr, Bit32u fetchModeMask, unsigned modrm, unsigned sse_prefix, unsigned osize, unsigned vex_vl, bx_bool vex_w);
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// 512 entries for 16bit operand size
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// 512 entries for 32bit operand size
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// 512 entries for 64bit operand size
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@ -2125,7 +2127,7 @@ modrm_done:
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}
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#endif
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ia_opcode = WalkOpcodeTables(OpcodeInfoPtr, attr, b2, sse_prefix, offset >> 9, i->getVL(), vex_w);
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ia_opcode = WalkOpcodeTables(OpcodeInfoPtr, attr, fetchModeMask, b2, sse_prefix, offset >> 9, i->getVL(), vex_w);
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}
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else {
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// Opcode does not require a MODRM byte.
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