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implemented Intel architecture extensions published in recently published SDM 058:

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! Implemented UMIP: User Mode Instruction Prevention (don't allow execution of SLDT/SIDT/SGDT/STR/SMSW with CPL>0)
! Implemented RDPID instruction

Bugfixes in RDPKRU/WRPKRU instructions implementation (Protection Keys feature)
This commit is contained in:
Stanislav Shwartsman 2016-04-15 11:35:32 +00:00
parent 45232b1860
commit adc143684b
12 changed files with 130 additions and 13 deletions
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3
bochs/bx_debug/dbg_main.cc
View File

@ -1024,7 +1024,7 @@ void bx_dbg_info_control_regs_command(void)
dbg_printf(" PWT=page-level write-through=%d\n", (cr3>>3) & 1);
#if BX_CPU_LEVEL >= 5
Bit32u cr4 = SIM->get_param_num("CR4", dbg_cpu_list)->get();
dbg_printf("CR4=0x%08x: %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s\n", cr4,
dbg_printf("CR4=0x%08x: %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s\n", cr4,
(cr4 & (1<<22)) ? "PKE" : "pke",
(cr4 & (1<<21)) ? "SMAP" : "smap",
(cr4 & (1<<20)) ? "SMEP" : "smep",
@ -1034,6 +1034,7 @@ void bx_dbg_info_control_regs_command(void)
(cr4 & (1<<14)) ? "SMX" : "smx",
(cr4 & (1<<13)) ? "VMX" : "vmx",
(cr4 & (1<<10)) ? "OSXMMEXCPT" : "osxmmexcpt",
(cr4 & (1<<11)) ? "UMIP" : "umip",
(cr4 & (1<<9)) ? "OSFXSR" : "osfxsr",
(cr4 & (1<<8)) ? "PCE" : "pce",
(cr4 & (1<<7)) ? "PGE" : "pge",

2
bochs/cpu/cpu.h
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@ -4398,6 +4398,8 @@ public: // for now...
BX_SMF BX_INSF_TYPE WRPKRU(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#endif
BX_SMF BX_INSF_TYPE RDPID_Ed(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE UndefinedOpcode(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE BxError(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#if BX_SUPPORT_HANDLERS_CHAINING_SPEEDUPS

27
bochs/cpu/cpuid.h
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@ -114,6 +114,8 @@ enum {
BX_ISA_FCS_FDS_DEPRECATION, /* FCS/FDS Deprecation */
BX_ISA_FDP_DEPRECATION, /* FDP Deprecation - FDP update on unmasked x87 exception only */
BX_ISA_PKU, /* User-Mode Protection Keys */
BX_ISA_UMIP, /* User-Mode Instructions Prevention */
BX_ISA_RDPID, /* RDPID Support */
BX_ISA_EXTENSION_LAST
};
@ -387,7 +389,7 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
// [0:0] FS/GS BASE access instructions
// [1:1] Support for IA32_TSC_ADJUST MSR
// [2:2] reserved
// [2:2] SGX: Intel Software Guard Extensions
// [3:3] BMI1: Advanced Bit Manipulation Extensions
// [4:4] HLE: Hardware Lock Elision
// [5:5] AVX2
@ -420,7 +422,7 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
#define BX_CPUID_EXT3_FSGSBASE (1 << 0)
#define BX_CPUID_EXT3_TSC_ADJUST (1 << 1)
#define BX_CPUID_EXT3_RESERVED2 (1 << 2)
#define BX_CPUID_EXT3_SGX (1 << 2)
#define BX_CPUID_EXT3_BMI1 (1 << 3)
#define BX_CPUID_EXT3_HLE (1 << 4)
#define BX_CPUID_EXT3_AVX2 (1 << 5)
@ -456,16 +458,31 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
// [0:0] PREFETCHWT1 instruction support
// [1:1] AVX512 VBMI instructions support
// [2:2] reserved
// [2:2] UMIP: Supports user-mode instruction prevention
// [3:3] PKU: Protection keys for user-mode pages.
// [4:4] OSPKE: OS has set CR4.PKE to enable protection keys
// [31:5] reserved
// [21:5] reserved
// [22:22] RDPID: Read Processor ID support
// [29:23] reserved
// [30:30] SGX_LC: SGX Launch Configuration
// [31:31] reserved
#define BX_CPUID_EXT4_PREFETCHWT1 (1 << 0)
#define BX_CPUID_EXT4_AVX512VBMI (1 << 1)
#define BX_CPUID_EXT4_RESERVED2 (1 << 2)
#define BX_CPUID_EXT4_UMIP (1 << 2)
#define BX_CPUID_EXT4_PKU (1 << 3)
#define BX_CPUID_EXT4_OSPKE (1 << 4)
// ...
#define BX_CPUID_EXT4_RDPID (1 << 22)
#define BX_CPUID_EXT4_RESERVED23 (1 << 23)
#define BX_CPUID_EXT4_RESERVED24 (1 << 24)
#define BX_CPUID_EXT4_RESERVED25 (1 << 25)
#define BX_CPUID_EXT4_RESERVED26 (1 << 26)
#define BX_CPUID_EXT4_RESERVED27 (1 << 27)
#define BX_CPUID_EXT4_RESERVED28 (1 << 28)
#define BX_CPUID_EXT4_RESERVED29 (1 << 29)
#define BX_CPUID_EXT4_SGX_LAUNCH_CONFIG (1 << 30)
#define BX_CPUID_EXT4_RESERVED31 (1 << 31)
// CPUID defines - STD2 features CPUID[0x80000001].EDX
// -----------------------------

17
bochs/cpu/crregs.cc
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@ -899,6 +899,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LMSW_Ew(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SMSW_EwR(bxInstruction_c *i)
{
if (CPL!=0 && BX_CPU_THIS_PTR cr4.get_UMIP()) {
BX_ERROR(("SMSW: CPL != 0 causes #GP when CR4.UMIP set"));
exception(BX_GP_EXCEPTION, 0);
}
Bit32u msw = (Bit32u) read_CR0(); // handle CR0 shadow in VMX
if (i->os32L()) {
@ -913,6 +918,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SMSW_EwR(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SMSW_EwM(bxInstruction_c *i)
{
if (CPL!=0 && BX_CPU_THIS_PTR cr4.get_UMIP()) {
BX_ERROR(("SMSW: CPL != 0 causes #GP when CR4.UMIP set"));
exception(BX_GP_EXCEPTION, 0);
}
Bit16u msw = read_CR0() & 0xffff; // handle CR0 shadow in VMX
bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);
write_virtual_word(i->seg(), eaddr, msw);
@ -1129,6 +1139,7 @@ Bit32u BX_CPU_C::get_cr4_allow_mask(void)
// CR4 bits definitions:
// [31-22] Reserved, Must be Zero
// [22] PKE: Protection Keys Enable R/W
// [21] SMAP: Supervisor Mode Access Prevention R/W
// [20] SMEP: Supervisor Mode Execution Protection R/W
// [19] Reserved, Must be Zero
@ -1138,7 +1149,8 @@ Bit32u BX_CPU_C::get_cr4_allow_mask(void)
// [15] Reserved, Must be Zero
// [14] SMXE: SMX Extensions R/W
// [13] VMXE: VMX Extensions R/W
// [12-11] Reserved, Must be Zero
// [12] Reserved, Must be Zero
// [11] UMIP: User Mode Instruction Prevention R/W
// [10] OSXMMEXCPT: Operating System Unmasked Exception Support R/W
// [9] OSFXSR: Operating System FXSAVE/FXRSTOR Support R/W
// [8] PCE: Performance-Monitoring Counter Enable R/W
@ -1214,6 +1226,9 @@ Bit32u BX_CPU_C::get_cr4_allow_mask(void)
if (is_cpu_extension_supported(BX_ISA_PKU))
allowMask |= BX_CR4_PKE_MASK;
if (is_cpu_extension_supported(BX_ISA_UMIP))
allowMask |= BX_CR4_UMIP_MASK;
#endif
return allowMask;

2
bochs/cpu/crregs.h
View File

@ -99,6 +99,7 @@ struct bx_cr0_t {
#define BX_CR4_PCE_MASK (1 << 8)
#define BX_CR4_OSFXSR_MASK (1 << 9)
#define BX_CR4_OSXMMEXCPT_MASK (1 << 10)
#define BX_CR4_UMIP_MASK (1 << 11)
#define BX_CR4_VMXE_MASK (1 << 13)
#define BX_CR4_SMXE_MASK (1 << 14)
#define BX_CR4_FSGSBASE_MASK (1 << 16)
@ -122,6 +123,7 @@ struct bx_cr4_t {
IMPLEMENT_CRREG_ACCESSORS(PCE, 8);
IMPLEMENT_CRREG_ACCESSORS(OSFXSR, 9);
IMPLEMENT_CRREG_ACCESSORS(OSXMMEXCPT, 10);
IMPLEMENT_CRREG_ACCESSORS(UMIP, 11);
#if BX_SUPPORT_VMX
IMPLEMENT_CRREG_ACCESSORS(VMXE, 13);
#endif

18
bochs/cpu/fetchdecode.h
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@ -867,6 +867,18 @@ static const BxOpcodeInfo_t BxOpcodeInfo64G8EqIb[8] = {
/* Group 9 */
/* ******* */
static const BxOpcodeInfo_t BxOpcodeGroupSSE_RDPID[3] = {
/* 66 */ { 0, BX_IA_ERROR },
/* F3 */ { 0, BX_IA_RDPID_Ed },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeGroupSSE_RDPID64[3] = {
/* 66 */ { 0, BX_IA_ERROR },
/* F3 */ { 0, BX_IA_RDPID_Eq },
/* F2 */ { 0, BX_IA_ERROR }
};
static const BxOpcodeInfo_t BxOpcodeInfoG9w[8*2] = {
/* /r form */
/* 0 */ { 0, BX_IA_ERROR },
@ -876,7 +888,7 @@ static const BxOpcodeInfo_t BxOpcodeInfoG9w[8*2] = {
/* 4 */ { 0, BX_IA_ERROR },
/* 5 */ { 0, BX_IA_ERROR },
/* 6 */ { BxPrefixSSEF2F3, BX_IA_RDRAND_Ew, BxOpcodeGroupSSE_ERR },
/* 7 */ { BxPrefixSSEF2F3, BX_IA_RDSEED_Ew, BxOpcodeGroupSSE_ERR },
/* 7 */ { BxPrefixSSEF2F3, BX_IA_RDSEED_Ew, BxOpcodeGroupSSE_RDPID },
/* /m form */
/* 0 */ { 0, BX_IA_ERROR },
@ -898,7 +910,7 @@ static const BxOpcodeInfo_t BxOpcodeInfoG9d[8*2] = {
/* 4 */ { 0, BX_IA_ERROR },
/* 5 */ { 0, BX_IA_ERROR },
/* 6 */ { BxPrefixSSEF2F3, BX_IA_RDRAND_Ed, BxOpcodeGroupSSE_ERR },
/* 7 */ { BxPrefixSSEF2F3, BX_IA_RDSEED_Ed, BxOpcodeGroupSSE_ERR },
/* 7 */ { BxPrefixSSEF2F3, BX_IA_RDSEED_Ed, BxOpcodeGroupSSE_RDPID },
/* /m form */
/* 0 */ { 0, BX_IA_ERROR },
@ -921,7 +933,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64G9q[8*2] = {
/* 4 */ { 0, BX_IA_ERROR },
/* 5 */ { 0, BX_IA_ERROR },
/* 6 */ { BxPrefixSSEF2F3, BX_IA_RDRAND_Eq, BxOpcodeGroupSSE_ERR },
/* 7 */ { BxPrefixSSEF2F3, BX_IA_RDSEED_Eq, BxOpcodeGroupSSE_ERR },
/* 7 */ { BxPrefixSSEF2F3, BX_IA_RDSEED_Eq, BxOpcodeGroupSSE_RDPID },
/* /m form */
/* 0 */ { 0, BX_IA_ERROR },

5
bochs/cpu/ia_opcodes.h
View File

@ -1603,6 +1603,11 @@ bx_define_opcode(BX_IA_RDPKRU, &BX_CPU_C::BxError, &BX_CPU_C::RDPKRU, BX_ISA_PKU
bx_define_opcode(BX_IA_WRPKRU, &BX_CPU_C::BxError, &BX_CPU_C::WRPKRU, BX_ISA_PKU, OP_NONE, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
#endif
bx_define_opcode(BX_IA_RDPID_Ed, NULL, &BX_CPU_C::RDPID_Ed, BX_ISA_RDPID, OP_Ed, OP_NONE, OP_NONE, OP_NONE, 0)
#if BX_SUPPORT_X86_64
bx_define_opcode(BX_IA_RDPID_Eq, NULL, &BX_CPU_C::RDPID_Ed, BX_ISA_RDPID, OP_Eq, OP_NONE, OP_NONE, OP_NONE, 0)
#endif
#if BX_SUPPORT_AVX && BX_CPU_LEVEL >= 6
// AVX1/AVX2
bx_define_opcode(BX_IA_VZEROUPPER, NULL, &BX_CPU_C::VZEROUPPER, BX_ISA_AVX, OP_NONE, OP_NONE, OP_NONE, OP_NONE, BX_PREPARE_AVX)

26
bochs/cpu/proc_ctrl.cc
View File

@ -652,7 +652,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDTSCP(bxInstruction_c *i)
#if BX_SUPPORT_X86_64
#if BX_SUPPORT_VMX
// RDTSCP will always #UD in legacy VMX mode
// RDPID will always #UD in legacy VMX mode
if (BX_CPU_THIS_PTR in_vmx_guest) {
if (! SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_RDTSCP)) {
BX_ERROR(("%s in VMX guest: not allowed to use instruction !", i->getIaOpcodeNameShort()));
@ -691,6 +691,26 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDTSCP(bxInstruction_c *i)
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDPID_Ed(bxInstruction_c *i)
{
#if BX_SUPPORT_X86_64
#if BX_SUPPORT_VMX
// RDTSCP will always #UD in legacy VMX mode
if (BX_CPU_THIS_PTR in_vmx_guest) {
if (! SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_RDTSCP)) {
BX_ERROR(("%s in VMX guest: not allowed to use instruction !", i->getIaOpcodeNameShort()));
exception(BX_UD_EXCEPTION, 0);
}
}
#endif
BX_WRITE_32BIT_REGZ(i->dst(), BX_CPU_THIS_PTR msr.tsc_aux);
#endif
BX_NEXT_INSTR(i);
}
#if BX_SUPPORT_MONITOR_MWAIT
bx_bool BX_CPU_C::is_monitor(bx_phy_address begin_addr, unsigned len)
{
@ -1479,6 +1499,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDPKRU(bxInstruction_c *i)
RAX = BX_CPU_THIS_PTR pkru;
RDX = 0;
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::WRPKRU(bxInstruction_c *i)
@ -1490,6 +1512,8 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::WRPKRU(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
BX_CPU_THIS_PTR set_PKRU(EAX);
BX_NEXT_TRACE(i);
}
#endif // BX_SUPPORT_PKEYS

30
bochs/cpu/protect_ctrl.cc
View File

@ -286,6 +286,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SLDT_Ew(bxInstruction_c *i)
exception(BX_UD_EXCEPTION, 0);
}
if (CPL!=0 && BX_CPU_THIS_PTR cr4.get_UMIP()) {
BX_ERROR(("SLDT: CPL != 0 causes #GP when CR4.UMIP set"));
exception(BX_GP_EXCEPTION, 0);
}
#if BX_SUPPORT_VMX >= 2
if (BX_CPU_THIS_PTR in_vmx_guest)
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_DESCRIPTOR_TABLE_VMEXIT))
@ -323,6 +328,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::STR_Ew(bxInstruction_c *i)
exception(BX_UD_EXCEPTION, 0);
}
if (CPL!=0 && BX_CPU_THIS_PTR cr4.get_UMIP()) {
BX_ERROR(("STR: CPL != 0 causes #GP when CR4.UMIP set"));
exception(BX_GP_EXCEPTION, 0);
}
#if BX_SUPPORT_VMX >= 2
if (BX_CPU_THIS_PTR in_vmx_guest)
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_DESCRIPTOR_TABLE_VMEXIT))
@ -746,6 +756,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SGDT_Ms(bxInstruction_c *i)
{
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
if (CPL!=0 && BX_CPU_THIS_PTR cr4.get_UMIP()) {
BX_ERROR(("SGDT: CPL != 0 causes #GP when CR4.UMIP set"));
exception(BX_GP_EXCEPTION, 0);
}
#if BX_SUPPORT_VMX >= 2
if (BX_CPU_THIS_PTR in_vmx_guest)
if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_DESCRIPTOR_TABLE_VMEXIT))
@ -771,6 +786,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SGDT_Ms(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SIDT_Ms(bxInstruction_c *i)
{
if (CPL!=0 && BX_CPU_THIS_PTR cr4.get_UMIP()) {
BX_ERROR(("SIDT: CPL != 0 causes #GP when CR4.UMIP set"));
exception(BX_GP_EXCEPTION, 0);
}
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
#if BX_SUPPORT_VMX >= 2
@ -870,6 +890,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LIDT_Ms(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SGDT64_Ms(bxInstruction_c *i)
{
if (CPL!=0 && BX_CPU_THIS_PTR cr4.get_UMIP()) {
BX_ERROR(("SGDT: CPL != 0 causes #GP when CR4.UMIP set"));
exception(BX_GP_EXCEPTION, 0);
}
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64);
#if BX_SUPPORT_VMX >= 2
@ -897,6 +922,11 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SGDT64_Ms(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SIDT64_Ms(bxInstruction_c *i)
{
if (CPL!=0 && BX_CPU_THIS_PTR cr4.get_UMIP()) {
BX_ERROR(("SIDT: CPL != 0 causes #GP when CR4.UMIP set"));
exception(BX_GP_EXCEPTION, 0);
}
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64);
#if BX_SUPPORT_VMX >= 2

2
bochs/cpu/vmx.cc
View File

@ -102,7 +102,7 @@ static const char *VMX_vmexit_reason_name[] =
/* 57 */ "RDRAND",
/* 58 */ "INVPCID",
/* 59 */ "VMFUNC",
/* 60 */ "Reserved60",
/* 60 */ "ENCLS",
/* 61 */ "RDSEED",
/* 62 */ "PML Log Full",
/* 63 */ "XSAVES",

9
bochs/cpu/vmx.h
View File

@ -130,7 +130,7 @@ enum VMX_vmexit_reason {
VMX_VMEXIT_RDRAND = 57,
VMX_VMEXIT_INVPCID = 58,
VMX_VMEXIT_VMFUNC = 59,
VMX_VMEXIT_RESERVED60 = 60,
VMX_VMEXIT_ENCLS = 60,
VMX_VMEXIT_RDSEED = 61,
VMX_VMEXIT_PML_LOGFULL = 62,
VMX_VMEXIT_XSAVES = 63,
@ -263,6 +263,8 @@ enum VMFunctions {
#define VMCS_64BIT_CONTROL_VE_EXCEPTION_INFO_ADDR_HI 0x0000202B
#define VMCS_64BIT_CONTROL_XSS_EXITING_BITMAP 0x0000202C /* XSAVES */
#define VMCS_64BIT_CONTROL_XSS_EXITING_BITMAP_HI 0x0000202D
#define VMCS_64BIT_CONTROL_ENCLS_EXITING_BITMAP 0x0000202E /* ENCLS/SGX */
#define VMCS_64BIT_CONTROL_ENCLS_EXITING_BITMAP_HI 0x0000202F
#define VMCS_64BIT_CONTROL_TSC_MULTIPLIER 0x00002032 /* TSC Scaling */
#define VMCS_64BIT_CONTROL_TSC_MULTIPLIER_HI 0x00002033
@ -291,6 +293,8 @@ enum VMFunctions {
#define VMCS_64BIT_GUEST_IA32_PDPTE2_HI 0x0000280F
#define VMCS_64BIT_GUEST_IA32_PDPTE3 0x00002810
#define VMCS_64BIT_GUEST_IA32_PDPTE3_HI 0x00002811
#define VMCS_64BIT_GUEST_IA32_BNDCFGS 0x00002812 /* MPX */
#define VMCS_64BIT_GUEST_IA32_BNDCFGS_HI 0x00002813
/* VMCS 64-bit host state fields */
/* binary 0010_11xx_xxxx_xxx0 */
@ -676,6 +680,7 @@ typedef struct bx_VMCS
#define VMX_VM_EXEC_CTRL3_INVPCID (1 << 12)
#define VMX_VM_EXEC_CTRL3_VMFUNC_ENABLE (1 << 13) /* VM Functions */
#define VMX_VM_EXEC_CTRL3_VMCS_SHADOWING (1 << 14) /* VMCS Shadowing */
#define VMX_VM_EXEC_CTRL3_SGX_ENCLS_VMEXIT (1 << 15) /* ENCLS/SGX */
#define VMX_VM_EXEC_CTRL3_RDSEED_VMEXIT (1 << 16)
#define VMX_VM_EXEC_CTRL3_PML_ENABLE (1 << 17) /* Page Modification Logging */
#define VMX_VM_EXEC_CTRL3_EPT_VIOLATION_EXCEPTION (1 << 18) /* #VE Exception */
@ -757,6 +762,7 @@ typedef struct bx_VMCS
#define VMX_VMEXIT_CTRL1_STORE_EFER_MSR (1 << 20) /* EFER */
#define VMX_VMEXIT_CTRL1_LOAD_EFER_MSR (1 << 21) /* EFER */
#define VMX_VMEXIT_CTRL1_STORE_VMX_PREEMPTION_TIMER (1 << 22) /* VMX preemption timer */
#define VMX_VMEXIT_CTRL1_CLEAR_BNDCFGS (1 << 23) /* MPX */
#define VMX_VMEXIT_CTRL1_SUPPRESS_VMX_PACKETS (1 << 24) /* Processor Trace */
#define VMX_VMEXIT_CTRL1_SUPPORTED_BITS \
@ -780,6 +786,7 @@ typedef struct bx_VMCS
#define VMX_VMENTRY_CTRL1_LOAD_PERF_GLOBAL_CTRL_MSR (1 << 13) /* Perf Global Ctrl */
#define VMX_VMENTRY_CTRL1_LOAD_PAT_MSR (1 << 14) /* PAT */
#define VMX_VMENTRY_CTRL1_LOAD_EFER_MSR (1 << 15) /* EFER */
#define VMX_VMENTRY_CTRL1_LOAD_BNDCFGS (1 << 16) /* MPX */
#define VMX_VMENTRY_CTRL1_SUPPRESS_VMX_PACKETS (1 << 17) /* Processor Trace */
#define VMX_VMENTRY_CTRL1_SUPPORTED_BITS \

2
bochs/disasm/disasm.h
View File

@ -122,6 +122,8 @@ enum {
IA_FCS_FDS_DEPRECATION, /* FCS/FDS Deprecation */
IA_FDP_DEPRECATION, /* FDP Deprecation */
IA_PKU, /* User-Mode Protection Keys */
IA_UMIP, /* User-Mode Instruction Prevention */
IA_RDPID, /* RDPID support */
IA_EXTENSION_LAST
};