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93 Commits

Author SHA1 Message Date
Stanislav Shwartsman
dd7b968404 SSE cvt instructions: transition from FPU to MMX state has higher priority than SSE exception (#XF/#UD) 2012-08-11 07:41:13 +00:00
Stanislav Shwartsman
cc694377b9 Standartization of Bochs instruction handlers. 
Bochs instruction emulation handlers won't refer to direct fields of instructions like MODRM.NNN or MODRM.RM anymore.
Use generic source/destination indications like SRC1, SRC2 and DST.
All handlers are modified to support new notation. In addition fetchDecode module was modified to assign sources to instructions properly.

Immediate benefits:
- Removal of several duplicated handlers (FMA3 duplicated with FMA4 is a trivial example)
- Simpler to understand fetch-decode code

Future benefits:
- Integration of disassembler into Bochs CPU module, ability to disasm bx_instruction_c instance (planned)

Huge patch. Almost all source files wre modified.
 2012-08-05 13:52:40 +00:00
Stanislav Shwartsman
16ecab5644 trying to guess real HW behavior for (V)DPPS/(V)DPPD instructions 2012-06-30 18:19:22 +00:00
Stanislav Shwartsman
e282b5e88d Move DAZ handling into softfloat library (for float16, float32 and float64 only) and cleanup SSE and AVX code 
Fix decoding of opcodes with VEX.W=1 in 32-bit mode (AVX2, FMA)
 2011-10-01 15:40:36 +00:00
Stanislav Shwartsman
2583f8549a small code duplication fix 2011-09-19 20:47:59 +00:00
Stanislav Shwartsman
44241a1e56 - Added support for AVX and AVX2 instructions emulation, to enable configure 
with --enable-avx option. When compiled in, AVX still has to be enabled
    using .bochsrc CPUID option. AVX2 FMA instructions still not implemented.

  - Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
    instructions support can be enabled using .bochsrc CPUID option.
 2011-08-27 13:47:16 +00:00
Stanislav Shwartsman
4fae848888 just rename variable 2011-08-23 20:27:52 +00:00
Stanislav Shwartsman
002c86660a reword all the CPU code in preparation for future CPU speedup implementation. 
Bochs emulation can be another 10-15% faster using technique described in paper
"Fast Microcode Interpretation with Transactional Commit/Abort"
http://amas-bt.cs.virginia.edu/2011proceedings/amasbt2011-p3.pdf
 2011-07-06 20:01:18 +00:00
Stanislav Shwartsman
2f582db722 compile less stuff for cpu-level=5 2011-06-26 19:15:30 +00:00
Stanislav Shwartsman
7664c55b08 first fixups after AVX 
(and for AVX)
 2011-03-20 18:27:31 +00:00
Stanislav Shwartsman
7ced718040 implemented AVX instructions support 
many changes - some cleanup will follow
please report ay found bugs !
 2011-03-19 20:09:34 +00:00
Stanislav Shwartsman
7d80a6ebe0 Adding Id and Rev property to all files 2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
2d3f3668c7 Fixed IRET 64-bit mode bug 
Support for 32 float copare methods for AVX
ckeanups in fetchdecode
 2011-02-13 06:10:11 +00:00
Stanislav Shwartsman
12005d92cf split more SSE ops 2011-01-21 19:46:44 +00:00
Stanislav Shwartsman
0de2b305bc split SSE opcode 2011-01-21 19:21:16 +00:00
Stanislav Shwartsman
fbc9b8b190 phase1 of opcode tables optimization 2011-01-20 16:24:42 +00:00
Stanislav Shwartsman
6a20d16562 indent 2011-01-13 20:48:29 +00:00
Stanislav Shwartsman
2ce1bd299c conditional compiling with misaligned sse 2011-01-12 20:16:25 +00:00
Stanislav Shwartsman
a80b44b6db split more sse ops 2011-01-09 20:18:02 +00:00
Stanislav Shwartsman
a1bc92a46b split more SSE opcodes 2011-01-08 11:20:29 +00:00
Stanislav Shwartsman
fd5558d4be another way to implement this op 2010-12-26 20:54:23 +00:00
Stanislav Shwartsman
25b1e2e58d split more SSE ops 2010-12-26 20:41:47 +00:00
Stanislav Shwartsman
1bd512e98d split more SSE ops, optimizations in MMX code 2010-12-25 17:04:36 +00:00
Stanislav Shwartsman
c005444d5b split more SSE opcodes 2010-12-25 07:59:15 +00:00
Stanislav Shwartsman
040a8e1a3a split bunch of SSE opcodes 2010-12-24 08:35:00 +00:00
Stanislav Shwartsman
43600f3756 complete rework of SSE code 
next step - split all SSE opcodes by ModC0
 2010-12-22 21:16:02 +00:00
Stanislav Shwartsman
a63b9900a7 optimization 2010-12-19 22:50:28 +00:00
Stanislav Shwartsman
9746e16657 SSE unmasked exceptions report fix 2010-04-14 20:20:17 +00:00
Stanislav Shwartsman
cffe32dd2c remove unused param from exception() call 2010-03-14 15:51:27 +00:00
Stanislav Shwartsman
927c3594d6 enable compilation with CPU_LEVEL <= 6 
converted SEP to runtime option as well
 2010-02-26 11:44:50 +00:00
Stanislav Shwartsman
033a20b3b2 allow to configure CPU features at runtime - implemened on example of SSE/AES/MOVBE/POPCNT 2010-02-25 22:04:31 +00:00
Stanislav Shwartsman
7254ea36a1 copyright fixes + small optimization 2009-10-14 20:45:29 +00:00
Stanislav Shwartsman
8e3276cf14 split opcodes by ModC0 2009-08-22 11:47:42 +00:00
Stanislav Shwartsman
a259ba7321 FPU2MMX again 2009-08-22 11:02:45 +00:00
Stanislav Shwartsman
7a75cad5ea FPU2MMX fixed 2009-08-20 19:53:05 +00:00
Stanislav Shwartsman
cfa3611a5f bugfixes, comment fixes, compilation fix in VMX 2009-06-20 20:39:51 +00:00
Stanislav Shwartsman
d5efb5c378 implemented biasing of unmasked x87 over/underflow result 2009-06-05 17:48:55 +00:00
Stanislav Shwartsman
a98a917c98 code cleanup 2009-05-28 20:18:34 +00:00
Stanislav Shwartsman
98d632c197 Fixed ROUNDxx opcodes 2009-05-21 11:44:59 +00:00
Stanislav Shwartsman
024d36fa12 x87: fixed C1 (rounding up) for overflow condition 2009-04-11 17:00:28 +00:00
Stanislav Shwartsman
08de514d9c code cleanup for future optimization 2009-03-10 21:43:11 +00:00
Stanislav Shwartsman
9929e6ed78 - updated FSF address 2009-01-16 18:18:59 +00:00
Stanislav Shwartsman
489447ae57 Fixed FPU2MMX state transition - should be done only fater all memory faults already checked 2008-10-08 10:51:38 +00:00
Stanislav Shwartsman
5dd02b26e3 Make even more efficient RmAddr calculation - good optimizing compiler could make more efficient code than it was before 2008-08-08 09:22:49 +00:00
Stanislav Shwartsman
709d74728d Call #UD exception directly instead of UndefinedOpcode function - for future use 2008-07-13 15:35:10 +00:00
Stanislav Shwartsman
ec1ff39a5f Splitted memory access methods for 32 and 64-bit code. 
The 64-bit code got >10% speedup, the 32-bit code also got about 2% because laddr cacluation optimization
 2008-05-10 18:10:53 +00:00
Stanislav Shwartsman
affbdbefb4 do not cause tranition to MMX state if no MMX reg touched 2008-04-29 21:47:16 +00:00
Stanislav Shwartsman
57a8e24615 Fixed REOUNDPS/PD/SS/SD 2008-04-20 14:10:44 +00:00
Stanislav Shwartsman
a45df4b584 Fixed ROUNDPS/PD bug 2008-04-20 13:32:42 +00:00
Stanislav Shwartsman
9668e735cd Inline fpu exceptions functions 2008-04-14 16:50:27 +00:00