enable compilation with CPU_LEVEL <= 6

converted SEP to runtime option as well
2010-02-26 11:44:50 +00:00 · 2010-02-26 11:44:50 +00:00 · 927c3594d6
commit 927c3594d6
parent 32e5f1ffc8
30 changed files with 909 additions and 410 deletions
--- a/bochs/.bochsrc
+++ b/bochs/.bochsrc
@ -142,6 +142,10 @@ cpu: count=1, ips=50000000, reset_on_triple_fault=1, ignore_bad_msrs=1, msrs="ms
 #
 # This defines features and functionality supported by Bochs emulated CPU:
 #
+#  SEP:
+#  Select SYSENTER/SYSEXIT instruction set support.
+#  This option exists only if Bochs compiled with BX_CPU_LEVEL >= 6.
+#
 #  SSE:
 #  Select SSE instruction set support.
 #  Any of SSE/SSE2/SSE3/SSSE3/SSE4_1/SSE4_2 could be selected.
@ -167,7 +171,7 @@ cpu: count=1, ips=50000000, reset_on_triple_fault=1, ignore_bad_msrs=1, msrs="ms
 #  Determine whether to limit maximum CPUID function to 3. This mode is
 #  required to workaround WinNT installation and boot issues.
 #=======================================================================
-cpuid: sse=sse4_2, aes=1, movbe=1, cpuid_limit_winnt=0
+cpuid: sep=1, sse=sse4_2, aes=1, movbe=1, cpuid_limit_winnt=0

 #=======================================================================
 # MEMORY
--- a/bochs/CHANGES
+++ b/bochs/CHANGES
@ -29,10 +29,11 @@ Detailed change log :
    configure option is deprecated and should not be used anymore.

  - Enable changing of part of CPU functionality at runtime through .bochsrc
-    instead of configure time. Now you could choose to emulate any of
-    SSE/AES/MOVBE instruction sets using new CPUID option in .bochsrc.
-    Configure options --enable-sse, --enable-aes, --enable-movbe are
-    deprecated and should not be used anymore.
+    Now you could enable/disable any of SSEx/AES/MOVBE/SYSENTER_SYSEXIT 
+    instruction sets using new CPUID option in .bochsrc.
+    Configure options
+       --enable-sse, --enable-aes, --enable-movbe, --enable-sep
+    are deprecated and should not be used anymore.

 - CPU
  - Implemented PCLMULQDQ AES instruction
--- a/bochs/config.cc
+++ b/bochs/config.cc
@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: config.cc,v 1.193 2010-02-25 22:34:56 sshwarts Exp $
+// $Id: config.cc,v 1.194 2010-02-26 11:44:49 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2002-2009  The Bochs Project
@ -392,7 +392,7 @@ void bx_init_options()
      "sse", "Support for SSE instruction set",
      "Support for SSE/SSE2/SSE3/SSSE3/SSE4_1/SSE4_2 instruction set",
      sse_names,
-      BX_CPUID_SUPPORT_NOSSE,
+      BX_CPUID_SUPPORT_SSE2,
      BX_CPUID_SUPPORT_NOSSE);
  new bx_param_bool_c(cpuid_param,
      "movbe", "Support for MOVBE instruction",
@ -402,6 +402,10 @@ void bx_init_options()
      "aes", "Support for AES instruction set",
      "Support for AES instruction set",
      0);
+  new bx_param_bool_c(cpuid_param,
+      "sep", "Support for SYSENTER/SYSEXIT instructions",
+      "Support for SYSENTER/SYSEXIT instructions",
+      (BX_CPU_LEVEL >= 6 && BX_SUPPORT_MMX) || BX_SUPPORT_X86_64);
 #endif

  cpuid_param->set_options(menu->SHOW_PARENT);
@ -2604,6 +2608,12 @@ static int parse_line_formatted(const char *context, int num_params, char *param
        } else {
          PARSE_ERR(("%s: cpuid directive malformed.", context));
        }
+      } else if (!strncmp(params[i], "sep=", 4)) {
+        if (params[i][4] == '0' || params[i][4] == '1') {
+          SIM->get_param_bool(BXPN_CPUID_SEP)->set(params[i][4] - '0');
+        } else {
+          PARSE_ERR(("%s: cpuid directive malformed.", context));
+        }
 #endif
      } else {
        PARSE_ERR(("%s: cpuid directive malformed.", context));
@ -3766,8 +3776,9 @@ int bx_write_configuration(const char *rc, int overwrite)
  fprintf(fp, "\n");
  fprintf(fp, "cpuid: cpuid_limit_winnt=%d", SIM->get_param_bool(BXPN_CPUID_LIMIT_WINNT)->get());
 #if BX_CPU_LEVEL >= 6
-  fprintf(fp, ", sse=%s, aes=%d, movbe=%d",
+  fprintf(fp, ", sse=%s, sep=%d, aes=%d, movbe=%d",
    SIM->get_param_enum(BXPN_CPUID_SSE)->get_selected(),
+    SIM->get_param_bool(BXPN_CPUID_SEP)->get(),
    SIM->get_param_bool(BXPN_CPUID_AES)->get(),
    SIM->get_param_bool(BXPN_CPUID_MOVBE)->get());
 #endif
--- a/bochs/config.h.in
+++ b/bochs/config.h.in
@ -686,7 +686,6 @@ typedef
 #define BX_SUPPORT_MMX 0
 #define BX_SUPPORT_3DNOW 0
 #define BX_SUPPORT_MISALIGNED_SSE 0
-#define BX_SUPPORT_SEP 0
 #define BX_SUPPORT_MONITOR_MWAIT 0
 #define BX_SUPPORT_XSAVE 0
 #define BX_SUPPORT_VMX 0
@ -738,18 +737,10 @@ typedef
  #error "3DNow! cannot be compiled without MMX support !"
 #endif

-#if (BX_CPU_LEVEL<6 && BX_SUPPORT_SEP)
-  #error "SYSENTER/SYSEXIT only supported with CPU_LEVEL >= 6 !"
-#endif
-
 #if (BX_CPU_LEVEL<6 && BX_SUPPORT_VMX)
  #error "VMX only supported with CPU_LEVEL >= 6 !"
 #endif

-#if (BX_SUPPORT_VMX && BX_SUPPORT_SEP == 0)
-  #error "SYSENTER/SYSEXIT is required for VMX support !"
-#endif
-
 #if (BX_SUPPORT_X86_64 == 0 && BX_SUPPORT_1G_PAGES)
  #error "1G only supported with x86-64 !"
 #endif
--- a/bochs/configure
+++ b/bochs/configure
@ -1,5 +1,5 @@
 #! /bin/sh
-# From configure.in Id: configure.in,v 1.424 2010/02/24 20:59:49 sshwarts Exp .
+# From configure.in Id: configure.in,v 1.425 2010/02/25 22:04:30 sshwarts Exp .
 # Guess values for system-dependent variables and create Makefiles.
 # Generated by GNU Autoconf 2.65.
 #
@ -977,7 +977,6 @@ enable_3dnow
 enable_xsave
 enable_alignment_check
 enable_misaligned_sse
-enable_sep
 enable_xapic
 enable_monitor_mwait
 enable_x86_debugger
@ -1006,6 +1005,7 @@ enable_sse_extension
 enable_popcnt
 enable_movbe
 enable_aes
+enable_sep
 enable_apic
 enable_ignore_bad_msr
 enable_pae
@ -1696,7 +1696,6 @@ Optional Features:
  --enable-xsave                    support for XSAVE/XRSTOR extensions
  --enable-alignment-check          alignment check (#AC) support
  --enable-misaligned-sse           misaligned SSE support
-  --enable-sep                      SYSENTER/SYSEXIT support
  --enable-xapic                    support for XAPIC extensions
  --enable-monitor-mwait            support for MONITOR/MWAIT instructions (experimental)
  --enable-x86-debugger             x86 debugger support
@ -1712,6 +1711,7 @@ Optional Features:
  --enable-popcnt                   support for POPCNT intruction (deprecated)
  --enable-movbe                    support for MOVBE intruction (deprecated)
  --enable-aes                      support for AES intruction set (deprecated)
+  --enable-sep                      support for SYSENTER/SYSEXIT intructions (deprecated)
  --enable-apic                     enable APIC support (deprecated)
  --enable-ignore-bad-msr           ignore bad MSR references (deprecated)
  --enable-pae                      enables PAE support (deprecated)
@ -23025,7 +23025,6 @@ $as_echo "no" >&6; }
 fi


-support_mmx=1
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for MMX support" >&5
 $as_echo_n "checking for MMX support... " >&6; }
 # Check whether --enable-mmx was given.
@ -23040,7 +23039,6 @@ $as_echo "yes" >&6; }
 $as_echo "no" >&6; }
    $as_echo "#define BX_SUPPORT_MMX 0" >>confdefs.h

-    support_mmx=0
   fi

 else
@ -23178,40 +23176,6 @@ $as_echo "no" >&6; }
 fi


-{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for SEP support" >&5
-$as_echo_n "checking for SEP support... " >&6; }
-# Check whether --enable-sep was given.
-if test "${enable_sep+set}" = set; then :
-  enableval=$enable_sep; if test "$enableval" = yes; then
-    { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
-$as_echo "yes" >&6; }
-    $as_echo "#define BX_SUPPORT_SEP 1" >>confdefs.h
-
-   elif test "$enableval" = no; then
-    { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
-$as_echo "no" >&6; }
-    $as_echo "#define BX_SUPPORT_SEP 0" >>confdefs.h
-
-   fi
-
-else
-
-    if test "$bx_cpu_level" -ge 6 -a "$support_mmx" = 1; then
-      { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
-$as_echo "yes" >&6; }
-      $as_echo "#define BX_SUPPORT_SEP 1" >>confdefs.h
-
-    else
-      { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
-$as_echo "no" >&6; }
-      $as_echo "#define BX_SUPPORT_SEP 0" >>confdefs.h
-
-    fi
-
-
-fi
-
-
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for XAPIC support" >&5
 $as_echo_n "checking for XAPIC support... " >&6; }
 # Check whether --enable-xapic was given.
@ -25161,6 +25125,22 @@ $as_echo "no" >&6; }
 fi


+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for SEP support (deprecated)" >&5
+$as_echo_n "checking for SEP support (deprecated)... " >&6; }
+# Check whether --enable-sep was given.
+if test "${enable_sep+set}" = set; then :
+  enableval=$enable_sep; { $as_echo "$as_me:${as_lineno-$LINENO}: result: $enableval" >&5
+$as_echo "$enableval" >&6; }
+   as_fn_error "DEPRECATED - moved to .bochsrc options" "$LINENO" 5
+
+else
+
+   { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+
+fi
+
+
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for APIC support (deprecated)" >&5
 $as_echo_n "checking for APIC support (deprecated)... " >&6; }
 # Check whether --enable-apic was given.
--- a/bochs/configure.in
+++ b/bochs/configure.in
@ -2,7 +2,7 @@ dnl // Process this file with autoconf to produce a configure script.

 AC_PREREQ(2.50)
 AC_INIT(bochs.h)
-AC_REVISION([[$Id: configure.in,v 1.425 2010-02-25 22:04:30 sshwarts Exp $]])
+AC_REVISION([[$Id: configure.in,v 1.426 2010-02-26 11:44:50 sshwarts Exp $]])
 AC_CONFIG_HEADER(config.h)
 AC_CONFIG_HEADER(ltdlconf.h)

@ -1408,7 +1408,6 @@ AC_ARG_ENABLE(vmx,
  ]
  )

-support_mmx=1
 AC_MSG_CHECKING(for MMX support)
 AC_ARG_ENABLE(mmx,
  [  --enable-mmx                      MMX support],
@ -1418,7 +1417,6 @@ AC_ARG_ENABLE(mmx,
   elif test "$enableval" = no; then
    AC_MSG_RESULT(no)
    AC_DEFINE(BX_SUPPORT_MMX, 0)
-    support_mmx=0
   fi
   ],
  [
@ -1507,28 +1505,6 @@ AC_ARG_ENABLE(misaligned-sse,
    ]
  )

-AC_MSG_CHECKING(for SEP support)
-AC_ARG_ENABLE(sep,
-  [  --enable-sep                      SYSENTER/SYSEXIT support],
-  [if test "$enableval" = yes; then
-    AC_MSG_RESULT(yes)
-    AC_DEFINE(BX_SUPPORT_SEP, 1)
-   elif test "$enableval" = no; then
-    AC_MSG_RESULT(no)
-    AC_DEFINE(BX_SUPPORT_SEP, 0)
-   fi
-   ],
-  [
-    if test "$bx_cpu_level" -ge 6 -a "$support_mmx" = 1; then
-      AC_MSG_RESULT(yes)
-      AC_DEFINE(BX_SUPPORT_SEP, 1)
-    else
-      AC_MSG_RESULT(no)
-      AC_DEFINE(BX_SUPPORT_SEP, 0)
-    fi
-    ]
-  )
-
 AC_MSG_CHECKING(for XAPIC support)
 AC_ARG_ENABLE(xapic,
  [  --enable-xapic                    support for XAPIC extensions],
@ -2721,6 +2697,16 @@ AC_ARG_ENABLE(aes,
   AC_MSG_RESULT(no)
  ])

+AC_MSG_CHECKING(for SEP support (deprecated))
+AC_ARG_ENABLE(sep,
+  [  --enable-sep                      support for SYSENTER/SYSEXIT intructions (deprecated)],
+  [AC_MSG_RESULT($enableval)
+   AC_MSG_ERROR([DEPRECATED - moved to .bochsrc options])
+  ],
+  [
+   AC_MSG_RESULT(no)
+  ])
+
 AC_MSG_CHECKING(for APIC support (deprecated))
 AC_ARG_ENABLE(apic,
  [  --enable-apic                     enable APIC support (deprecated)],
--- a/bochs/cpu/aes.cc
+++ b/bochs/cpu/aes.cc
@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: aes.cc,v 1.9 2010-02-25 22:04:30 sshwarts Exp $
+// $Id: aes.cc,v 1.10 2010-02-26 11:44:50 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //   Copyright (c) 2008-2009 Stanislav Shwartsman
@ -26,6 +26,8 @@
 #include "cpu.h"
 #define LOG_THIS BX_CPU_THIS_PTR

+#if BX_CPU_LEVEL >= 6
+
 //
 // XMM - Byte Representation of a 128-bit AES State
 //
@ -285,9 +287,12 @@ BX_CPP_INLINE Bit32u AES_RotWord(Bit32u x)
  return (x >> 8) | (x << 24);
 }

+#endif
+
 /* 66 0F 38 DB */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESIMC_VdqWdq(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op;
@ -305,11 +310,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESIMC_VdqWdq(bxInstruction_c *i)
  AES_InverseMixColumns(op);

  BX_WRITE_XMM_REG(i->nnn(), op);
+#endif
 }

 /* 66 0F 38 DC */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESENC_VdqWdq(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;
@ -332,11 +339,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESENC_VdqWdq(bxInstruction_c *i)
  op1.xmm64u(1) ^= op2.xmm64u(1);

  BX_WRITE_XMM_REG(i->nnn(), op1);
+#endif
 }

 /* 66 0F 38 DD */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESENCLAST_VdqWdq(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;
@ -358,11 +367,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESENCLAST_VdqWdq(bxInstruction_c *i)
  op1.xmm64u(1) ^= op2.xmm64u(1);

  BX_WRITE_XMM_REG(i->nnn(), op1);
+#endif
 }

 /* 66 0F 38 DE */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESDEC_VdqWdq(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;
@ -385,11 +396,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESDEC_VdqWdq(bxInstruction_c *i)
  op1.xmm64u(1) ^= op2.xmm64u(1);

  BX_WRITE_XMM_REG(i->nnn(), op1);
+#endif
 }

 /* 66 0F 38 DF */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESDECLAST_VdqWdq(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;
@ -411,11 +424,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESDECLAST_VdqWdq(bxInstruction_c *i)
  op1.xmm64u(1) ^= op2.xmm64u(1);

  BX_WRITE_XMM_REG(i->nnn(), op1);
+#endif
 }

 /* 66 0F 3A DF */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESKEYGENASSIST_VdqWdqIb(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op, result;
@ -438,11 +453,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::AESKEYGENASSIST_VdqWdqIb(bxInstruction_c *
  result.xmm32u(3) = AES_RotWord(result.xmm32u(2)) ^ rcon32;

  BX_WRITE_XMM_REG(i->nnn(), result);
+#endif
 }

 /* 66 0F 3A 44 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCLMULQDQ_VdqWdqIb(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, r, a;
@ -484,4 +501,5 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCLMULQDQ_VdqWdqIb(bxInstruction_c *i)
  }

  BX_WRITE_XMM_REG(i->nnn(), r);
+#endif
 }
--- a/bochs/cpu/arith16.cc
+++ b/bochs/cpu/arith16.cc
@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: arith16.cc,v 1.73 2009-12-04 16:53:12 sshwarts Exp $
+// $Id: arith16.cc,v 1.74 2010-02-26 11:44:50 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001-2009  The Bochs Project
@ -275,7 +275,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CWD(bxInstruction_c *i)

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EwGwM(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 4
  Bit16u op1_16, op2_16, sum_16;

  /* XADD dst(r/m), src(r)
@ -295,15 +294,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EwGwM(bxInstruction_c *i)
  BX_WRITE_16BIT_REG(i->nnn(), op1_16);

  SET_FLAGS_OSZAPC_ADD_16(op1_16, op2_16, sum_16);
-#else
-  BX_INFO(("XADD_EwGw: not supported on < 80486"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EwGwR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 4
  Bit16u op1_16, op2_16, sum_16;

  /* XADD dst(r/m), src(r)
@ -324,10 +318,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EwGwR(bxInstruction_c *i)
  BX_WRITE_16BIT_REG(i->rm(), sum_16);

  SET_FLAGS_OSZAPC_ADD_16(op1_16, op2_16, sum_16);
-#else
-  BX_INFO(("XADD_EwGw: not supported on < 80486"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EwIwM(bxInstruction_c *i)
@ -474,7 +464,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::DEC_EwM(bxInstruction_c *i)

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EwGwM(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 4
  Bit16u op1_16, op2_16, diff_16;

  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -492,15 +481,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EwGwM(bxInstruction_c *i)
    // accumulator <-- dest
    AX = op1_16;
  }
-#else
-  BX_INFO(("CMPXCHG_EwGw: not supported for cpu-level <= 3"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EwGwR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 4
  Bit16u op1_16, op2_16, diff_16;

  op1_16 = BX_READ_16BIT_REG(i->rm());
@ -516,8 +500,4 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EwGwR(bxInstruction_c *i)
    // accumulator <-- dest
    AX = op1_16;
  }
-#else
-  BX_INFO(("CMPXCHG_EwGw: not supported for cpu-level <= 3"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }
--- a/bochs/cpu/arith32.cc
+++ b/bochs/cpu/arith32.cc
@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: arith32.cc,v 1.84 2009-12-04 16:53:12 sshwarts Exp $
+// $Id: arith32.cc,v 1.85 2010-02-26 11:44:50 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001-2009  The Bochs Project
@ -315,7 +315,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_IBTS(bxInstruction_c *i)

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EdGdM(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 4
  Bit32u op1_32, op2_32, sum_32;

  /* XADD dst(r/m), src(r)
@ -335,15 +334,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EdGdM(bxInstruction_c *i)
  BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);

  SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
-#else
-  BX_INFO (("XADD_EdGd not supported for cpulevel <= 3"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EdGdR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 4
  Bit32u op1_32, op2_32, sum_32;

  /* XADD dst(r/m), src(r)
@ -364,10 +358,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EdGdR(bxInstruction_c *i)
  BX_WRITE_32BIT_REGZ(i->rm(), sum_32);

  SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32);
-#else
-  BX_INFO (("XADD_EdGd not supported for cpulevel <= 3"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EdIdM(bxInstruction_c *i)
@ -523,7 +513,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::DEC_EdM(bxInstruction_c *i)

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EdGdM(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 4
  Bit32u op1_32, op2_32, diff_32;

  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -541,15 +530,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EdGdM(bxInstruction_c *i)
    // accumulator <-- dest
    RAX = op1_32;
  }
-#else
-  BX_INFO(("CMPXCHG_EdGd: not supported for cpulevel <= 3"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EdGdR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 4
  Bit32u op1_32, op2_32, diff_32;

  op1_32 = BX_READ_32BIT_REG(i->rm());
@ -565,15 +549,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EdGdR(bxInstruction_c *i)
    // accumulator <-- dest
    RAX = op1_32;
  }
-#else
-  BX_INFO(("CMPXCHG_EdGd: not supported for cpulevel <= 3"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG8B(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 5
  Bit64u op1_64, op2_64;

  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -594,9 +573,4 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG8B(bxInstruction_c *i)
    RDX = GET32H(op1_64);
    clear_ZF();
  }
-
-#else
-  BX_INFO(("CMPXCHG8B: not supported for cpulevel <= 4"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }
--- a/bochs/cpu/arith8.cc
+++ b/bochs/cpu/arith8.cc
@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: arith8.cc,v 1.62 2009-12-04 16:53:12 sshwarts Exp $
+// $Id: arith8.cc,v 1.63 2010-02-26 11:44:50 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001-2009  The Bochs Project
@ -245,7 +245,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_ALIb(bxInstruction_c *i)

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EbGbM(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 4
  Bit8u op1, op2, sum;

  /* XADD dst(r/m8), src(r8)
@ -265,15 +264,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EbGbM(bxInstruction_c *i)
  BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op1);

  SET_FLAGS_OSZAPC_ADD_8(op1, op2, sum);
-#else
-  BX_INFO(("XADD_EbGb: not supported on < 80486"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EbGbR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 4
  Bit8u op1, op2, sum;

  /* XADD dst(r/m8), src(r8)
@ -294,10 +288,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EbGbR(bxInstruction_c *i)
  BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), sum);

  SET_FLAGS_OSZAPC_ADD_8(op1, op2, sum);
-#else
-  BX_INFO(("XADD_EbGb: not supported on < 80486"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADD_EbIbM(bxInstruction_c *i)
--- a/bochs/cpu/bit.cc
+++ b/bochs/cpu/bit.cc
@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: bit.cc,v 1.66 2010-02-25 22:04:30 sshwarts Exp $
+// $Id: bit.cc,v 1.67 2010-02-26 11:44:50 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001-2009  The Bochs Project
@ -238,7 +238,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SETNLE_EbR(bxInstruction_c *i)

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSWAP_ERX(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 4
  Bit32u val32, b0, b1, b2, b3;

  if (i->os32L() == 0) {
@ -253,10 +252,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSWAP_ERX(bxInstruction_c *i)
  val32 = (b0<<24) | (b1<<16) | (b2<<8) | b3;

  BX_WRITE_32BIT_REGZ(i->opcodeReg(), val32);
-#else
-  BX_INFO(("BSWAP_ERX: required CPU >= 4, use --enable-cpu-level=4 option"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 #if BX_SUPPORT_X86_64
--- a/bochs/cpu/cpu.h
+++ b/bochs/cpu/cpu.h
@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: cpu.h,v 1.640 2010-02-25 22:04:30 sshwarts Exp $
+// $Id: cpu.h,v 1.641 2010-02-26 11:44:50 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001-2009  The Bochs Project
@ -285,10 +285,10 @@ struct BxExceptionInfo {
 #define BX_MSR_TSC                 0x010
 #define BX_MSR_APICBASE            0x01b

-#if BX_SUPPORT_SEP
-#  define BX_MSR_SYSENTER_CS       0x174
-#  define BX_MSR_SYSENTER_ESP      0x175
-#  define BX_MSR_SYSENTER_EIP      0x176
+#if BX_CPU_LEVEL >= 6
+  #define BX_MSR_SYSENTER_CS       0x174
+  #define BX_MSR_SYSENTER_ESP      0x175
+  #define BX_MSR_SYSENTER_EIP      0x176
 #endif

 #define BX_MSR_DEBUGCTLMSR         0x1d9
@ -574,7 +574,7 @@ typedef struct
  Bit64u tsc_last_reset;

  // SYSENTER/SYSEXIT instruction msr's
-#if BX_SUPPORT_SEP
+#if BX_CPU_LEVEL >= 6
  Bit32u sysenter_cs_msr;
  bx_address sysenter_esp_msr;
  bx_address sysenter_eip_msr;
@ -755,6 +755,9 @@ typedef struct {

 #if BX_SUPPORT_FPU
 #include "cpu/i387.h"
+#endif
+
+#if BX_CPU_LEVEL >= 6
 #include "cpu/xmm.h"
 #endif

@ -892,9 +895,11 @@ public: // for now...
  i387_t the_i387;
 #endif

+#if BX_CPU_LEVEL >= 6
  bx_xmm_reg_t xmm[BX_XMM_REGISTERS]; // need TMP XMM register ?
  bx_mxcsr_t mxcsr;
  Bit32u mxcsr_mask;
+#endif

 #if BX_SUPPORT_MONITOR_MWAIT
  monitor_addr_t monitor;
@ -3330,9 +3335,11 @@ public: // for now...
  BX_SMF void prepareFPU2MMX(void); /* cause transition from FPU to MMX technology state */
  BX_SMF void print_state_MMX(void);

+#if BX_CPU_LEVEL >= 6
  BX_SMF void prepareSSE(void);
  BX_SMF void check_exceptionsSSE(int);
  BX_SMF void print_state_SSE(void);
+#endif

 #if BX_SUPPORT_XSAVE
  BX_SMF void prepareXSAVE(void);
@ -3424,6 +3431,7 @@ BX_CPP_INLINE void BX_CPU_C::prepareMMX(void)
 }
 #endif

+#if BX_CPU_LEVEL >= 6
 BX_CPP_INLINE void BX_CPU_C::prepareSSE(void)
 {
  if(BX_CPU_THIS_PTR cr0.get_EM() || !BX_CPU_THIS_PTR cr4.get_OSFXSR())
@ -3432,6 +3440,7 @@ BX_CPP_INLINE void BX_CPU_C::prepareSSE(void)
  if(BX_CPU_THIS_PTR cr0.get_TS())
    exception(BX_NM_EXCEPTION, 0, 0);
 }
+#endif

 #if BX_SUPPORT_XSAVE
 BX_CPP_INLINE void BX_CPU_C::prepareXSAVE(void)
--- a/bochs/cpu/cpuid.cc
+++ b/bochs/cpu/cpuid.cc
@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: cpuid.cc,v 1.91 2010-02-25 22:44:46 sshwarts Exp $
+// $Id: cpuid.cc,v 1.92 2010-02-26 11:44:50 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //   Copyright (c) 2007-2009 Stanislav Shwartsman
@ -764,6 +764,7 @@ void BX_CPU_C::init_cpu_features_bitmask(void)
 {
  Bit32u features_bitmask = 0;

+  bx_bool sep_enabled = SIM->get_param_bool(BXPN_CPUID_SEP)->get();
  bx_bool aes_enabled = SIM->get_param_bool(BXPN_CPUID_AES)->get();
  bx_bool movbe_enabled = SIM->get_param_bool(BXPN_CPUID_MOVBE)->get();
  unsigned sse_enabled = SIM->get_param_enum(BXPN_CPUID_SSE)->get();
@ -812,6 +813,13 @@ void BX_CPU_C::init_cpu_features_bitmask(void)
  }
 #endif

+#if BX_SUPPORT_VMX
+  if (! sep_enabled) {
+    BX_PANIC(("PANIC: VMX emulation requires SYSENTER/SYSEXIT support !"));
+    return;
+  }
+#endif
+
 #if BX_SUPPORT_FPU
  features_bitmask |= BX_CPU_X87;
 #endif
@ -857,11 +865,11 @@ void BX_CPU_C::init_cpu_features_bitmask(void)
    default:
      break;
  };
+
+  if (sep_enabled)
+    features_bitmask |= BX_CPU_SYSENTER_SYSEXIT;
 #endif

-#if BX_SUPPORT_SEP
-  features_bitmask |= BX_CPU_SYSENTER_SYSEXIT;
-#endif
 #if BX_SUPPORT_VMX
  features_bitmask |= BX_CPU_VMX;
 #endif
--- a/bochs/cpu/data_xfer16.cc
+++ b/bochs/cpu/data_xfer16.cc
@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: data_xfer16.cc,v 1.66 2009-12-04 16:53:12 sshwarts Exp $
+// $Id: data_xfer16.cc,v 1.67 2010-02-26 11:44:50 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001-2009  The Bochs Project
@ -220,176 +220,96 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XCHG_EwGwR(bxInstruction_c *i)

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVO_GwEwR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (get_OF())
    BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
-#else
-  BX_INFO(("CMOVO_GwEw: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNO_GwEwR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (!get_OF())
    BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
-#else
-  BX_INFO(("CMOVNO_GwEw: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVB_GwEwR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (get_CF())
    BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
-#else
-  BX_INFO(("CMOVB_GwEw: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNB_GwEwR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (!get_CF())
    BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
-#else
-  BX_INFO(("CMOVNB_GwEw: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVZ_GwEwR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (get_ZF())
    BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
-#else
-  BX_INFO(("CMOVZ_GwEw: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNZ_GwEwR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (!get_ZF())
    BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
-#else
-  BX_INFO(("CMOVNZ_GwEw: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVBE_GwEwR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (get_CF() || get_ZF())
    BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
-#else
-  BX_INFO(("CMOVBE_GwEw: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNBE_GwEwR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (! (get_CF() || get_ZF()))
    BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
-#else
-  BX_INFO(("CMOVNBE_GwEw: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVS_GwEwR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (get_SF())
    BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
-#else
-  BX_INFO(("CMOVS_GwEw: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNS_GwEwR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (!get_SF())
    BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
-#else
-  BX_INFO(("CMOVNS_GwEw: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVP_GwEwR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (get_PF())
    BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
-#else
-  BX_INFO(("CMOVP_GwEw: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNP_GwEwR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (!get_PF())
    BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
-#else
-  BX_INFO(("CMOVNP_GwEw: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVL_GwEwR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (getB_SF() != getB_OF())
    BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
-#else
-  BX_INFO(("CMOVL_GwEw: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNL_GwEwR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (getB_SF() == getB_OF())
    BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
-#else
-  BX_INFO(("CMOVNL_GwEw: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVLE_GwEwR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (get_ZF() || (getB_SF() != getB_OF()))
    BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
-#else
-  BX_INFO(("CMOVLE_GwEw: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNLE_GwEwR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (! get_ZF() && (getB_SF() == getB_OF()))
    BX_WRITE_16BIT_REG(i->nnn(), BX_READ_16BIT_REG(i->rm()));
-#else
-  BX_INFO(("CMOVNLE_GwEw: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }
--- a/bochs/cpu/data_xfer32.cc
+++ b/bochs/cpu/data_xfer32.cc
@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: data_xfer32.cc,v 1.65 2009-12-04 16:53:12 sshwarts Exp $
+// $Id: data_xfer32.cc,v 1.66 2010-02-26 11:44:50 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001-2009  The Bochs Project
@ -190,208 +190,128 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::XCHG_EdGdR(bxInstruction_c *i)

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVO_GdEdR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (get_OF())
    BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));

  BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
-#else
-  BX_INFO(("CMOVO_GdEd: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNO_GdEdR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (!get_OF())
    BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));

  BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
-#else
-  BX_INFO(("CMOVNO_GdEd: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVB_GdEdR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (get_CF())
    BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));

  BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
-#else
-  BX_INFO(("CMOVB_GdEd: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNB_GdEdR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (!get_CF())
    BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));

  BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
-#else
-  BX_INFO(("CMOVNB_GdEd: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVZ_GdEdR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (get_ZF())
    BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));

  BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
-#else
-  BX_INFO(("CMOVZ_GdEd: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNZ_GdEdR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (!get_ZF())
    BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));

  BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
-#else
-  BX_INFO(("CMOVNZ_GdEd: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVBE_GdEdR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (get_CF() || get_ZF())
    BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));

  BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
-#else
-  BX_INFO(("CMOVBE_GdEd: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNBE_GdEdR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (! (get_CF() || get_ZF()))
    BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));

  BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
-#else
-  BX_INFO(("CMOVNBE_GdEd: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVS_GdEdR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (get_SF())
    BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));

  BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
-#else
-  BX_INFO(("CMOVS_GdEd: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNS_GdEdR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (!get_SF())
    BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));

  BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
-#else
-  BX_INFO(("CMOVNS_GdEd: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVP_GdEdR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (get_PF())
    BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));

  BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
-#else
-  BX_INFO(("CMOVP_GdEd: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNP_GdEdR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (!get_PF())
    BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));

  BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
-#else
-  BX_INFO(("CMOVNP_GdEd: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVL_GdEdR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (getB_SF() != getB_OF())
    BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));

  BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
-#else
-  BX_INFO(("CMOVL_GdEd: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNL_GdEdR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (getB_SF() == getB_OF())
    BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));

  BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
-#else
-  BX_INFO(("CMOVNL_GdEd: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVLE_GdEdR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (get_ZF() || (getB_SF() != getB_OF()))
    BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));

  BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
-#else
-  BX_INFO(("CMOVLE_GdEd: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMOVNLE_GdEdR(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 6
  if (! get_ZF() && (getB_SF() == getB_OF()))
    BX_WRITE_32BIT_REGZ(i->nnn(), BX_READ_32BIT_REG(i->rm()));

  BX_CLEAR_64BIT_HIGH(i->nnn()); // always clear upper part of the register
-#else
-  BX_INFO(("CMOVNLE_GdEd: --enable-cpu-level=6 required"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }
--- a/bochs/cpu/fetchdecode.cc
+++ b/bochs/cpu/fetchdecode.cc
@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: fetchdecode.cc,v 1.254 2010-02-25 22:44:46 sshwarts Exp $
+// $Id: fetchdecode.cc,v 1.255 2010-02-26 11:44:50 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001-2009  The Bochs Project
@ -2906,7 +2906,8 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BxError(bxInstruction_c *i)
 #endif
  }
  else {
-    BX_INFO(("%s: instruction not supported (signalling #UD)", get_bx_opcode_name(ia_opcode)));
+    BX_INFO(("%s: instruction not supported - signalling #UD (features bitmask: 0x%08x)",
+      get_bx_opcode_name(ia_opcode), BX_CPU_THIS_PTR cpuid_features_bitmask));
  }

  exception(BX_UD_EXCEPTION, 0, 0);
--- a/bochs/cpu/init.cc
+++ b/bochs/cpu/init.cc
@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: init.cc,v 1.225 2010-02-25 22:34:56 sshwarts Exp $
+// $Id: init.cc,v 1.226 2010-02-26 11:44:50 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001-2009  The Bochs Project
@ -425,12 +425,10 @@ void BX_CPU_C::register_state(void)
  BXRS_HEX_PARAM_FIELD(MSR, tsc_aux, msr.tsc_aux);
 #endif
  BXRS_HEX_PARAM_FIELD(MSR, tsc_last_reset, msr.tsc_last_reset);
-#if BX_SUPPORT_SEP
+#if BX_CPU_LEVEL >= 6
  BXRS_HEX_PARAM_FIELD(MSR, sysenter_cs_msr,  msr.sysenter_cs_msr);
  BXRS_HEX_PARAM_FIELD(MSR, sysenter_esp_msr, msr.sysenter_esp_msr);
  BXRS_HEX_PARAM_FIELD(MSR, sysenter_eip_msr, msr.sysenter_eip_msr);
-#endif
-#if BX_CPU_LEVEL >= 6
  BXRS_HEX_PARAM_FIELD(MSR, mtrrphysbase0, msr.mtrrphys[0]);
  BXRS_HEX_PARAM_FIELD(MSR, mtrrphysmask0, msr.mtrrphys[1]);
  BXRS_HEX_PARAM_FIELD(MSR, mtrrphysbase1, msr.mtrrphys[2]);
@ -499,6 +497,7 @@ void BX_CPU_C::register_state(void)
  BXRS_DEC_PARAM_FIELD(fpu, tos, the_i387.tos);
 #endif

+#if BX_CPU_LEVEL >= 6
  if (BX_CPU_SUPPORT_FEATURE(BX_CPU_SSE)) {
    bx_list_c *sse = new bx_list_c(cpu, "SSE", 2*BX_XMM_REGISTERS+1);
    BXRS_HEX_PARAM_FIELD(sse, mxcsr, mxcsr.mxcsr);
@ -509,6 +508,7 @@ void BX_CPU_C::register_state(void)
      new bx_shadow_num_c(sse, name, &xmm[n].xmm64u(0), BASE_HEX);
    }
  }
+#endif

 #if BX_SUPPORT_MONITOR_MWAIT
  bx_list_c *monitor_list = new bx_list_c(cpu, "MONITOR", 3);
@ -941,7 +941,7 @@ void BX_CPU_C::reset(unsigned source)
  }
 #endif

-#if BX_SUPPORT_SEP
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR msr.sysenter_cs_msr  = 0;
  BX_CPU_THIS_PTR msr.sysenter_esp_msr = 0;
  BX_CPU_THIS_PTR msr.sysenter_eip_msr = 0;
@ -1002,6 +1002,7 @@ void BX_CPU_C::reset(unsigned source)
  }
 #endif

+#if BX_CPU_LEVEL >= 6
  // Reset XMM state - unchanged on #INIT
  if (source == BX_RESET_HARDWARE) {
    for(n=0; n<BX_XMM_REGISTERS; n++)
@ -1017,6 +1018,7 @@ void BX_CPU_C::reset(unsigned source)
    if (BX_SUPPORT_MISALIGNED_SSE)
      BX_CPU_THIS_PTR mxcsr_mask |= MXCSR_MISALIGNED_EXCEPTION_MASK;
  }
+#endif

 #if BX_SUPPORT_VMX
  BX_CPU_THIS_PTR in_vmx = BX_CPU_THIS_PTR in_vmx_guest = 0;
--- a/bochs/cpu/mmx.cc
+++ b/bochs/cpu/mmx.cc
--- a/bochs/cpu/msr.cc
+++ b/bochs/cpu/msr.cc
@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: msr.cc,v 1.30 2009-11-13 15:55:46 sshwarts Exp $
+// $Id: msr.cc,v 1.31 2010-02-26 11:44:50 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //   Copyright (c) 2008-2009 Stanislav Shwartsman
@ -39,16 +39,34 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::rdmsr(Bit32u index, Bit64u *msr)

  switch(index) {

-#if BX_SUPPORT_SEP
+#if BX_CPU_LEVEL >= 6
    case BX_MSR_SYSENTER_CS:
+      if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
+        // failed to find the MSR, could #GP or ignore it silently
+        BX_ERROR(("RDMSR MSR_SYSENTER_CS: SYSENTER/SYSEXIT feature not enabled !"));
+        if (! BX_CPU_THIS_PTR ignore_bad_msrs)
+          return 0; // will result in #GP fault due to unknown MSR
+      }
      val64 = BX_CPU_THIS_PTR msr.sysenter_cs_msr;
      break;

    case BX_MSR_SYSENTER_ESP:
+      if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
+        // failed to find the MSR, could #GP or ignore it silently
+        BX_ERROR(("RDMSR MSR_SYSENTER_ESP: SYSENTER/SYSEXIT feature not enabled !"));
+        if (! BX_CPU_THIS_PTR ignore_bad_msrs)
+          return 0; // will result in #GP fault due to unknown MSR
+      }
      val64 = BX_CPU_THIS_PTR msr.sysenter_esp_msr;
      break;

    case BX_MSR_SYSENTER_EIP:
+      if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
+        // failed to find the MSR, could #GP or ignore it silently
+        BX_ERROR(("RDMSR MSR_SYSENTER_EIP: SYSENTER/SYSEXIT feature not enabled !"));
+        if (! BX_CPU_THIS_PTR ignore_bad_msrs)
+          return 0; // will result in #GP fault due to unknown MSR
+      }
      val64 = BX_CPU_THIS_PTR msr.sysenter_eip_msr;
      break;
 #endif
@ -268,12 +286,24 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::wrmsr(Bit32u index, Bit64u val_64)

  switch(index) {

-#if BX_SUPPORT_SEP
+#if BX_CPU_LEVEL >= 6
    case BX_MSR_SYSENTER_CS:
+      if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
+        // failed to find the MSR, could #GP or ignore it silently
+        BX_ERROR(("WRMSR MSR_SYSENTER_CS: SYSENTER/SYSEXIT feature not enabled !"));
+        if (! BX_CPU_THIS_PTR ignore_bad_msrs)
+          return 0; // will result in #GP fault due to unknown MSR
+      }
      BX_CPU_THIS_PTR msr.sysenter_cs_msr = val32_lo;
      break;

    case BX_MSR_SYSENTER_ESP:
+      if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
+        // failed to find the MSR, could #GP or ignore it silently
+        BX_ERROR(("WRMSR MSR_SYSENTER_ESP: SYSENTER/SYSEXIT feature not enabled !"));
+        if (! BX_CPU_THIS_PTR ignore_bad_msrs)
+          return 0; // will result in #GP fault due to unknown MSR
+      }
 #if BX_SUPPORT_X86_64
      if (! IsCanonical(val_64)) {
        BX_ERROR(("WRMSR: attempt to write non-canonical value to MSR_SYSENTER_ESP !"));
@ -284,6 +314,12 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::wrmsr(Bit32u index, Bit64u val_64)
      break;

    case BX_MSR_SYSENTER_EIP:
+      if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
+        // failed to find the MSR, could #GP or ignore it silently
+        BX_ERROR(("WRMSR MSR_SYSENTER_EIP: SYSENTER/SYSEXIT feature not enabled !"));
+        if (! BX_CPU_THIS_PTR ignore_bad_msrs)
+          return 0; // will result in #GP fault due to unknown MSR
+      }
 #if BX_SUPPORT_X86_64
      if (! IsCanonical(val_64)) {
        BX_ERROR(("WRMSR: attempt to write non-canonical value to MSR_SYSENTER_EIP !"));
--- a/bochs/cpu/paging.cc
+++ b/bochs/cpu/paging.cc
@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: paging.cc,v 1.190 2009-12-04 16:53:12 sshwarts Exp $
+// $Id: paging.cc,v 1.191 2010-02-26 11:44:50 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001-2009  The Bochs Project
@ -737,7 +737,6 @@ void BX_CPU_C::TLB_invlpg(bx_address laddr)

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::INVLPG(bxInstruction_c* i)
 {
-#if BX_CPU_LEVEL >= 4
  if (!real_mode() && CPL!=0) {
    BX_ERROR(("INVLPG: priveledge check failed, generate #GP(0)"));
    exception(BX_GP_EXCEPTION, 0, 0);
@ -759,10 +758,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::INVLPG(bxInstruction_c* i)

  BX_INSTR_TLB_CNTRL(BX_CPU_ID, BX_INSTR_INVLPG, laddr);
  TLB_invlpg(laddr);
-#else
-  BX_INFO(("INVLPG: required i486, use --enable-cpu=4 option"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 // error checking order - page not present, reserved bits, protection
--- a/bochs/cpu/proc_ctrl.cc
+++ b/bochs/cpu/proc_ctrl.cc
@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: proc_ctrl.cc,v 1.312 2010-02-25 22:04:30 sshwarts Exp $
+// $Id: proc_ctrl.cc,v 1.313 2010-02-26 11:44:50 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001-2009  The Bochs Project
@ -149,7 +149,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CLTS(bxInstruction_c *i)
 /* 0F 08 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::INVD(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 4
  if (!real_mode() && CPL!=0) {
    BX_ERROR(("INVD: priveledge check failed, generate #GP(0)"));
    exception(BX_GP_EXCEPTION, 0, 0);
@ -168,16 +167,11 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::INVD(bxInstruction_c *i)
  BX_INSTR_CACHE_CNTRL(BX_CPU_ID, BX_INSTR_INVD);

  flushICaches();
-#else
-  BX_INFO(("INVD: required 486 support, use --enable-cpu-level=4 option"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 /* 0F 09 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::WBINVD(bxInstruction_c *i)
 {
-#if BX_CPU_LEVEL >= 4
  if (!real_mode() && CPL!=0) {
    BX_ERROR(("INVD/WBINVD: priveledge check failed, generate #GP(0)"));
    exception(BX_GP_EXCEPTION, 0, 0);
@ -189,10 +183,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::WBINVD(bxInstruction_c *i)
  BX_INSTR_CACHE_CNTRL(BX_CPU_ID, BX_INSTR_WBINVD);

  flushICaches();
-#else
-  BX_INFO(("WBINVD: required 486 support, use --enable-cpu-level=4 option"));
-  exception(BX_UD_EXCEPTION, 0, 0);
-#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::CLFLUSH(bxInstruction_c *i)
@ -1514,12 +1504,8 @@ bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::SetCR4(bx_address val)

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::RDPMC(bxInstruction_c *i)
 {
-/* We need to be Pentium with MMX or later */
-#if (BX_CPU_LEVEL >= 6) || (BX_SUPPORT_MMX && BX_CPU_LEVEL == 5)
-  bx_bool pce = BX_CPU_THIS_PTR cr4.get_PCE();
-
-  if ((pce==1) || (CPL==0) || real_mode())
-  {
+#if BX_CPU_LEVEL >= 5
+  if (BX_CPU_THIS_PTR cr4.get_PCE() || CPL==0 || real_mode()) {

 #if BX_SUPPORT_VMX
    VMexit_RDPMC(i);
@ -1531,8 +1517,14 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RDPMC(bxInstruction_c *i)
     * limited to 40 bits.
     */

-    if ((ECX & 0xffffffff) >= 2)
-      exception(BX_GP_EXCEPTION, 0, 0);
+    if (BX_CPU_SUPPORT_FEATURE(BX_CPU_SSE2)) { // Pentium 4 processor (see cpuid.cc)
+      if ((ECX & 0x7fffffff) >= 18)
+        exception(BX_GP_EXCEPTION, 0, 0);
+    }
+    else {
+      if ((ECX & 0xffffffff) >= 2)
+        exception(BX_GP_EXCEPTION, 0, 0);
+    }

    // Most counters are for hardware specific details, which
    // we anyhow do not emulate (like pipeline stalls etc)
@ -1549,8 +1541,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RDPMC(bxInstruction_c *i)
    // not allowed to use RDPMC!
    exception(BX_GP_EXCEPTION, 0, 0);
  }
-#else
-  exception(BX_UD_EXCEPTION, 0, 0);
 #endif
 }

@ -1594,9 +1584,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RDTSC(bxInstruction_c *i)
    BX_ERROR(("RDTSC: not allowed to use instruction !"));
    exception(BX_GP_EXCEPTION, 0, 0);
  }
-#else
-  BX_INFO(("RDTSC: Pentium CPU required, use --enable-cpu=5"));
-  exception(BX_UD_EXCEPTION, 0, 0);
 #endif
 }

@ -1788,7 +1775,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MWAIT(bxInstruction_c *i)

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSENTER(bxInstruction_c *i)
 {
-#if BX_SUPPORT_SEP
+#if BX_CPU_LEVEL >= 6
  if (real_mode()) {
    BX_ERROR(("SYSENTER not recognized in real mode !"));
    exception(BX_GP_EXCEPTION, 0, 0);
@ -1875,15 +1862,12 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSENTER(bxInstruction_c *i)

  BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_SYSENTER,
                      BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
-#else
-  BX_INFO(("SYSENTER: use --enable-sep to enable SYSENTER/SYSEXIT support"));
-  exception(BX_UD_EXCEPTION, 0, 0);
 #endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSEXIT(bxInstruction_c *i)
 {
-#if BX_SUPPORT_SEP
+#if BX_CPU_LEVEL >= 6
  if (real_mode() || CPL != 0) {
    BX_ERROR(("SYSEXIT from real mode or with CPL<>0 !"));
    exception(BX_GP_EXCEPTION, 0, 0);
@ -1981,9 +1965,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSEXIT(bxInstruction_c *i)

  BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_SYSEXIT,
                      BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
-#else
-  BX_INFO(("SYSEXIT: use --enable-sep to enable SYSENTER/SYSEXIT support"));
-  exception(BX_UD_EXCEPTION, 0, 0);
 #endif
 }

--- a/bochs/cpu/sse.cc
+++ b/bochs/cpu/sse.cc
--- a/bochs/cpu/sse_move.cc
+++ b/bochs/cpu/sse_move.cc
@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: sse_move.cc,v 1.108 2010-02-25 22:04:31 sshwarts Exp $
+// $Id: sse_move.cc,v 1.109 2010-02-26 11:44:50 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //   Copyright (c) 2003-2009 Stanislav Shwartsman
@ -26,6 +26,8 @@
 #include "cpu.h"
 #define LOG_THIS BX_CPU_THIS_PTR

+#if BX_CPU_LEVEL >= 6
+
 void BX_CPU_C::print_state_SSE(void)
 {
  BX_DEBUG(("MXCSR: 0x%08x\n", BX_MXCSR_REGISTER));
@ -36,6 +38,8 @@ void BX_CPU_C::print_state_SSE(void)
  }
 }

+#endif
+
 #if BX_SUPPORT_FPU
 Bit8u BX_CPU_C::pack_FPU_TW(Bit16u twd)
 {
@ -119,6 +123,7 @@ Bit16u BX_CPU_C::unpack_FPU_TW(Bit16u tag_byte)
 /* 0F AE Grp15 010 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::LDMXCSR(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
@ -128,11 +133,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::LDMXCSR(bxInstruction_c *i)
      exception(BX_GP_EXCEPTION, 0, 0);

  BX_MXCSR_REGISTER = new_mxcsr;
+#endif
 }

 /* 0F AE Grp15 011 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::STMXCSR(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  Bit32u mxcsr = BX_MXCSR_REGISTER & MXCSR_MASK;
@ -140,11 +147,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::STMXCSR(bxInstruction_c *i)
  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));

  write_virtual_dword(i->seg(), eaddr, mxcsr);
+#endif
 }

 /* 0F AE Grp15 000 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXSAVE(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  unsigned index;
  BxPackedXmmRegister xmm;

@ -242,6 +251,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXSAVE(bxInstruction_c *i)
    return; // skip saving of the XMM state
 #endif

+
  if (BX_CPU_SUPPORT_FEATURE(BX_CPU_SSE))
  {
    /* store XMM register file */
@ -256,11 +266,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXSAVE(bxInstruction_c *i)
  }

  /* do not touch reserved fields */
+#endif
 }

 /* 0F AE Grp15 001 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXRSTOR(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BxPackedXmmRegister xmm;
  unsigned index;

@ -316,6 +328,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXRSTOR(bxInstruction_c *i)
    BX_CPU_THIS_PTR the_i387.fds = xmm.xmm16u(2);
  }

+#if BX_CPU_LEVEL >= 6
  /* If the OSFXSR bit in CR4 is not set, the FXRSTOR instruction does
     not restore the states of the XMM and MXCSR registers. */
  if(BX_CPU_THIS_PTR cr4.get_OSFXSR())
@ -326,6 +339,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXRSTOR(bxInstruction_c *i)

    BX_MXCSR_REGISTER = new_mxcsr;
  }
+#endif

  /* load i387 register file */
  for(index=0; index < 8; index++)
@ -353,6 +367,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXRSTOR(bxInstruction_c *i)
    return; // skip restore of the XMM state
 #endif

+#if BX_CPU_LEVEL >= 6
  /* If the OSFXSR bit in CR4 is not set, the FXRSTOR instruction does
     not restore the states of the XMM and MXCSR registers. */
  if(BX_CPU_THIS_PTR cr4.get_OSFXSR())
@ -367,6 +382,9 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXRSTOR(bxInstruction_c *i)
      }
    }
  }
+#endif
+
+#endif
 }

 /* *************************** */
@ -380,6 +398,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXRSTOR(bxInstruction_c *i)
 /* MOVDQU: F3 0F 6F */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVUPS_VpsWpsM(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op;
@ -388,6 +407,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVUPS_VpsWpsM(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG(i->nnn(), op);
+#endif
 }

 /* MOVUPS:    0F 11 */
@ -395,10 +415,12 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVUPS_VpsWpsM(bxInstruction_c *i)
 /* MOVDQU: F3 0F 7F */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVUPS_WpsVpsM(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
  write_virtual_dqword(i->seg(), eaddr, (Bit8u *) &op);
+#endif
 }

 /* MOVAPS:    0F 28 */
@ -406,12 +428,15 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVUPS_WpsVpsM(bxInstruction_c *i)
 /* MOVDQA: F3 0F 6F */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVAPS_VpsWpsR(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BX_WRITE_XMM_REG(i->nnn(), BX_READ_XMM_REG(i->rm()));
+#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVAPS_VpsWpsM(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op;
@ -420,6 +445,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVAPS_VpsWpsM(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG(i->nnn(), op);
+#endif
 }

 /* MOVAPS:    0F 29 */
@ -427,30 +453,37 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVAPS_VpsWpsM(bxInstruction_c *i)
 /* MOVDQA: F3 0F 7F */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVAPS_WpsVpsR(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BX_WRITE_XMM_REG(i->rm(), BX_READ_XMM_REG(i->nnn()));
+#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVAPS_WpsVpsM(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
  write_virtual_dqword_aligned(i->seg(), eaddr, (Bit8u *) &op);
+#endif
 }

 /* F3 0F 10 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSS_VssWssR(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  /* If the source operand is an XMM register, the high-order
          96 bits of the destination XMM register are not modified. */
  BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), BX_READ_XMM_REG_LO_DWORD(i->rm()));
+#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSS_VssWssM(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op;
@ -464,30 +497,36 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSS_VssWssM(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG(i->nnn(), op);
+#endif
 }

 /* F3 0F 11 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSS_WssVssM(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
  write_virtual_dword(i->seg(), eaddr, BX_READ_XMM_REG_LO_DWORD(i->nnn()));
+#endif
 }

 /* F2 0F 10 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSD_VsdWsdR(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  /* If the source operand is an XMM register, the high-order
          64 bits of the destination XMM register are not modified. */
  BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), BX_READ_XMM_REG_LO_QWORD(i->rm()));
+#endif
 }

 /* MOVLPS:    0F 12 */
 /* MOVLPD: 66 0F 12 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVLPS_VpsMq(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  Bit64u val64;

@ -503,11 +542,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVLPS_VpsMq(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), val64);
+#endif
 }

 /* F2 0F 12 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVDDUP_VpdWq(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  Bit64u val64;
  BxPackedXmmRegister op;
@ -527,11 +568,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVDDUP_VpdWq(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG(i->nnn(), op);
+#endif
 }

 /* F3 0F 12 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSLDUP_VpsWps(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BxPackedXmmRegister op, result;

@ -552,11 +595,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSLDUP_VpsWps(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG(i->nnn(), result);
+#endif
 }

 /* F3 0F 16 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSHDUP_VpsWps(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BxPackedXmmRegister op, result;

@ -577,21 +622,25 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSHDUP_VpsWps(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG(i->nnn(), result);
+#endif
 }

 /* MOVLPS:    0F 13 */
 /* MOVLPD: 66 0F 13 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVLPS_MqVps(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
  write_virtual_qword(i->seg(), eaddr, BX_XMM_REG_LO_QWORD(i->nnn()));
+#endif
 }

 /* MOVHPS:    0F 16 */
 /* MOVHPD: 66 0F 16 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVHPS_VpsMq(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  Bit64u val64;

@ -607,20 +656,24 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVHPS_VpsMq(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG_HI_QWORD(i->nnn(), val64);
+#endif
 }

 /* MOVHPS:    0F 17 */
 /* MOVHPD: 66 0F 17 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVHPS_MqVps(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
  write_virtual_qword(i->seg(), eaddr, BX_XMM_REG_HI_QWORD(i->nnn()));
+#endif
 }

 /* F2 0F F0 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::LDDQU_VdqMdq(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op;
@ -629,11 +682,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::LDDQU_VdqMdq(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG(i->nnn(), op);
+#endif
 }

 /* 66 0F F7 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MASKMOVDQU_VdqUdq(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  bx_address rdi;
@ -665,11 +720,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MASKMOVDQU_VdqUdq(bxInstruction_c *i)

  /* and write result back to the memory */
  write_virtual_dqword(i->seg(), rdi, (Bit8u *) &temp);
+#endif
 }

 /* 0F 50 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVMSKPS_GdVRps(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
@ -681,11 +738,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVMSKPS_GdVRps(bxInstruction_c *i)
  if(op.xmm32u(3) & 0x80000000) val32 |= 0x8;

  BX_WRITE_32BIT_REGZ(i->rm(), val32);
+#endif
 }

 /* 66 0F 50 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVMSKPD_GdVRpd(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op = BX_READ_XMM_REG(i->nnn());
@ -695,11 +754,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVMSKPD_GdVRpd(bxInstruction_c *i)
  if(op.xmm32u(3) & 0x80000000) val32 |= 0x2;

  BX_WRITE_32BIT_REGZ(i->rm(), val32);
+#endif
 }

 /* 66 0F 6E */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_VdqEdR(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op;
@ -707,6 +768,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_VdqEdR(bxInstruction_c *i)
  op.xmm64u(1) = 0;

  BX_WRITE_XMM_REG(i->nnn(), op);
+#endif
 }

 #if BX_SUPPORT_X86_64
@ -714,6 +776,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_VdqEdR(bxInstruction_c *i)
 /* 66 0F 6E */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VdqEqR(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op;
@ -721,6 +784,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VdqEqR(bxInstruction_c *i)
  op.xmm64u(1) = 0;

  BX_WRITE_XMM_REG(i->nnn(), op);
+#endif
 }

 #endif
@ -728,15 +792,19 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VdqEqR(bxInstruction_c *i)
 /* 66 0F 7E */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_EdVdR(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BX_WRITE_32BIT_REGZ(i->rm(), BX_READ_XMM_REG_LO_DWORD(i->nnn()));
+#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_EdVdM(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
  write_virtual_dword(i->seg(), eaddr, BX_READ_XMM_REG_LO_DWORD(i->nnn()));
+#endif
 }

 #if BX_SUPPORT_X86_64
@ -744,8 +812,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVD_EdVdM(bxInstruction_c *i)
 /* 66 0F 7E */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_EqVqR(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BX_WRITE_64BIT_REG(i->rm(), BX_READ_XMM_REG_LO_QWORD(i->nnn()));
+#endif
 }

 #endif
@ -753,6 +823,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_EqVqR(bxInstruction_c *i)
 /* F3 0F 7E */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VqWqR(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op;
@ -761,10 +832,12 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VqWqR(bxInstruction_c *i)
  op.xmm64u(1) = 0; /* zero-extension to 128 bit */

  BX_WRITE_XMM_REG(i->nnn(), op);
+#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VqWqM(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op;
@ -775,29 +848,35 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VqWqM(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG(i->nnn(), op);
+#endif
 }

 /* 66 0F D6 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_WqVqR(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op;
  op.xmm64u(0) = BX_READ_XMM_REG_LO_QWORD(i->nnn());
  op.xmm64u(1) = 0; /* zero-extension to 128 bit */
  BX_WRITE_XMM_REG(i->rm(), op);
+#endif
 }

 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_WqVqM(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
  write_virtual_qword(i->seg(), eaddr, BX_READ_XMM_REG_LO_QWORD(i->nnn()));
+#endif
 }

 /* F2 0F D6 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVDQ2Q_PqVRq(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BX_CPU_THIS_PTR FPU_check_pending_exceptions(); /* check floating point status word for a pending FPU exceptions */
  BX_CPU_THIS_PTR prepareFPU2MMX();
@ -806,11 +885,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVDQ2Q_PqVRq(bxInstruction_c *i)
  MMXUQ(mm) = BX_READ_XMM_REG_LO_QWORD(i->nnn());

  BX_WRITE_MMX_REG(i->rm(), mm);
+#endif
 }

 /* F3 0F D6 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ2DQ_VdqQq(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BX_CPU_THIS_PTR FPU_check_pending_exceptions(); /* check floating point status word for a pending FPU exceptions */
  BX_CPU_THIS_PTR prepareFPU2MMX();
@ -822,11 +903,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ2DQ_VdqQq(bxInstruction_c *i)
  op.xmm64u(1) = 0;

  BX_WRITE_XMM_REG(i->rm(), op);
+#endif
 }

 /* 66 0F D7 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVMSKB_GdUdq(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op = BX_READ_XMM_REG(i->rm());
@ -851,6 +934,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVMSKB_GdUdq(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_32BIT_REGZ(i->nnn(), result);
+#endif
 }

 /* **************************** */
@ -860,8 +944,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVMSKB_GdUdq(bxInstruction_c *i)
 /* 0F C3 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVNTI_MdGd(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
  write_virtual_dword(i->seg(), eaddr, BX_READ_32BIT_REG(i->nnn()));
+#endif
 }

 #if BX_SUPPORT_X86_64
@ -869,8 +955,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVNTI_MdGd(bxInstruction_c *i)
 /* 0F C3 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVNTI_MqGq(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
  write_virtual_qword_64(i->seg(), eaddr, BX_READ_64BIT_REG(i->nnn()));
+#endif
 }

 #endif
@ -880,9 +968,11 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVNTI_MqGq(bxInstruction_c *i)
 /* MOVNTDQ: 66 0F E7 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVNTPS_MpsVps(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
  write_virtual_dqword_aligned(i->seg(), eaddr, (Bit8u *)(&BX_READ_XMM_REG(i->nnn())));
+#endif
 }

 /* ************************** */
@ -892,6 +982,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVNTPS_MpsVps(bxInstruction_c *i)
 /* 66 0F 38 20 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXBW_VdqWq(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BxPackedXmmRegister result;
  Bit64u val64;
@ -917,11 +1008,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXBW_VdqWq(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG(i->nnn(), result);
+#endif
 }

 /* 66 0F 38 21 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXBD_VdqWd(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BxPackedXmmRegister result;
  Bit32u val32;
@ -943,11 +1036,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXBD_VdqWd(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG(i->nnn(), result);
+#endif
 }

 /* 66 0F 38 22 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXBQ_VdqWw(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BxPackedXmmRegister result;
  Bit16u val16;
@ -967,11 +1062,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXBQ_VdqWw(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG(i->nnn(), result);
+#endif
 }

 /* 66 0F 38 23 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXWD_VdqWq(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BxPackedXmmRegister result;
  Bit64u val64;
@ -993,11 +1090,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXWD_VdqWq(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG(i->nnn(), result);
+#endif
 }

 /* 66 0F 38 24 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXWQ_VdqWd(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BxPackedXmmRegister result;
  Bit32u val32;
@ -1017,11 +1116,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXWQ_VdqWd(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG(i->nnn(), result);
+#endif
 }

 /* 66 0F 38 25 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXDQ_VdqWq(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BxPackedXmmRegister result;
  Bit64u val64;
@ -1041,11 +1142,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVSXDQ_VdqWq(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG(i->nnn(), result);
+#endif
 }

 /* 66 0F 38 2A */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVNTDQA_VdqMdq(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  /* source must be memory reference */
  if (i->modC0()) {
    BX_INFO(("MOVNTDQA_VdqMdq: must be memory reference"));
@ -1062,11 +1165,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVNTDQA_VdqMdq(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG(i->nnn(), op);
+#endif
 }

 /* 66 0F 38 30 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXBW_VdqWq(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BxPackedXmmRegister result;
  Bit64u val64;
@ -1092,11 +1197,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXBW_VdqWq(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG(i->nnn(), result);
+#endif
 }

 /* 66 0F 38 31 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXBD_VdqWd(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BxPackedXmmRegister result;
  Bit32u val32;
@ -1118,11 +1225,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXBD_VdqWd(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG(i->nnn(), result);
+#endif
 }

 /* 66 0F 38 32 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXBQ_VdqWw(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BxPackedXmmRegister result;
  Bit16u val16;
@ -1142,11 +1251,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXBQ_VdqWw(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG(i->nnn(), result);
+#endif
 }

 /* 66 0F 38 33 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXWD_VdqWq(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BxPackedXmmRegister result;
  Bit64u val64;
@ -1168,11 +1279,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXWD_VdqWq(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG(i->nnn(), result);
+#endif
 }

 /* 66 0F 38 34 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXWQ_VdqWd(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BxPackedXmmRegister result;
  Bit32u val32;
@ -1192,11 +1305,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXWQ_VdqWd(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG(i->nnn(), result);
+#endif
 }

 /* 66 0F 38 35 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXDQ_VdqWq(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BxPackedXmmRegister result;
  Bit64u val64;
@ -1216,11 +1331,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMOVZXDQ_VdqWq(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG(i->nnn(), result);
+#endif
 }

 /* 66 0F 3A 0F */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PALIGNR_VdqWdqIb(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
@ -1274,4 +1391,5 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PALIGNR_VdqWdqIb(bxInstruction_c *i)

  /* now write result back to destination */
  BX_WRITE_XMM_REG(i->nnn(), result);
+#endif
 }
--- a/bochs/cpu/sse_pfp.cc
+++ b/bochs/cpu/sse_pfp.cc
--- a/bochs/cpu/sse_rcp.cc
+++ b/bochs/cpu/sse_rcp.cc
@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: sse_rcp.cc,v 1.23 2010-02-25 22:04:31 sshwarts Exp $
+// $Id: sse_rcp.cc,v 1.24 2010-02-26 11:44:50 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //   Copyright (c) 2003-2009 Stanislav Shwartsman
@ -26,6 +26,8 @@
 #include "cpu.h"
 #define LOG_THIS BX_CPU_THIS_PTR

+#if BX_CPU_LEVEL >= 6
+
 #include "fpu/softfloat-specialize.h"

 BX_CPP_INLINE float32 convert_to_QNaN(float32 op)
@ -335,6 +337,8 @@ static float32 approximate_rcp(float32 op)
  return packFloat32(sign, exp, (Bit32u)(rcp_table[fraction >> 12]) << 8);
 }

+#endif
+
 /*
 * Opcode: 0F 53
 * Approximate reciprocals of packed single precision FP values from XMM2/MEM.
@ -342,6 +346,7 @@ static float32 approximate_rcp(float32 op)
 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::RCPPS_VpsWps(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BxPackedXmmRegister op;

@ -361,6 +366,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RCPPS_VpsWps(bxInstruction_c *i)
  op.xmm32u(3) = approximate_rcp(op.xmm32u(3));

  BX_WRITE_XMM_REG(i->nnn(), op);
+#endif
 }

 /*
@ -370,6 +376,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RCPPS_VpsWps(bxInstruction_c *i)
 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::RCPSS_VssWss(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  float32 op;

@ -385,8 +392,11 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RCPSS_VssWss(bxInstruction_c *i)

  op = approximate_rcp(op);
  BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), op);
+#endif
 }

+#if BX_CPU_LEVEL >= 6
+
 Bit16u rsqrt_table0[1024] =
 {
    0x34f8, 0x34e0, 0x34d0, 0x34b8, 0x34a0, 0x3488, 0x3470, 0x3460,
@ -702,6 +712,8 @@ static float32 approximate_rsqrt(float32 op)
  return packFloat32(sign, exp, (Bit32u)(rsqrt_table[fraction >> 13]) << 8);
 }

+#endif
+
 /*
 * Opcode: F3 0F 52
 * Approximate reciprocal of square root of scalar single precision FP value
@ -710,6 +722,7 @@ static float32 approximate_rsqrt(float32 op)
 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::RSQRTSS_VssWss(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  float32 op;

@ -725,6 +738,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RSQRTSS_VssWss(bxInstruction_c *i)

  op = approximate_rsqrt(op);
  BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), op);
+#endif
 }

 /*
@ -735,6 +749,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RSQRTSS_VssWss(bxInstruction_c *i)
 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::RSQRTPS_VpsWps(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();
  BxPackedXmmRegister op;

@ -754,4 +769,5 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RSQRTPS_VpsWps(bxInstruction_c *i)
  op.xmm32u(3) = approximate_rsqrt(op.xmm32u(3));

  BX_WRITE_XMM_REG(i->nnn(), op);
+#endif
 }
--- a/bochs/cpu/sse_string.cc
+++ b/bochs/cpu/sse_string.cc
@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: sse_string.cc,v 1.15 2010-02-25 22:04:31 sshwarts Exp $
+// $Id: sse_string.cc,v 1.16 2010-02-26 11:44:50 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //   Copyright (c) 2007-2009 Stanislav Shwartsman
@ -31,6 +31,8 @@
 #define RCX ECX
 #endif

+#if BX_CPU_LEVEL >= 6
+
 // Compare all pairs of Ai, Bj according to imm8 control
 static void compare_strings(Bit8u BoolRes[16][16], BxPackedXmmRegister op1, BxPackedXmmRegister op2, Bit8u imm)
 {
@ -284,9 +286,12 @@ static Bit16u aggregate(Bit8u BoolRes[16][16], unsigned len1, unsigned len2, Bit
  return result;
 }

+#endif // BX_CPU_LEVEL >= 6
+
 /* 66 0F 3A 60 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPESTRM_VdqWdqIb(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
@ -347,11 +352,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPESTRM_VdqWdqIb(bxInstruction_c *i)
  setEFlagsOSZAPC(flags);

  BX_WRITE_XMM_REG(0, result); /* store result XMM0 */
+#endif
 }

 /* 66 0F 3A 61 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPESTRI_VdqWdqIb(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;
@ -408,11 +415,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPESTRI_VdqWdqIb(bxInstruction_c *i)
  if (result2 & 0x1)
    flags |= EFlagsOFMask;
  setEFlagsOSZAPC(flags);
+#endif
 }

 /* 66 0F 3A 62 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPISTRM_VdqWdqIb(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
@ -464,11 +473,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPISTRM_VdqWdqIb(bxInstruction_c *i)
  setEFlagsOSZAPC(flags);

  BX_WRITE_XMM_REG(0, result); /* store result XMM0 */
+#endif
 }

 /* 66 0F 3A 63 */
 void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPISTRI_VdqWdqIb(bxInstruction_c *i)
 {
+#if BX_CPU_LEVEL >= 6
  BX_CPU_THIS_PTR prepareSSE();

  BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;
@ -516,4 +527,5 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPISTRI_VdqWdqIb(bxInstruction_c *i)
  if (result2 & 0x1)
    flags |= EFlagsOFMask;
  setEFlagsOSZAPC(flags);
+#endif
 }
--- a/bochs/doc/docbook/user/user.dbk
+++ b/bochs/doc/docbook/user/user.dbk
@ -1,7 +1,7 @@
 <!--
 ================================================================
 doc/docbook/user/user.dbk
-$Id: user.dbk,v 1.273 2010-02-24 20:59:49 sshwarts Exp $
+$Id: user.dbk,v 1.274 2010-02-26 11:44:50 sshwarts Exp $

 This is the top level file for the Bochs Users Manual.
 ================================================================
@ -2091,31 +2091,11 @@ turn it off.
      Add support for MMX instructions, written by Stanislav Shwartsman.
      </entry>
    </row>
-    <row>
-      <entry>--enable-sse=LEVEL</entry>
-      <entry>no</entry>
-      <entry>
-      Add support for SSE instructions, written by Stanislav Shwartsman.
-      Any of SSE/SSE2/SSE3/SSSE3/SSE4_1/SSE4_2 instruction sets are supported.
-      </entry>
-    </row>
-    <row>
-      <entry>--enable-aes</entry>
-      <entry>no</entry>
-      <entry>
-      Add support for AES instructions, written by Stanislav Shwartsman.
-      </entry>
-    </row>
    <row>
      <entry>--enable-xsave</entry>
      <entry>no</entry>
      <entry>XSAVE support</entry>
    </row>
-    <row>
-      <entry>--enable-sep</entry>
-      <entry>no</entry>
-      <entry>SYSENTER/SYSEXIT support</entry>
-    </row>
    <row>
      <entry>--enable-vmx</entry>
      <entry>no</entry>
@ -2135,16 +2115,6 @@ turn it off.
      <entry>no</entry>
      <entry>MONITOR/MWAIT instructions support (still experimental)</entry>
    </row>
-    <row>
-      <entry>--enable-movbe</entry>
-      <entry>no</entry>
-      <entry>support for MOVBE Intel Atom(R) instruction</entry>
-    </row>
-    <row>
-      <entry>--enable-popcnt</entry>
-      <entry>no</entry>
-      <entry>support for POPCNT instruction</entry>
-    </row>
    <row>
      <entry>--enable-misaligned-sse</entry>
      <entry>no</entry>
@ -8369,7 +8339,7 @@ user_shortcut: keys=ctrl-alt-del
 For installing and using Windows NT it is necessary to limit the maximum CPUID
 to 3. In the configuration file you need to add a line like this:
 <programlisting>
-cpu: cpuid_limit_winnt=1
+cpuid: cpuid_limit_winnt=1
 </programlisting>
 </para>
 </listitem>
--- a/bochs/gui/enh_dbg.cc
+++ b/bochs/gui/enh_dbg.cc
@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: enh_dbg.cc,v 1.23 2010-02-25 22:04:31 sshwarts Exp $
+// $Id: enh_dbg.cc,v 1.24 2010-02-26 11:44:50 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  BOCHS ENHANCED DEBUGGER Ver 1.2
@ -728,6 +728,7 @@ void ParseBkpt()
 // -- but it might not be "turned on", either
 int FillSSE(int LineCount)
 {
+#if BX_CPU_LEVEL >= 6
    if (! bx_cpu_support_sse)
        return (LineCount);

@ -783,7 +784,7 @@ int FillSSE(int LineCount)
        InsertListRow(cols, 3, REG_WND, LineCount, 4);  // 3 cols, group 4
        ++LineCount;
    }
-
+#endif
    return (LineCount);
 }

@ -1276,6 +1277,7 @@ void InitRegObjects()
        RegObject[j][ST7_exp] = SIM->get_param_num("FPU.st7.exp", cpu_list);
 #endif

+#if BX_CPU_LEVEL >= 6
        if (! bx_cpu_support_sse) {
            RegObject[j][XMM0_Rnum] = SIM->get_param_num("SSE.xmm00_lo", cpu_list);
            RegObject[j][XMM1_Rnum] = SIM->get_param_num("SSE.xmm01_lo", cpu_list);
@ -1313,6 +1315,7 @@ void InitRegObjects()
            RegObject[j][XMMF_hi] = SIM->get_param_num("SSE.xmm15_hi", cpu_list);
 #endif
        }
+#endif

        RegObject[j][DR0_Rnum] = SIM->get_param_num("DR0", cpu_list);
        RegObject[j][DR1_Rnum] = SIM->get_param_num("DR1", cpu_list);
--- a/bochs/gui/param_names.h
+++ b/bochs/gui/param_names.h
@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: param_names.h,v 1.2 2010-02-25 22:04:31 sshwarts Exp $
+// $Id: param_names.h,v 1.3 2010-02-26 11:44:50 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2009  The Bochs Project
@ -46,6 +46,7 @@
 #define BXPN_CPUID_SSE                   "cpuid.sse"
 #define BXPN_CPUID_AES                   "cpuid.aes"
 #define BXPN_CPUID_MOVBE                 "cpuid.movbe"
+#define BXPN_CPUID_SEP                   "cpuid.sep"
 #define BXPN_MEM_SIZE                    "memory.standard.ram.size"
 #define BXPN_HOST_MEM_SIZE               "memory.standard.ram.host_size"
 #define BXPN_ROM_PATH                    "memory.standard.rom.path"
--- a/bochs/main.cc
+++ b/bochs/main.cc
@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: main.cc,v 1.411 2010-02-25 22:04:30 sshwarts Exp $
+// $Id: main.cc,v 1.412 2010-02-26 11:44:50 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001-2009  The Bochs Project
@ -985,6 +985,7 @@ void bx_init_hardware()

  bx_bool aes_enabled = SIM->get_param_bool(BXPN_CPUID_AES)->get();
  bx_bool movbe_enabled = SIM->get_param_bool(BXPN_CPUID_MOVBE)->get();
+  bx_bool sep_enabled = SIM->get_param_bool(BXPN_CPUID_SEP)->get();

  // Output to the log file the cpu and device settings
  // This will by handy for bug reports
@ -1015,7 +1016,7 @@ void bx_init_hardware()
  BX_INFO(("  1G paging support: %s",BX_SUPPORT_1G_PAGES?"yes":"no"));
 #endif
  BX_INFO(("  x86-64 support: %s",BX_SUPPORT_X86_64?"yes":"no"));
-  BX_INFO(("  SEP support: %s",BX_SUPPORT_SEP?"yes":"no"));
+  BX_INFO(("  SEP support: %s",sep_enabled?"yes":"no"));
  BX_INFO(("  MWAIT support: %s",BX_SUPPORT_MONITOR_MWAIT?"yes":"no"));
  BX_INFO(("  XSAVE support: %s",BX_SUPPORT_XSAVE?"yes":"no"));
  BX_INFO(("  AES support: %s",aes_enabled?"yes":"no"));