code cleanup
This commit is contained in:
Stanislav Shwartsman
parent
73cc6a485d
commit
a98a917c98
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: sse_pfp.cc,v 1.55 2009-05-21 11:44:59 sshwarts Exp $
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// $Id: sse_pfp.cc,v 1.56 2009-05-28 20:18:34 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2003 Stanislav Shwartsman
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@ -112,7 +112,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PS_VpsQq(bxInstruction_c *i)
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result.xmm32u(0) = int32_to_float32(MMXUD0(op), status_word);
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result.xmm32u(1) = int32_to_float32(MMXUD1(op), status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), result.xmm64u(0));
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#else
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BX_INFO(("CVTPI2PS_VpsQq: required SSE, use --enable-sse option"));
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@ -208,7 +208,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSI2SD_VsdEd(bxInstruction_c *i)
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result = int32_to_float64(op);
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}
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), result);
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#else
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BX_INFO(("CVTSI2SD_VsdEd: required SSE2, use --enable-sse option"));
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@ -267,7 +267,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSI2SS_VssEd(bxInstruction_c *i)
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result = int32_to_float32(op, status_word);
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}
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), result);
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#else
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BX_INFO(("CVTSI2SS_VssEd: required SSE, use --enable-sse option"));
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@ -318,7 +318,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTPS2PI_PqWps(bxInstruction_c *i)
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MMXUD0(result) = float32_to_int32_round_to_zero(r0, status_word);
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MMXUD1(result) = float32_to_int32_round_to_zero(r1, status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_MMX_REG(i->nnn(), result);
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#else
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BX_INFO(("CVTTPS2PI_PqWps: required SSE, use --enable-sse option"));
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@ -366,7 +366,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTPD2PI_PqWpd(bxInstruction_c *i)
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MMXUD0(result) = float64_to_int32_round_to_zero(op.xmm64u(0), status_word);
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MMXUD1(result) = float64_to_int32_round_to_zero(op.xmm64u(1), status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_MMX_REG(i->nnn(), result);
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#else
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BX_INFO(("CVTTPD2PI_PqWpd: required SSE2, use --enable-sse option"));
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@ -406,14 +406,14 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTSD2SI_GdWsd(bxInstruction_c *i)
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if (i->os64L()) /* 64 bit operand size mode */
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{
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Bit64u result = float64_to_int64_round_to_zero(op, status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_64BIT_REG(i->nnn(), result);
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}
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else
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#endif
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{
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Bit32u result = float64_to_int32_round_to_zero(op, status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_32BIT_REGZ(i->nnn(), result);
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}
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#else
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@ -454,14 +454,14 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTSS2SI_GdWss(bxInstruction_c *i)
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if (i->os64L()) /* 64 bit operand size mode */
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{
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Bit64u result = float32_to_int64_round_to_zero(op, status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_64BIT_REG(i->nnn(), result);
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}
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else
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#endif
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{
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Bit32u result = float32_to_int32_round_to_zero(op, status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_32BIT_REGZ(i->nnn(), result);
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}
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#else
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@ -514,7 +514,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPS2PI_PqWps(bxInstruction_c *i)
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MMXUD0(result) = float32_to_int32(r0, status_word);
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MMXUD1(result) = float32_to_int32(r1, status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_MMX_REG(i->nnn(), result);
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#else
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BX_INFO(("CVTPS2PI_PqWps: required SSE, use --enable-sse option"));
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@ -563,7 +563,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPD2PI_PqWpd(bxInstruction_c *i)
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MMXUD0(result) = float64_to_int32(op.xmm64u(0), status_word);
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MMXUD1(result) = float64_to_int32(op.xmm64u(1), status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_MMX_REG(i->nnn(), result);
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#else
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BX_INFO(("CVTPD2PI_PqWpd: required SSE2, use --enable-sse option"));
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@ -603,14 +603,14 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSD2SI_GdWsd(bxInstruction_c *i)
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if (i->os64L()) /* 64 bit operand size mode */
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{
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Bit64u result = float64_to_int64(op, status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_64BIT_REG(i->nnn(), result);
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}
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else
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#endif
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{
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Bit32u result = float64_to_int32(op, status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_32BIT_REGZ(i->nnn(), result);
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}
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#else
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@ -651,14 +651,14 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSS2SI_GdWss(bxInstruction_c *i)
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if (i->os64L()) /* 64 bit operand size mode */
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{
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Bit64u result = float32_to_int64(op, status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_64BIT_REG(i->nnn(), result);
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}
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else
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#endif
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{
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Bit32u result = float32_to_int32(op, status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_32BIT_REGZ(i->nnn(), result);
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}
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#else
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@ -704,7 +704,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPS2PD_VpsWps(bxInstruction_c *i)
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result.xmm64u(0) = float32_to_float64(r0, status_word);
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result.xmm64u(1) = float32_to_float64(r1, status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_XMM_REG(i->nnn(), result);
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#else
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BX_INFO(("CVTPS2PD_VpsWps: required SSE2, use --enable-sse option"));
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@ -749,7 +749,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPD2PS_VpdWpd(bxInstruction_c *i)
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result.xmm32u(1) = float64_to_float32(op.xmm64u(1), status_word);
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result.xmm64u(1) = 0;
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_XMM_REG(i->nnn(), result);
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#else
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BX_INFO(("CVTPD2PS_VpdWpd: required SSE2, use --enable-sse option"));
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@ -786,7 +786,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSD2SS_VsdWsd(bxInstruction_c *i)
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mxcsr_to_softfloat_status_word(status_word, MXCSR);
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if (MXCSR.get_DAZ()) op = float64_denormal_to_zero(op);
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result = float64_to_float32(op, status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), result);
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#else
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BX_INFO(("CVTSD2SS_VsdWsd: required SSE2, use --enable-sse option"));
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@ -821,7 +821,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSS2SD_VssWss(bxInstruction_c *i)
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mxcsr_to_softfloat_status_word(status_word, MXCSR);
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if (MXCSR.get_DAZ()) op = float32_denormal_to_zero(op);
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result = float32_to_float64(op, status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), result);
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#else
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BX_INFO(("CVTSS2SD_VssWss: required SSE2, use --enable-sse option"));
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@ -863,7 +863,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTDQ2PS_VpsWdq(bxInstruction_c *i)
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op.xmm32u(2) = int32_to_float32(op.xmm32u(2), status_word);
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op.xmm32u(3) = int32_to_float32(op.xmm32u(3), status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_XMM_REG(i->nnn(), op);
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#else
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BX_INFO(("CVTDQ2PS_VpsWdq: required SSE2, use --enable-sse option"));
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@ -910,7 +910,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPS2DQ_VdqWps(bxInstruction_c *i)
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op.xmm32u(2) = float32_to_int32(op.xmm32u(2), status_word);
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op.xmm32u(3) = float32_to_int32(op.xmm32u(3), status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_XMM_REG(i->nnn(), op);
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#else
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BX_INFO(("CVTPS2DQ_VdqWps: required SSE2, use --enable-sse option"));
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@ -956,7 +956,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTPS2DQ_VdqWps(bxInstruction_c *i)
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op.xmm32u(2) = float32_to_int32_round_to_zero(op.xmm32u(2), status_word);
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op.xmm32u(3) = float32_to_int32_round_to_zero(op.xmm32u(3), status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_XMM_REG(i->nnn(), op);
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#else
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BX_INFO(("CVTTPS2DQ_VdqWps: required SSE2, use --enable-sse option"));
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@ -999,7 +999,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTPD2DQ_VqWpd(bxInstruction_c *i)
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result.xmm32u(1) = float64_to_int32_round_to_zero(op.xmm64u(1), status_word);
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result.xmm64u(1) = 0;
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_XMM_REG(i->nnn(), result);
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#else
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BX_INFO(("CVTTPD2DQ_VqWpd: required SSE2, use --enable-sse option"));
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@ -1043,7 +1043,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPD2DQ_VqWpd(bxInstruction_c *i)
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result.xmm32u(1) = float64_to_int32(op.xmm64u(1), status_word);
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result.xmm64u(1) = 0;
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_XMM_REG(i->nnn(), result);
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#else
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BX_INFO(("CVTPD2DQ_VqWpd: required SSE2, use --enable-sse option"));
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@ -1119,7 +1119,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::UCOMISS_VssWss(bxInstruction_c *i)
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}
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int rc = float32_compare_quiet(op1, op2, status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_CPU_THIS_PTR write_eflags_fpu_compare(rc);
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#else
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BX_INFO(("UCOMISS_VssWss: required SSE, use --enable-sse option"));
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@ -1159,7 +1159,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::UCOMISD_VsdWsd(bxInstruction_c *i)
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}
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int rc = float64_compare_quiet(op1, op2, status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_CPU_THIS_PTR write_eflags_fpu_compare(rc);
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#else
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BX_INFO(("UCOMISD_VsdWsd: required SSE2, use --enable-sse option"));
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@ -1199,7 +1199,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::COMISS_VpsWps(bxInstruction_c *i)
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}
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int rc = float32_compare(op1, op2, status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_CPU_THIS_PTR write_eflags_fpu_compare(rc);
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#else
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BX_INFO(("COMISS_VpsWps: required SSE, use --enable-sse option"));
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@ -1239,7 +1239,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::COMISD_VpdWpd(bxInstruction_c *i)
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}
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int rc = float64_compare(op1, op2, status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_CPU_THIS_PTR write_eflags_fpu_compare(rc);
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#else
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BX_INFO(("COMISD_VpdWpd: required SSE2, use --enable-sse option"));
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@ -1285,7 +1285,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SQRTPS_VpsWps(bxInstruction_c *i)
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op.xmm32u(2) = float32_sqrt(op.xmm32u(2), status_word);
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op.xmm32u(3) = float32_sqrt(op.xmm32u(3), status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_XMM_REG(i->nnn(), op);
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#else
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BX_INFO(("SQRTPS_VpsWps: required SSE, use --enable-sse option"));
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@ -1327,7 +1327,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SQRTPD_VpdWpd(bxInstruction_c *i)
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op.xmm64u(0) = float64_sqrt(op.xmm64u(0), status_word);
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op.xmm64u(1) = float64_sqrt(op.xmm64u(1), status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_XMM_REG(i->nnn(), op);
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#else
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BX_INFO(("SQRTPD_VpdWpd: required SSE2, use --enable-sse option"));
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@ -1361,7 +1361,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SQRTSD_VsdWsd(bxInstruction_c *i)
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mxcsr_to_softfloat_status_word(status_word, MXCSR);
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if (MXCSR.get_DAZ()) op = float64_denormal_to_zero(op);
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op = float64_sqrt(op, status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), op);
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#else
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BX_INFO(("SQRTSD_VsdWsd: required SSE2, use --enable-sse option"));
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@ -1395,7 +1395,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SQRTSS_VssWss(bxInstruction_c *i)
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mxcsr_to_softfloat_status_word(status_word, MXCSR);
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if (MXCSR.get_DAZ()) op = float32_denormal_to_zero(op);
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op = float32_sqrt(op, status_word);
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BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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check_exceptionsSSE(status_word.float_exception_flags);
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BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), op);
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#else
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BX_INFO(("SQRTSS_VssWss: required SSE, use --enable-sse option"));
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@ -1445,7 +1445,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADDPS_VpsWps(bxInstruction_c *i)
|
||||
op1.xmm32u(2) = float32_add(op1.xmm32u(2), op2.xmm32u(2), status_word);
|
||||
op1.xmm32u(3) = float32_add(op1.xmm32u(3), op2.xmm32u(3), status_word);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("ADDPS_VpsWps: required SSE, use --enable-sse option"));
|
||||
@ -1489,7 +1489,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADDPD_VpdWpd(bxInstruction_c *i)
|
||||
op1.xmm64u(0) = float64_add(op1.xmm64u(0), op2.xmm64u(0), status_word);
|
||||
op1.xmm64u(1) = float64_add(op1.xmm64u(1), op2.xmm64u(1), status_word);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("ADDPD_VpdWpd: required SSE2, use --enable-sse option"));
|
||||
@ -1529,7 +1529,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADDSD_VsdWsd(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
op1 = float64_add(op1, op2, status_word);
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("ADDSD_VsdWsd: required SSE2, use --enable-sse option"));
|
||||
@ -1569,7 +1569,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADDSS_VssWss(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
op1 = float32_add(op1, op2, status_word);
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("ADDSS_VssWss: required SSE, use --enable-sse option"));
|
||||
@ -1619,7 +1619,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MULPS_VpsWps(bxInstruction_c *i)
|
||||
op1.xmm32u(2) = float32_mul(op1.xmm32u(2), op2.xmm32u(2), status_word);
|
||||
op1.xmm32u(3) = float32_mul(op1.xmm32u(3), op2.xmm32u(3), status_word);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("MULPS_VpsWps: required SSE, use --enable-sse option"));
|
||||
@ -1663,7 +1663,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MULPD_VpdWpd(bxInstruction_c *i)
|
||||
op1.xmm64u(0) = float64_mul(op1.xmm64u(0), op2.xmm64u(0), status_word);
|
||||
op1.xmm64u(1) = float64_mul(op1.xmm64u(1), op2.xmm64u(1), status_word);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("MULPD_VpdWpd: required SSE2, use --enable-sse option"));
|
||||
@ -1703,7 +1703,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MULSD_VsdWsd(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
op1 = float64_mul(op1, op2, status_word);
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("MULSD_VsdWsd: required SSE2, use --enable-sse option"));
|
||||
@ -1743,7 +1743,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MULSS_VssWss(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
op1 = float32_mul(op1, op2, status_word);
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("MULSS_VssWss: required SSE, use --enable-sse option"));
|
||||
@ -1793,7 +1793,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SUBPS_VpsWps(bxInstruction_c *i)
|
||||
op1.xmm32u(2) = float32_sub(op1.xmm32u(2), op2.xmm32u(2), status_word);
|
||||
op1.xmm32u(3) = float32_sub(op1.xmm32u(3), op2.xmm32u(3), status_word);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("SUBPS_VpsWps: required SSE, use --enable-sse option"));
|
||||
@ -1837,7 +1837,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SUBPD_VpdWpd(bxInstruction_c *i)
|
||||
op1.xmm64u(0) = float64_sub(op1.xmm64u(0), op2.xmm64u(0), status_word);
|
||||
op1.xmm64u(1) = float64_sub(op1.xmm64u(1), op2.xmm64u(1), status_word);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("SUBPD_VpdWpd: required SSE2, use --enable-sse option"));
|
||||
@ -1877,7 +1877,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SUBSD_VsdWsd(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
op1 = float64_sub(op1, op2, status_word);
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("SUBSD_VsdWsd: required SSE2, use --enable-sse option"));
|
||||
@ -1917,7 +1917,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SUBSS_VssWss(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
op1 = float32_sub(op1, op2, status_word);
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("SUBSS_VssWss: required SSE, use --enable-sse option"));
|
||||
@ -1972,7 +1972,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MINPS_VpsWps(bxInstruction_c *i)
|
||||
rc = float32_compare(op1.xmm32u(3), op2.xmm32u(3), status_word);
|
||||
op1.xmm32u(3) = (rc == float_relation_less) ? op1.xmm32u(3) : op2.xmm32u(3);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("MINPS_VpsWps: required SSE, use --enable-sse option"));
|
||||
@ -2019,7 +2019,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MINPD_VpdWpd(bxInstruction_c *i)
|
||||
rc = float64_compare(op1.xmm64u(1), op2.xmm64u(1), status_word);
|
||||
op1.xmm64u(1) = (rc == float_relation_less) ? op1.xmm64u(1) : op2.xmm64u(1);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("MINPD_VpdWpd: required SSE2, use --enable-sse option"));
|
||||
@ -2059,7 +2059,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MINSD_VsdWsd(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
int rc = float64_compare(op1, op2, status_word);
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(),
|
||||
(rc == float_relation_less) ? op1 : op2);
|
||||
#else
|
||||
@ -2100,7 +2100,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MINSS_VssWss(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
int rc = float32_compare(op1, op2, status_word);
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG_LO_DWORD(i->nnn(),
|
||||
(rc == float_relation_less) ? op1 : op2);
|
||||
#else
|
||||
@ -2151,7 +2151,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::DIVPS_VpsWps(bxInstruction_c *i)
|
||||
op1.xmm32u(2) = float32_div(op1.xmm32u(2), op2.xmm32u(2), status_word);
|
||||
op1.xmm32u(3) = float32_div(op1.xmm32u(3), op2.xmm32u(3), status_word);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("DIVPS_VpsWps: required SSE, use --enable-sse option"));
|
||||
@ -2195,7 +2195,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::DIVPD_VpdWpd(bxInstruction_c *i)
|
||||
op1.xmm64u(0) = float64_div(op1.xmm64u(0), op2.xmm64u(0), status_word);
|
||||
op1.xmm64u(1) = float64_div(op1.xmm64u(1), op2.xmm64u(1), status_word);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("DIVPD_VpdWpd: required SSE2, use --enable-sse option"));
|
||||
@ -2235,7 +2235,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::DIVSD_VsdWsd(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
op1 = float64_div(op1, op2, status_word);
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("DIVSD_VsdWsd: required SSE2, use --enable-sse option"));
|
||||
@ -2275,7 +2275,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::DIVSS_VssWss(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
op1 = float32_div(op1, op2, status_word);
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("DIVSS_VssWss: required SSE, use --enable-sse option"));
|
||||
@ -2330,7 +2330,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MAXPS_VpsWps(bxInstruction_c *i)
|
||||
rc = float32_compare(op1.xmm32u(3), op2.xmm32u(3), status_word);
|
||||
op1.xmm32u(3) = (rc == float_relation_greater) ? op1.xmm32u(3) : op2.xmm32u(3);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("MAXPS_VpsWps: required SSE, use --enable-sse option"));
|
||||
@ -2377,7 +2377,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MAXPD_VpdWpd(bxInstruction_c *i)
|
||||
rc = float64_compare(op1.xmm64u(1), op2.xmm64u(1), status_word);
|
||||
op1.xmm64u(1) = (rc == float_relation_greater) ? op1.xmm64u(1) : op2.xmm64u(1);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("MAXPD_VpdWpd: required SSE2, use --enable-sse option"));
|
||||
@ -2417,7 +2417,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MAXSD_VsdWsd(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
int rc = float64_compare(op1, op2, status_word);
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(),
|
||||
(rc == float_relation_greater) ? op1 : op2);
|
||||
#else
|
||||
@ -2458,7 +2458,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MAXSS_VssWss(bxInstruction_c *i)
|
||||
}
|
||||
|
||||
int rc = float32_compare(op1, op2, status_word);
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG_LO_DWORD(i->nnn(),
|
||||
(rc == float_relation_greater) ? op1 : op2);
|
||||
#else
|
||||
@ -2503,7 +2503,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::HADDPD_VpdWpd(bxInstruction_c *i)
|
||||
op1.xmm64u(0) = float64_add(op1.xmm64u(0), op1.xmm64u(1), status_word);
|
||||
op1.xmm64u(1) = float64_add(op2.xmm64u(0), op2.xmm64u(1), status_word);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("HADDPD_VpdWpd: required SSE3, use --enable-sse option"));
|
||||
@ -2553,7 +2553,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::HADDPS_VpsWps(bxInstruction_c *i)
|
||||
op1.xmm32u(2) = float32_add(op2.xmm32u(0), op2.xmm32u(1), status_word);
|
||||
op1.xmm32u(3) = float32_add(op2.xmm32u(2), op2.xmm32u(3), status_word);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("HADDPS_VpsWps: required SSE3, use --enable-sse option"));
|
||||
@ -2597,7 +2597,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::HSUBPD_VpdWpd(bxInstruction_c *i)
|
||||
op1.xmm64u(0) = float64_sub(op1.xmm64u(0), op1.xmm64u(1), status_word);
|
||||
op1.xmm64u(1) = float64_sub(op2.xmm64u(0), op2.xmm64u(1), status_word);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("HSUBPD_VpdWpd: required SSE3, use --enable-sse option"));
|
||||
@ -2647,7 +2647,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::HSUBPS_VpsWps(bxInstruction_c *i)
|
||||
op1.xmm32u(2) = float32_sub(op2.xmm32u(0), op2.xmm32u(1), status_word);
|
||||
op1.xmm32u(3) = float32_sub(op2.xmm32u(2), op2.xmm32u(3), status_word);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("HSUBPS_VpsWps: required SSE3, use --enable-sse option"));
|
||||
@ -2724,7 +2724,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPPS_VpsWpsIb(bxInstruction_c *i)
|
||||
compare32[ib](op1.xmm32u(3), op2.xmm32u(3), status) ? 0 : 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status.float_exception_flags);
|
||||
check_exceptionsSSE(status.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("CMPPS_VpsWpsIb: required SSE, use --enable-sse option"));
|
||||
@ -2789,7 +2789,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPPD_VpdWpdIb(bxInstruction_c *i)
|
||||
0 : BX_CONST64(0xFFFFFFFFFFFFFFFF);
|
||||
}
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status.float_exception_flags);
|
||||
check_exceptionsSSE(status.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("CMPPD_VpdWpdIb: required SSE2, use --enable-sse option"));
|
||||
@ -2849,7 +2849,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPSD_VsdWsdIb(bxInstruction_c *i)
|
||||
}
|
||||
}
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), result);
|
||||
#else
|
||||
BX_INFO(("CMPSD_VsdWsdIb: required SSE2, use --enable-sse option"));
|
||||
@ -2909,7 +2909,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPSS_VssWssIb(bxInstruction_c *i)
|
||||
}
|
||||
}
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
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||||
BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), result);
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||||
#else
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||||
BX_INFO(("CMPSS_VssWssIb: required SSE, use --enable-sse option"));
|
||||
@ -2953,7 +2953,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADDSUBPD_VpdWpd(bxInstruction_c *i)
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||||
op1.xmm64u(0) = float64_sub(op1.xmm64u(0), op2.xmm64u(0), status_word);
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op1.xmm64u(1) = float64_add(op1.xmm64u(1), op2.xmm64u(1), status_word);
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||||
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||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
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||||
check_exceptionsSSE(status_word.float_exception_flags);
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||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("ADDSUBPD_VpdWpd: required SSE3, use --enable-sse option"));
|
||||
@ -3003,7 +3003,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ADDSUBPS_VpsWps(bxInstruction_c *i)
|
||||
op1.xmm32u(2) = float32_sub(op1.xmm32u(2), op2.xmm32u(2), status_word);
|
||||
op1.xmm32u(3) = float32_add(op1.xmm32u(3), op2.xmm32u(3), status_word);
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("ADDSUBPS_VpsWps: required SSE3, use --enable-sse option"));
|
||||
@ -3056,7 +3056,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ROUNDPS_VpsWpsIb(bxInstruction_c *i)
|
||||
if (control & 0x8)
|
||||
status_word.float_exception_flags &= ~float_flag_inexact;
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op);
|
||||
#else
|
||||
BX_INFO(("ROUNDPS_VpsWpsIb: required SSE4, use --enable-sse option"));
|
||||
@ -3102,7 +3102,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ROUNDPD_VpdWpdIb(bxInstruction_c *i)
|
||||
if (control & 0x8)
|
||||
status_word.float_exception_flags &= ~float_flag_inexact;
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op);
|
||||
#else
|
||||
BX_INFO(("ROUNDPD_VpdWpdIb: required SSE4, use --enable-sse option"));
|
||||
@ -3144,7 +3144,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ROUNDSS_VssWssIb(bxInstruction_c *i)
|
||||
if (control & 0x8)
|
||||
status_word.float_exception_flags &= ~float_flag_inexact;
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), op);
|
||||
#else
|
||||
BX_INFO(("ROUNDSS_VssWssIb: required SSE4, use --enable-sse option"));
|
||||
@ -3186,7 +3186,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::ROUNDSD_VsdWsdIb(bxInstruction_c *i)
|
||||
if (control & 0x8)
|
||||
status_word.float_exception_flags &= ~float_flag_inexact;
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG_LO_QWORD(i->nnn(), op);
|
||||
#else
|
||||
BX_INFO(("ROUNDSD_VsdWsdIb: required SSE4, use --enable-sse option"));
|
||||
@ -3254,7 +3254,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::DPPS_VpsWpsIb(bxInstruction_c *i)
|
||||
if (mask & 0x04) op1.xmm32u(2) = r;
|
||||
if (mask & 0x08) op1.xmm32u(3) = r;
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("DPPS_VpsWpsIb: required SSE4, use --enable-sse option"));
|
||||
@ -3310,7 +3310,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::DPPD_VpdWpdIb(bxInstruction_c *i)
|
||||
if (mask & 0x01) op1.xmm64u(0) = result;
|
||||
if (mask & 0x02) op1.xmm64u(1) = result;
|
||||
|
||||
BX_CPU_THIS_PTR check_exceptionsSSE(status_word.float_exception_flags);
|
||||
check_exceptionsSSE(status_word.float_exception_flags);
|
||||
BX_WRITE_XMM_REG(i->nnn(), op1);
|
||||
#else
|
||||
BX_INFO(("DPPD_VpdWpdIb: required SSE4, use --enable-sse option"));
|
||||
|
||||
Loading…
Reference in New Issue
Block a user