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bugfixes, comment fixes, compilation fix in VMX

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This commit is contained in:
Stanislav Shwartsman 2009-06-20 20:39:51 +00:00
parent 712e5a6f18
commit cfa3611a5f
7 changed files with 49 additions and 44 deletions
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16
bochs/cpu/shift16.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: shift16.cc,v 1.49 2009-06-20 09:10:48 sshwarts Exp $
// $Id: shift16.cc,v 1.50 2009-06-20 20:39:51 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -69,7 +69,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EwGwM(bxInstruction_c *i)
write_RMW_virtual_word(result_16);
SET_FLAGS_OSZAPC_LOGIC_16(result_16); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_16(result_16);
cf = (temp_32 >> (32 - count)) & 0x1;
of = cf ^ (result_16 >> 15); // of = cf ^ result15
@ -111,7 +111,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EwGwR(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->rm(), result_16);
SET_FLAGS_OSZAPC_LOGIC_16(result_16); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_16(result_16);
cf = (temp_32 >> (32 - count)) & 0x1;
of = cf ^ (result_16 >> 15); // of = cf ^ result15
@ -156,7 +156,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EwGwM(bxInstruction_c *i)
write_RMW_virtual_word(result_16);
SET_FLAGS_OSZAPC_LOGIC_16(result_16); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_16(result_16);
cf = (op1_16 >> (count - 1)) & 0x1;
of = (((result_16 << 1) ^ result_16) >> 15) & 0x1; // of = result14 ^ result15
@ -197,7 +197,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EwGwR(bxInstruction_c *i)
BX_WRITE_16BIT_REG(i->rm(), result_16);
SET_FLAGS_OSZAPC_LOGIC_16(result_16); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_16(result_16);
cf = (op1_16 >> (count - 1)) & 0x1;
of = (((result_16 << 1) ^ result_16) >> 15) & 0x1; // of = result14 ^ result15
@ -434,7 +434,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHL_Ew(bxInstruction_c *i)
write_RMW_virtual_word(result_16);
}
SET_FLAGS_OSZAPC_LOGIC_16(result_16); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_16(result_16);
SET_FLAGS_OxxxxC(of, cf);
}
@ -478,7 +478,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHR_Ew(bxInstruction_c *i)
// of == 0 if count >= 2
of = ((result_16 << 1) ^ result_16) >> 15;
SET_FLAGS_OSZAPC_LOGIC_16(result_16); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_16(result_16);
SET_FLAGS_OxxxxC(of, cf);
}
@ -527,7 +527,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SAR_Ew(bxInstruction_c *i)
cf = (result_16 & 0x1);
}
SET_FLAGS_OSZAPC_LOGIC_16(result_16); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_16(result_16);
/* signed overflow cannot happen in SAR instruction */
SET_FLAGS_OxxxxC(0, cf);

22
bochs/cpu/shift32.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: shift32.cc,v 1.48 2009-01-16 18:18:58 sshwarts Exp $
// $Id: shift32.cc,v 1.49 2009-06-20 20:39:51 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -55,7 +55,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EdGdM(bxInstruction_c *i)
write_RMW_virtual_dword(result_32);
SET_FLAGS_OSZAPC_LOGIC_32(result_32); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
cf = (op1_32 >> (32 - count)) & 0x1;
of = cf ^ (result_32 >> 31); // of = cf ^ result31
@ -83,7 +83,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EdGdR(bxInstruction_c *i)
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
SET_FLAGS_OSZAPC_LOGIC_32(result_32); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
cf = (op1_32 >> (32 - count)) & 0x1;
of = cf ^ (result_32 >> 31); // of = cf ^ result31
@ -115,7 +115,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EdGdM(bxInstruction_c *i)
write_RMW_virtual_dword(result_32);
SET_FLAGS_OSZAPC_LOGIC_32(result_32); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
cf = (op1_32 >> (count - 1)) & 0x1;
of = ((result_32 << 1) ^ result_32) >> 31; // of = result30 ^ result31
@ -143,7 +143,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EdGdR(bxInstruction_c *i)
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
SET_FLAGS_OSZAPC_LOGIC_32(result_32); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
cf = (op1_32 >> (count - 1)) & 0x1;
of = ((result_32 << 1) ^ result_32) >> 31; // of = result30 ^ result31
@ -411,7 +411,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHL_EdM(bxInstruction_c *i)
cf = (op1_32 >> (32 - count)) & 0x1;
of = cf ^ (result_32 >> 31);
SET_FLAGS_OSZAPC_LOGIC_32(result_32); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
SET_FLAGS_OxxxxC(of, cf);
}
@ -438,7 +438,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHL_EdR(bxInstruction_c *i)
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
SET_FLAGS_OSZAPC_LOGIC_32(result_32); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
SET_FLAGS_OxxxxC(of, cf);
}
@ -470,7 +470,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHR_EdM(bxInstruction_c *i)
// of == 0 if count >= 2
of = ((result_32 << 1) ^ result_32) >> 31;
SET_FLAGS_OSZAPC_LOGIC_32(result_32); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
SET_FLAGS_OxxxxC(of, cf);
}
@ -497,7 +497,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHR_EdR(bxInstruction_c *i)
// of == 0 if count >= 2
of = ((result_32 << 1) ^ result_32) >> 31;
SET_FLAGS_OSZAPC_LOGIC_32(result_32); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
SET_FLAGS_OxxxxC(of, cf);
}
@ -529,7 +529,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SAR_EdM(bxInstruction_c *i)
write_RMW_virtual_dword(result_32);
SET_FLAGS_OSZAPC_LOGIC_32(result_32); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
set_CF((op1_32 >> (count - 1)) & 1);
clear_OF(); /* signed overflow cannot happen in SAR instruction */
}
@ -559,7 +559,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SAR_EdR(bxInstruction_c *i)
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
SET_FLAGS_OSZAPC_LOGIC_32(result_32); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_32(result_32);
set_CF((op1_32 >> (count - 1)) & 1);
clear_OF(); /* signed overflow cannot happen in SAR instruction */
}

22
bochs/cpu/shift64.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: shift64.cc,v 1.39 2009-01-16 18:18:58 sshwarts Exp $
// $Id: shift64.cc,v 1.40 2009-06-20 20:39:51 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -57,7 +57,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EqGqM(bxInstruction_c *i)
write_RMW_virtual_qword(result_64);
SET_FLAGS_OSZAPC_LOGIC_64(result_64); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
cf = (op1_64 >> (64 - count)) & 0x1;
of = cf ^ (result_64 >> 63); // of = cf ^ result63
@ -85,7 +85,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EqGqR(bxInstruction_c *i)
BX_WRITE_64BIT_REG(i->rm(), result_64);
SET_FLAGS_OSZAPC_LOGIC_64(result_64); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
cf = (op1_64 >> (64 - count)) & 0x1;
of = cf ^ (result_64 >> 63); // of = cf ^ result63
@ -117,7 +117,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EqGqM(bxInstruction_c *i)
write_RMW_virtual_qword(result_64);
SET_FLAGS_OSZAPC_LOGIC_64(result_64); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
cf = (op1_64 >> (count - 1)) & 0x1;
of = ((result_64 << 1) ^ result_64) >> 63; // of = result62 ^ result63
@ -145,7 +145,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EqGqR(bxInstruction_c *i)
BX_WRITE_64BIT_REG(i->rm(), result_64);
SET_FLAGS_OSZAPC_LOGIC_64(result_64); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
cf = (op1_64 >> (count - 1)) & 0x1;
of = ((result_64 << 1) ^ result_64) >> 63; // of = result62 ^ result63
@ -414,7 +414,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHL_EqM(bxInstruction_c *i)
write_RMW_virtual_qword(result_64);
SET_FLAGS_OSZAPC_LOGIC_64(result_64); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
SET_FLAGS_OxxxxC(of, cf);
}
@ -439,7 +439,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHL_EqR(bxInstruction_c *i)
cf = (op1_64 >> (64 - count)) & 0x1;
of = cf ^ (result_64 >> 63);
SET_FLAGS_OSZAPC_LOGIC_64(result_64); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
SET_FLAGS_OxxxxC(of, cf);
}
@ -471,7 +471,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHR_EqM(bxInstruction_c *i)
// of == 0 if count >= 2
of = ((result_64 << 1) ^ result_64) >> 63;
SET_FLAGS_OSZAPC_LOGIC_64(result_64); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
SET_FLAGS_OxxxxC(of, cf);
}
@ -498,7 +498,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHR_EqR(bxInstruction_c *i)
// of == 0 if count >= 2
of = ((result_64 << 1) ^ result_64) >> 63;
SET_FLAGS_OSZAPC_LOGIC_64(result_64); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
SET_FLAGS_OxxxxC(of, cf);
}
@ -530,7 +530,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SAR_EqM(bxInstruction_c *i)
write_RMW_virtual_qword(result_64);
SET_FLAGS_OSZAPC_LOGIC_64(result_64); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
set_CF((op1_64 >> (count - 1)) & 1);
clear_OF(); /* signed overflow cannot happen in SAR instruction */
}
@ -560,7 +560,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SAR_EqR(bxInstruction_c *i)
BX_WRITE_64BIT_REG(i->rm(), result_64);
SET_FLAGS_OSZAPC_LOGIC_64(result_64); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
set_CF((op1_64 >> (count - 1)) & 1);
clear_OF(); /* signed overflow cannot happen in SAR instruction */
}

10
bochs/cpu/shift8.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: shift8.cc,v 1.40 2009-06-20 09:10:48 sshwarts Exp $
// $Id: shift8.cc,v 1.41 2009-06-20 20:39:51 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -264,7 +264,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHL_Eb(bxInstruction_c *i)
write_RMW_virtual_byte(result_8);
}
SET_FLAGS_OSZAPC_LOGIC_8(result_8); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_8(result_8);
SET_FLAGS_OxxxxC(of, cf);
}
@ -306,9 +306,9 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHR_Eb(bxInstruction_c *i)
cf = (op1_8 >> (count - 1)) & 0x1;
// note, that of == result7 if count == 1 and
// of == 0 if count >= 2
of = ((result_8 << 1) ^ result_8) >> 7;
of = (((result_8 << 1) ^ result_8) >> 7) & 0x1;
SET_FLAGS_OSZAPC_LOGIC_8(result_8); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_8(result_8);
SET_FLAGS_OxxxxC(of, cf);
}
@ -357,7 +357,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::SAR_Eb(bxInstruction_c *i)
cf = (result_8 & 0x1);
}
SET_FLAGS_OSZAPC_LOGIC_8(result_8); /* handle SF, ZF and AF flags */
SET_FLAGS_OSZAPC_LOGIC_8(result_8);
/* signed overflow cannot happen in SAR instruction */
SET_FLAGS_OxxxxC(0, cf);

4
bochs/cpu/sse_pfp.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: sse_pfp.cc,v 1.57 2009-06-05 17:48:55 sshwarts Exp $
// $Id: sse_pfp.cc,v 1.58 2009-06-20 20:39:51 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003 Stanislav Shwartsman
@ -32,7 +32,7 @@
void BX_CPU_C::check_exceptionsSSE(int exceptions_flags)
{
exceptions_flags &= 0x3F;
exceptions_flags &= MXCSR_EXCEPTIONS;
int unmasked = ~(MXCSR.get_exceptions_masks()) & exceptions_flags;
MXCSR.set_exceptions(exceptions_flags);

6
bochs/cpu/vmx.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: vmx.cc,v 1.22 2009-06-15 15:10:05 sshwarts Exp $
// $Id: vmx.cc,v 1.23 2009-06-20 20:39:51 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2009 Stanislav Shwartsman
@ -1306,7 +1306,9 @@ Bit32u BX_CPU_C::VMenterLoadCheckGuestState(Bit64u *qualification)
#endif
invalidate_prefetch_q();
#if BX_SUPPORT_ALIGNMENT_CHECK
handleAlignmentCheck();
#endif
handleCpuModeChange();
return VMXERR_NO_ERROR;
@ -1653,7 +1655,9 @@ void BX_CPU_C::VMexitLoadHostState(void)
#endif
invalidate_prefetch_q();
#if BX_SUPPORT_ALIGNMENT_CHECK
handleAlignmentCheck();
#endif
handleCpuModeChange();
}

13
bochs/fpu/softfloat-round-pack.cc
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@ -543,18 +543,19 @@ floatx80 SoftFloatRoundAndPackFloatx80(int roundingPrecision,
floatx80 roundAndPackFloatx80(int roundingPrecision,
int zSign, Bit32s zExp, Bit64u zSig0, Bit64u zSig1, float_status_t &status)
{
float_status_t round_status = status;
floatx80 result = SoftFloatRoundAndPackFloatx80(roundingPrecision, zSign, zExp, zSig0, zSig1, status);
// bias unmasked undeflow
if (! (status.float_exception_masks & float_flag_underflow)) {
if (status.float_exception_flags & float_flag_underflow)
return SoftFloatRoundAndPackFloatx80(roundingPrecision, zSign, zExp + 0x6000, zSig0, zSig1, status);
if (status.float_exception_flags & ~status.float_exception_masks & float_flag_underflow) {
float_raise(round_status, float_flag_underflow);
return SoftFloatRoundAndPackFloatx80(roundingPrecision, zSign, zExp + 0x6000, zSig0, zSig1, status = round_status);
}
// bias unmasked overflow
if (! (status.float_exception_masks & float_flag_overflow)) {
if (status.float_exception_flags & float_flag_overflow)
return SoftFloatRoundAndPackFloatx80(roundingPrecision, zSign, zExp - 0x6000, zSig0, zSig1, status);
if (status.float_exception_flags & ~status.float_exception_masks & float_flag_overflow) {
float_raise(round_status, float_flag_overflow);
return SoftFloatRoundAndPackFloatx80(roundingPrecision, zSign, zExp - 0x6000, zSig0, zSig1, status = round_status);
}
return result;