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another way to implement this op

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This commit is contained in:
Stanislav Shwartsman 2010-12-26 20:54:23 +00:00
parent 25b1e2e58d
commit fd5558d4be
3 changed files with 4 additions and 22 deletions
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3
bochs/cpu/cpu.h
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.699 2010-12-26 20:41:47 sshwarts Exp $
// $Id: cpu.h,v 1.700 2010-12-26 20:54:23 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001-2011 The Bochs Project
@ -2086,7 +2086,6 @@ public: // for now...
/* SSE2 */
BX_SMF void MOVSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void CVTPI2PD_VpdQqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void CVTPI2PD_VpdQqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void CVTSI2SD_VsdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void CVTSI2SD_VsdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF void CVTTPD2PI_PqWpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);

4
bochs/cpu/ia_opcodes.h
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: ia_opcodes.h,v 1.58 2010-12-26 20:41:47 sshwarts Exp $
// $Id: ia_opcodes.h,v 1.59 2010-12-26 20:54:23 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2008-2011 Stanislav Shwartsman
@ -1077,7 +1077,7 @@ bx_define_opcode(BX_IA_MOVSD_VsdWsdR, &BX_CPU_C::MOVSD_VsdWsdR, NULL, BX_CPU_SSE
bx_define_opcode(BX_IA_MOVSD_VsdWsdM, &BX_CPU_C::MOVQ_VqWqM, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVSD_WsdVsdM, &BX_CPU_C::MOVQ_WqVqM, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_CVTPI2PD_VpdQqR, &BX_CPU_C::CVTPI2PD_VpdQqR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_CVTPI2PD_VpdQqM, &BX_CPU_C::CVTPI2PD_VpdQqM, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_CVTPI2PD_VpdQqM, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTDQ2PD_VpdWqR, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_CVTSI2SD_VsdEdR, &BX_CPU_C::CVTSI2SD_VsdEdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_CVTSI2SD_VsdEdM, &BX_CPU_C::CVTSI2SD_VsdEdM, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_CVTTPD2PI_PqWpd, &BX_CPU_C::CVTTPD2PI_PqWpd, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)

19
bochs/cpu/sse_pfp.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: sse_pfp.cc,v 1.72 2010-12-26 20:41:47 sshwarts Exp $
// $Id: sse_pfp.cc,v 1.73 2010-12-26 20:54:23 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2003-2010 Stanislav Shwartsman
@ -146,23 +146,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PD_VpdQqR(bxInstruction_c *i)
#endif
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PD_VpdQqM(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BxPackedMmxRegister op;
BxPackedXmmRegister result;
// do not cause transition to MMX state if no MMX register touched
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
MMXUQ(op) = read_virtual_qword(i->seg(), eaddr);
result.xmm64u(0) = int32_to_float64(MMXUD0(op));
result.xmm64u(1) = int32_to_float64(MMXUD1(op));
BX_WRITE_XMM_REG(i->nnn(), result);
#endif
}
/*
* Opcode: F2 0F 2A
* Convert one 32bit signed integer to one double precision FP