From fd5558d4be1e89e03ed01ad23b9db43e9fc03f4e Mon Sep 17 00:00:00 2001
From: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
Date: Sun, 26 Dec 2010 20:54:23 +0000
Subject: [PATCH] another way to implement this op

---
 bochs/cpu/cpu.h        |  3 +--
 bochs/cpu/ia_opcodes.h |  4 ++--
 bochs/cpu/sse_pfp.cc   | 19 +------------------
 3 files changed, 4 insertions(+), 22 deletions(-)

diff --git a/bochs/cpu/cpu.h b/bochs/cpu/cpu.h
index 3a677e8c0..ef17bdc0d 100644
--- a/bochs/cpu/cpu.h
+++ b/bochs/cpu/cpu.h
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: cpu.h,v 1.699 2010-12-26 20:41:47 sshwarts Exp $
+// $Id: cpu.h,v 1.700 2010-12-26 20:54:23 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001-2011  The Bochs Project
@@ -2086,7 +2086,6 @@ public: // for now...
   /* SSE2 */
   BX_SMF void MOVSD_VsdWsdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
   BX_SMF void CVTPI2PD_VpdQqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
-  BX_SMF void CVTPI2PD_VpdQqM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
   BX_SMF void CVTSI2SD_VsdEdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
   BX_SMF void CVTSI2SD_VsdEdM(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
   BX_SMF void CVTTPD2PI_PqWpd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
diff --git a/bochs/cpu/ia_opcodes.h b/bochs/cpu/ia_opcodes.h
index 10145736d..1954ab1f6 100644
--- a/bochs/cpu/ia_opcodes.h
+++ b/bochs/cpu/ia_opcodes.h
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: ia_opcodes.h,v 1.58 2010-12-26 20:41:47 sshwarts Exp $
+// $Id: ia_opcodes.h,v 1.59 2010-12-26 20:54:23 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //   Copyright (c) 2008-2011 Stanislav Shwartsman
@@ -1077,7 +1077,7 @@ bx_define_opcode(BX_IA_MOVSD_VsdWsdR, &BX_CPU_C::MOVSD_VsdWsdR, NULL, BX_CPU_SSE
 bx_define_opcode(BX_IA_MOVSD_VsdWsdM, &BX_CPU_C::MOVQ_VqWqM, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_MOVSD_WsdVsdM, &BX_CPU_C::MOVQ_WqVqM, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_CVTPI2PD_VpdQqR, &BX_CPU_C::CVTPI2PD_VpdQqR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CVTPI2PD_VpdQqM, &BX_CPU_C::CVTPI2PD_VpdQqM, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CVTPI2PD_VpdQqM, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTDQ2PD_VpdWqR, BX_CPU_SSE2, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_CVTSI2SD_VsdEdR, &BX_CPU_C::CVTSI2SD_VsdEdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_CVTSI2SD_VsdEdM, &BX_CPU_C::CVTSI2SD_VsdEdM, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
 bx_define_opcode(BX_IA_CVTTPD2PI_PqWpd, &BX_CPU_C::CVTTPD2PI_PqWpd, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
diff --git a/bochs/cpu/sse_pfp.cc b/bochs/cpu/sse_pfp.cc
index 106f9194d..edaee7dc6 100644
--- a/bochs/cpu/sse_pfp.cc
+++ b/bochs/cpu/sse_pfp.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: sse_pfp.cc,v 1.72 2010-12-26 20:41:47 sshwarts Exp $
+// $Id: sse_pfp.cc,v 1.73 2010-12-26 20:54:23 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //   Copyright (c) 2003-2010 Stanislav Shwartsman
@@ -146,23 +146,6 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PD_VpdQqR(bxInstruction_c *i)
 #endif
 }
 
-void BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PD_VpdQqM(bxInstruction_c *i)
-{
-#if BX_CPU_LEVEL >= 6
-  BxPackedMmxRegister op;
-  BxPackedXmmRegister result;
-
-  // do not cause transition to MMX state if no MMX register touched
-  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
-  MMXUQ(op) = read_virtual_qword(i->seg(), eaddr);
-
-  result.xmm64u(0) = int32_to_float64(MMXUD0(op));
-  result.xmm64u(1) = int32_to_float64(MMXUD1(op));
-
-  BX_WRITE_XMM_REG(i->nnn(), result);
-#endif
-}
-
 /*
  * Opcode: F2 0F 2A
  * Convert one 32bit signed integer to one double precision FP