Stanislav Shwartsman
44241a1e56
- Added support for AVX and AVX2 instructions emulation, to enable configure
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with --enable-avx option. When compiled in, AVX still has to be enabled
using .bochsrc CPUID option. AVX2 FMA instructions still not implemented.
- Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
instructions support can be enabled using .bochsrc CPUID option.
2011-08-27 13:47:16 +00:00
Stanislav Shwartsman
d841e82d87
MOVBE instruction exists only in memory form
2011-08-25 21:20:50 +00:00
Stanislav Shwartsman
13feb0772a
- 10% emulation speedup with handlers chaining optimization implemented. The
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feature is enabled by default when configure with --enable-all-optimizations
option, to disable handlers chaining speedups configure with
--disable-handlers-chaining
2011-08-21 14:31:08 +00:00
Stanislav Shwartsman
dd79431702
rename AVX handlers - match their real operands
2011-08-20 15:10:18 +00:00
Stanislav Shwartsman
ed9b8478b5
undo RDTSC commit
2011-08-17 21:13:06 +00:00
Stanislav Shwartsman
165e6f0fdf
separate TSC to uniq feature that can be disabled in CPU configuration
2011-08-17 20:57:44 +00:00
Stanislav Shwartsman
0bc93fdc59
added pentium mmx to cpudb. for now only can be enabled when cpu-level=5
2011-08-16 19:04:36 +00:00
Stanislav Shwartsman
8962cfddde
re-definition of x86-64 support, 1st step towards x86-64 enable/disable through .bochsrc
2011-08-12 18:04:56 +00:00
Stanislav Shwartsman
6344c6a719
Added P2 Klamath CPUID + some code reorg again
2011-08-11 18:06:09 +00:00
Stanislav Shwartsman
d84dbcd02b
fixed *x86 ISA extensions that enable this instruction* in ia_opcodes.h
2011-07-31 20:09:04 +00:00
Stanislav Shwartsman
6aaf9297f8
ability to turn off rdtscp
2011-07-30 09:35:20 +00:00
Stanislav Shwartsman
e48765a511
VMX fixed, cleanups
2011-07-29 20:22:35 +00:00
Stanislav Shwartsman
002c86660a
reword all the CPU code in preparation for future CPU speedup implementation.
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Bochs emulation can be another 10-15% faster using technique described in paper
"Fast Microcode Interpretation with Transactional Commit/Abort"
http://amas-bt.cs.virginia.edu/2011proceedings/amasbt2011-p3.pdf
2011-07-06 20:01:18 +00:00
Stanislav Shwartsman
08ba847ce4
fix bug inserted with prev commit + cleanup
2011-06-28 16:04:40 +00:00
Stanislav Shwartsman
87953711b1
cleanup in mmx code
2011-06-26 19:31:42 +00:00
Stanislav Shwartsman
2f582db722
compile less stuff for cpu-level=5
2011-06-26 19:15:30 +00:00
Stanislav Shwartsman
5ef9f8acf8
cleanup
2011-06-26 17:25:25 +00:00
Stanislav Shwartsman
ef38c9e235
fix decode for VCVTPH2PS
2011-06-11 18:26:05 +00:00
Stanislav Shwartsman
8399dee24c
implemented AVX float16 convert instructions
2011-06-11 13:12:32 +00:00
Stanislav Shwartsman
a02d8cfe67
cleanups, simplications, copyright updates
2011-04-23 20:39:27 +00:00
Stanislav Shwartsman
f0a3cce1e2
added XSAVEOPT instruction emulation (for now with no state tracking according to Intel docs, just alias it to XSAVE)
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update CHANGES
2011-03-25 20:32:07 +00:00
Stanislav Shwartsman
7664c55b08
first fixups after AVX
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(and for AVX)
2011-03-20 18:27:31 +00:00
Stanislav Shwartsman
7ced718040
implemented AVX instructions support
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many changes - some cleanup will follow
please report ay found bugs !
2011-03-19 20:09:34 +00:00
Stanislav Shwartsman
7d80a6ebe0
Adding Id and Rev property to all files
2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
e4c7e21c2c
added comment (check how SVN updates $Id tag)
2011-02-24 21:34:44 +00:00
Stanislav Shwartsman
b5ebe5865e
Fixes for incoming bug report, missed changes in CVS, repository fixups and etc
2011-02-11 09:56:23 +00:00
Stanislav Shwartsman
12005d92cf
split more SSE ops
2011-01-21 19:46:44 +00:00
Stanislav Shwartsman
0de2b305bc
split SSE opcode
2011-01-21 19:21:16 +00:00
Stanislav Shwartsman
a31103e7d8
optimize fetchdecode tables - part2
2011-01-21 16:07:51 +00:00
Stanislav Shwartsman
fbc9b8b190
phase1 of opcode tables optimization
2011-01-20 16:24:42 +00:00
Stanislav Shwartsman
8c5c078b13
optimize sse and mmx code
2011-01-16 20:42:28 +00:00
Stanislav Shwartsman
45f0c72385
remove duplicated instr
2011-01-15 15:17:28 +00:00
Stanislav Shwartsman
7511729424
cleanup
2011-01-13 21:36:56 +00:00
Stanislav Shwartsman
85234807d1
fixed typo
2011-01-09 20:36:13 +00:00
Stanislav Shwartsman
a80b44b6db
split more sse ops
2011-01-09 20:18:02 +00:00
Stanislav Shwartsman
37204c0aaa
split more SSE ops
2011-01-08 12:28:25 +00:00
Stanislav Shwartsman
a1bc92a46b
split more SSE opcodes
2011-01-08 11:20:29 +00:00
Stanislav Shwartsman
2946d0ac26
split more SSE ops
2010-12-30 21:45:39 +00:00
Stanislav Shwartsman
f9f868247a
split more SSE ops
2010-12-30 20:35:10 +00:00
Stanislav Shwartsman
fd5558d4be
another way to implement this op
2010-12-26 20:54:23 +00:00
Stanislav Shwartsman
25b1e2e58d
split more SSE ops
2010-12-26 20:41:47 +00:00
Stanislav Shwartsman
f705cbbc63
rename functions
2010-12-25 19:34:43 +00:00
Stanislav Shwartsman
1bd512e98d
split more SSE ops, optimizations in MMX code
2010-12-25 17:04:36 +00:00
Stanislav Shwartsman
c005444d5b
split more SSE opcodes
2010-12-25 07:59:15 +00:00
Stanislav Shwartsman
040a8e1a3a
split bunch of SSE opcodes
2010-12-24 08:35:00 +00:00
Stanislav Shwartsman
43600f3756
complete rework of SSE code
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next step - split all SSE opcodes by ModC0
2010-12-22 21:16:02 +00:00
Stanislav Shwartsman
29a674e520
split rd/wr CR opcodes for simplicity
2010-12-19 22:36:19 +00:00
Stanislav Shwartsman
48d94d6dc3
optimization
2010-12-18 11:58:16 +00:00
Stanislav Shwartsman
91ac0df65c
implemented GS/FS BASE access instructions published in _319433-007.pdf document
2010-07-22 16:41:59 +00:00
Stanislav Shwartsman
3dfcfd0ccd
Split shift opcodes | optimize SAR opcode
2010-05-18 07:28:05 +00:00
