added XSAVEOPT instruction emulation (for now with no state tracking according to Intel docs, just alias it to XSAVE)

update CHANGES
2011-03-25 20:32:07 +00:00 · 2011-03-25 20:32:07 +00:00 · f0a3cce1e2
commit f0a3cce1e2
parent dd36d3c754
8 changed files with 67 additions and 29 deletions
--- a/bochs/CHANGES
+++ b/bochs/CHANGES
@ -3,19 +3,32 @@ Changes after 2.4.6 release:
 Bochs repository moved to the SVN version control !

 - CPU
-  - Added support of AVX instruction set emulation, to enable configure with
+  - Added support for XSAVEOPT instruction, the instruction can be enabled
+    through .bochsrc CPUID option.
+  - Added support for AVX instruction set emulation, to enable configure with
        --enable-avx option
+  - Updated/Fixed instrumentation callbacks

 - Configure and compile
  - Added ability to configure CPUID family through .bochsrc.
    The default family value determined by configure option --enable-cpu-level.
  - Added ability to configure CPUID model through .bochsrc.
    The default model value is 3.
+  - Configure option --enable-vbe is deprecated is should not be used anymore.
+    The VBE support is always automatically compiled in, in order to enable
+    VBE support the bochsrc option "vga: extension=" has be set to "vbe". If
+    PCI is present, the "pcivga" device can be assigned to PCI slot.

 - I/O Devices
  - Networking
    - new networking module 'slirp' (user mode networking using Slirp and a
      builtin DHCP server)
+  - Hard drive / cdrom
+    - implemented ATA commands "READ NATIVE MAX ADDRESS" and
+      "READ NATIVE MAX ADDRESS EXT"
+  - Sound
+    - ported ES1370 soundcard emulation from Qemu, to enable configure with
+        --enable-es1370 option

 - SF patches applied
  [3190995] add eth backend based on Slirp by Heikki Lindholm
--- a/bochs/PARAM_TREE.txt
+++ b/bochs/PARAM_TREE.txt
@ -38,6 +38,7 @@ cpuid
  aes
  movbe
  xsave
+  xsaveopt
  xapic
  1g_pages
  pcid
--- a/bochs/config.cc
+++ b/bochs/config.cc
@ -322,7 +322,7 @@ void bx_init_options()

  // cpuid subtree
 #if BX_CPU_LEVEL >= 4
-  bx_list_c *cpuid_param = new bx_list_c(root_param, "cpuid", "CPUID Options", 18);
+  bx_list_c *cpuid_param = new bx_list_c(root_param, "cpuid", "CPUID Options", 19);

  new bx_param_bool_c(cpuid_param,
      "cpuid_limit_winnt", "Limit max CPUID function to 3",
@ -405,6 +405,10 @@ void bx_init_options()
      "xsave", "Support for XSAVE extensions",
      "Support for XSAVE extensions",
      0);
+  new bx_param_bool_c(cpuid_param,
+      "xsaveopt", "Support for XSAVEOPT instruction",
+      "Support for XSAVEOPT instruction",
+      0);
 #if BX_SUPPORT_X86_64
  new bx_param_bool_c(cpuid_param,
      "1g_pages", "1G pages support in long mode",
@ -2659,6 +2663,10 @@ static int parse_line_formatted(const char *context, int num_params, char *param
        if (parse_param_bool(params[i], 6, BXPN_CPUID_XSAVE) < 0) {
          PARSE_ERR(("%s: cpuid directive malformed.", context));
        }
+      } else if (!strncmp(params[i], "xsaveopt=", 9)) {
+        if (parse_param_bool(params[i], 9, BXPN_CPUID_XSAVEOPT) < 0) {
+          PARSE_ERR(("%s: cpuid directive malformed.", context));
+        }
      } else if (!strncmp(params[i], "xapic=", 6)) {
        if (parse_param_bool(params[i], 6, BXPN_CPUID_XAPIC) < 0) {
          PARSE_ERR(("%s: cpuid directive malformed.", context));
@ -3876,12 +3884,13 @@ int bx_write_configuration(const char *rc, int overwrite)
  fprintf(fp, ", mmx=%d", SIM->get_param_bool(BXPN_CPUID_MMX)->get());
 #endif
 #if BX_CPU_LEVEL >= 6
-  fprintf(fp, ", sse=%s, xapic=%d, sep=%d, aes=%d, xsave=%d, movbe=%d",
+  fprintf(fp, ", sse=%s, xapic=%d, sep=%d, aes=%d, xsave=%d, xsaveopt=%d, movbe=%d",
    SIM->get_param_enum(BXPN_CPUID_SSE)->get_selected(),
    SIM->get_param_bool(BXPN_CPUID_XAPIC)->get(),
    SIM->get_param_bool(BXPN_CPUID_SEP)->get(),
    SIM->get_param_bool(BXPN_CPUID_AES)->get(),
    SIM->get_param_bool(BXPN_CPUID_XSAVE)->get(),
+    SIM->get_param_bool(BXPN_CPUID_XSAVEOPT)->get(),
    SIM->get_param_bool(BXPN_CPUID_MOVBE)->get());
 #if BX_SUPPORT_X86_64
  fprintf(fp, ", 1g_pages=%d, pcid=%d, fsgsbase=%d",
--- a/bochs/cpu/cpuid.cc
+++ b/bochs/cpu/cpuid.cc
@ -954,6 +954,8 @@ void BX_CPU_C::bx_cpuid_xsave_leaf(Bit32u subfunction)
 {
  BX_ASSERT(BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_XSAVE));

+  static bx_bool xsaveopt_enabled = SIM->get_param_bool(BXPN_CPUID_XSAVEOPT)->get();
+
  switch(subfunction) {
  case 0:
    RAX = BX_CPU_THIS_PTR cpuid_std_function[0xd].eax;
@ -963,7 +965,7 @@ void BX_CPU_C::bx_cpuid_xsave_leaf(Bit32u subfunction)
    break;

  case 1:
-    RAX = 0; // TODO: report XSAVEOPT
+    RAX = xsaveopt_enabled;
    RBX = 0;
    RCX = 0;
    RDX = 0;
@ -998,7 +1000,7 @@ void BX_CPU_C::init_isa_features_bitmask(void)
  Bit32u features_bitmask = 0;

  bx_bool mmx_enabled = 0, movbe_enabled = 0;
-  bx_bool sep_enabled = 0, xsave_enabled = 0;
+  bx_bool sep_enabled = 0, xsave_enabled = 0, xsaveopt_enabled = 0;
  bx_bool aes_enabled = 0, xapic_enabled = 0;
  unsigned sse_enabled = 0;

@ -1010,6 +1012,7 @@ void BX_CPU_C::init_isa_features_bitmask(void)
  aes_enabled = SIM->get_param_bool(BXPN_CPUID_AES)->get();
  movbe_enabled = SIM->get_param_bool(BXPN_CPUID_MOVBE)->get();
  xsave_enabled = SIM->get_param_bool(BXPN_CPUID_XSAVE)->get();
+  xsaveopt_enabled = SIM->get_param_bool(BXPN_CPUID_XSAVEOPT)->get();
  xapic_enabled = SIM->get_param_bool(BXPN_CPUID_XAPIC)->get();
  sse_enabled = SIM->get_param_enum(BXPN_CPUID_SSE)->get();
 #endif // BX_CPU_LEVEL >= 6
@ -1065,13 +1068,6 @@ void BX_CPU_C::init_isa_features_bitmask(void)
     }
  }

-#if BX_SUPPORT_AVX
-  if (BX_SUPPORT_AVX && ! xsave_enabled) {
-     BX_PANIC(("PANIC: AVX emulation requires XSAVE support !"));
-     return;
-  }
-#endif
-
 #if BX_SUPPORT_X86_64
  if (sse_enabled < BX_CPUID_SUPPORT_SSE2) {
    BX_PANIC(("PANIC: x86-64 emulation requires SSE2 support !"));
@ -1113,6 +1109,18 @@ void BX_CPU_C::init_isa_features_bitmask(void)
 #if BX_CPU_LEVEL >= 6
  features_bitmask |= BX_CPU_P6;

+  if (xsaveopt_enabled && ! xsave_enabled) {
+     BX_PANIC(("PANIC: XSAVEOPT emulation requires XSAVE !"));
+     return;
+  }
+
+#if BX_SUPPORT_AVX
+  if (BX_SUPPORT_AVX && ! xsave_enabled) {
+     BX_PANIC(("PANIC: AVX emulation requires XSAVE support !"));
+     return;
+  }
+#endif
+
 #if BX_SUPPORT_MONITOR_MWAIT
  static bx_bool mwait_enabled = SIM->get_param_bool(BXPN_CPUID_MWAIT)->get();
  if (mwait_enabled)
@ -1152,6 +1160,9 @@ void BX_CPU_C::init_isa_features_bitmask(void)
  if (xsave_enabled)
    features_bitmask |= BX_CPU_XSAVE;

+  if (xsaveopt_enabled)
+    features_bitmask |= BX_CPU_XSAVEOPT;
+
  if (aes_enabled)
    features_bitmask |= BX_CPU_AES_PCLMULQDQ;

--- a/bochs/cpu/fetchdecode.h
+++ b/bochs/cpu/fetchdecode.h
@ -712,14 +712,14 @@ static const BxOpcodeInfo_t BxOpcodeInfoG15[8*2] = {
  /* 7 */ { BxPrefixSSE, BX_IA_SFENCE, BxOpcodeGroupSSE_ERR },

  /* /m form */
-  /* 0 */ { BxPrefixSSE, BX_IA_FXSAVE,  BxOpcodeGroupSSE_ERR },
-  /* 1 */ { BxPrefixSSE, BX_IA_FXRSTOR, BxOpcodeGroupSSE_ERR },
-  /* 2 */ { BxPrefixSSE, BX_IA_LDMXCSR, BxOpcodeGroupSSE_ERR },
-  /* 3 */ { BxPrefixSSE, BX_IA_STMXCSR, BxOpcodeGroupSSE_ERR },
-  /* 4 */ { BxPrefixSSE, BX_IA_XSAVE,   BxOpcodeGroupSSE_ERR },
-  /* 5 */ { BxPrefixSSE, BX_IA_XRSTOR,  BxOpcodeGroupSSE_ERR },
-  /* 6 */ { 0, BX_IA_ERROR },
-  /* 7 */ { BxPrefixSSE, BX_IA_CLFLUSH, BxOpcodeGroupSSE_ERR }
+  /* 0 */ { BxPrefixSSE, BX_IA_FXSAVE,   BxOpcodeGroupSSE_ERR },
+  /* 1 */ { BxPrefixSSE, BX_IA_FXRSTOR,  BxOpcodeGroupSSE_ERR },
+  /* 2 */ { BxPrefixSSE, BX_IA_LDMXCSR,  BxOpcodeGroupSSE_ERR },
+  /* 3 */ { BxPrefixSSE, BX_IA_STMXCSR,  BxOpcodeGroupSSE_ERR },
+  /* 4 */ { BxPrefixSSE, BX_IA_XSAVE,    BxOpcodeGroupSSE_ERR },
+  /* 5 */ { BxPrefixSSE, BX_IA_XRSTOR,   BxOpcodeGroupSSE_ERR },
+  /* 6 */ { BxPrefixSSE, BX_IA_XSAVEOPT, BxOpcodeGroupSSE_ERR },
+  /* 7 */ { BxPrefixSSE, BX_IA_CLFLUSH,  BxOpcodeGroupSSE_ERR }
 };

 #if BX_SUPPORT_X86_64
@ -735,14 +735,14 @@ static const BxOpcodeInfo_t BxOpcodeInfoG15q[8*2] = {
  /* 7 */ { BxPrefixSSE, BX_IA_SFENCE, BxOpcodeGroupSSE_ERR },

  /* /m form */
-  /* 0 */ { BxPrefixSSE, BX_IA_FXSAVE,  BxOpcodeGroupSSE_ERR },
-  /* 1 */ { BxPrefixSSE, BX_IA_FXRSTOR, BxOpcodeGroupSSE_ERR },
-  /* 2 */ { BxPrefixSSE, BX_IA_LDMXCSR, BxOpcodeGroupSSE_ERR },
-  /* 3 */ { BxPrefixSSE, BX_IA_STMXCSR, BxOpcodeGroupSSE_ERR },
-  /* 4 */ { BxPrefixSSE, BX_IA_XSAVE,   BxOpcodeGroupSSE_ERR },
-  /* 5 */ { BxPrefixSSE, BX_IA_XRSTOR,  BxOpcodeGroupSSE_ERR },
-  /* 6 */ { 0, BX_IA_ERROR },
-  /* 7 */ { BxPrefixSSE, BX_IA_CLFLUSH, BxOpcodeGroupSSE_ERR }
+  /* 0 */ { BxPrefixSSE, BX_IA_FXSAVE,   BxOpcodeGroupSSE_ERR },
+  /* 1 */ { BxPrefixSSE, BX_IA_FXRSTOR,  BxOpcodeGroupSSE_ERR },
+  /* 2 */ { BxPrefixSSE, BX_IA_LDMXCSR,  BxOpcodeGroupSSE_ERR },
+  /* 3 */ { BxPrefixSSE, BX_IA_STMXCSR,  BxOpcodeGroupSSE_ERR },
+  /* 4 */ { BxPrefixSSE, BX_IA_XSAVE,    BxOpcodeGroupSSE_ERR },
+  /* 5 */ { BxPrefixSSE, BX_IA_XRSTOR,   BxOpcodeGroupSSE_ERR },
+  /* 6 */ { BxPrefixSSE, BX_IA_XSAVEOPT, BxOpcodeGroupSSE_ERR },
+  /* 7 */ { BxPrefixSSE, BX_IA_CLFLUSH,  BxOpcodeGroupSSE_ERR }
 };
 #endif

--- a/bochs/cpu/ia_opcodes.h
+++ b/bochs/cpu/ia_opcodes.h
@ -1126,6 +1126,7 @@ bx_define_opcode(BX_IA_XRSTOR, &BX_CPU_C::XRSTOR, &BX_CPU_C::BxError, BX_CPU_XSA
 bx_define_opcode(BX_IA_XSAVE, &BX_CPU_C::XSAVE, &BX_CPU_C::BxError, BX_CPU_XSAVE, 0)
 bx_define_opcode(BX_IA_XSETBV, &BX_CPU_C::BxError, &BX_CPU_C::XSETBV, BX_CPU_XSAVE, 0)
 bx_define_opcode(BX_IA_XGETBV, &BX_CPU_C::BxError, &BX_CPU_C::XGETBV, BX_CPU_XSAVE, 0)
+bx_define_opcode(BX_IA_XSAVEOPT, &BX_CPU_C::XSAVE, &BX_CPU_C::BxError, BX_CPU_XSAVEOPT, 0)

 // AES instructions
 bx_define_opcode(BX_IA_AESIMC_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::AESIMC_VdqWdqR, BX_CPU_AES_PCLMULQDQ, BX_PREPARE_SSE)
--- a/bochs/main.cc
+++ b/bochs/main.cc
@ -1013,6 +1013,7 @@ void bx_init_hardware()
  bx_bool movbe_enabled = SIM->get_param_bool(BXPN_CPUID_MOVBE)->get();
  bx_bool sep_enabled = SIM->get_param_bool(BXPN_CPUID_SEP)->get();
  bx_bool xsave_enabled = SIM->get_param_bool(BXPN_CPUID_XSAVE)->get();
+  bx_bool xsaveopt_enabled = SIM->get_param_bool(BXPN_CPUID_XSAVEOPT)->get();
 #if BX_SUPPORT_X86_64
  bx_bool xlarge_pages_enabled = SIM->get_param_bool(BXPN_CPUID_1G_PAGES)->get();
 #endif
@ -1057,7 +1058,8 @@ void bx_init_hardware()
 #if BX_CPU_LEVEL >= 6
  BX_INFO(("  SEP support: %s",sep_enabled?"yes":"no"));
  BX_INFO(("  SSE support: %s", SIM->get_param_enum(BXPN_CPUID_SSE)->get_selected()));
-  BX_INFO(("  XSAVE support: %s",xsave_enabled?"yes":"no"));
+  BX_INFO(("  XSAVE support: %s %s",
+    xsave_enabled?"xsave":"no", xsaveopt_enabled?"xsaveopt":""));
  BX_INFO(("  AES support: %s",aes_enabled?"yes":"no"));
  BX_INFO(("  MOVBE support: %s",movbe_enabled?"yes":"no"));
  BX_INFO(("  x86-64 support: %s",BX_SUPPORT_X86_64?"yes":"no"));
--- a/bochs/param_names.h
+++ b/bochs/param_names.h
@ -52,6 +52,7 @@
 #define BXPN_CPUID_MOVBE                 "cpuid.movbe"
 #define BXPN_CPUID_SEP                   "cpuid.sep"
 #define BXPN_CPUID_XSAVE                 "cpuid.xsave"
+#define BXPN_CPUID_XSAVEOPT              "cpuid.xsaveopt"
 #define BXPN_CPUID_XAPIC                 "cpuid.xapic"
 #define BXPN_CPUID_MWAIT                 "cpuid.mwait"
 #define BXPN_CPUID_MWAIT_IS_NOP          "cpuid.mwait_is_nop"