rename functions
This commit is contained in:
Stanislav Shwartsman
parent
1bd512e98d
commit
f705cbbc63
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.697 2010-12-25 17:04:35 sshwarts Exp $
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// $Id: cpu.h,v 1.698 2010-12-25 19:34:43 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2011 The Bochs Project
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@ -1766,11 +1766,12 @@ public: // for now...
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#if BX_SUPPORT_X86_64
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BX_SMF void LOAD_Eq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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#endif
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BX_SMF void LOADA_Vdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LOADU_Vdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LOAD_Vdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LOAD_Vss(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LOAD_Vsd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LOADA_Wdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LOADU_Wdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LOAD_Wdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LOAD_Wss(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LOAD_Wsd(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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BX_SMF void LOAD_Ww(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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#if BX_SUPPORT_FPU == 0 // if FPU is disabled
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BX_SMF void FPU_ESC(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: ia_opcodes.h,v 1.56 2010-12-25 17:04:36 sshwarts Exp $
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// $Id: ia_opcodes.h,v 1.57 2010-12-25 19:34:43 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2008-2011 Stanislav Shwartsman
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@ -1013,47 +1013,47 @@ bx_define_opcode(BX_IA_UCOMISS_VssWss, &BX_CPU_C::UCOMISS_VssWss, NULL, BX_CPU_S
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bx_define_opcode(BX_IA_COMISS_VpsWps, &BX_CPU_C::COMISS_VpsWps, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MOVMSKPS_GdVRps, &BX_CPU_C::MOVMSKPS_GdVRps, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_SQRTPS_VpsWpsR, &BX_CPU_C::SQRTPS_VpsWpsR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_SQRTPS_VpsWpsM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::SQRTPS_VpsWpsR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_SQRTPS_VpsWpsM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SQRTPS_VpsWpsR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_SQRTSS_VssWssR, &BX_CPU_C::SQRTSS_VssWssR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_SQRTSS_VssWssM, &BX_CPU_C::LOAD_Vss, &BX_CPU_C::SQRTSS_VssWssR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_SQRTSS_VssWssM, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::SQRTSS_VssWssR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_RSQRTPS_VpsWpsR, &BX_CPU_C::RSQRTPS_VpsWpsR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_RSQRTPS_VpsWpsM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::RSQRTPS_VpsWpsR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_RSQRTPS_VpsWpsM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::RSQRTPS_VpsWpsR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_RSQRTSS_VssWssR, &BX_CPU_C::RSQRTSS_VssWssR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_RSQRTSS_VssWssM, &BX_CPU_C::LOAD_Vss, &BX_CPU_C::RSQRTSS_VssWssR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_RSQRTSS_VssWssM, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::RSQRTSS_VssWssR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_RCPPS_VpsWpsR, &BX_CPU_C::RCPPS_VpsWpsR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_RCPPS_VpsWpsM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::RCPPS_VpsWpsR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_RCPPS_VpsWpsM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::RCPPS_VpsWpsR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_RCPSS_VssWssR, &BX_CPU_C::RCPSS_VssWssR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_RCPSS_VssWssM, &BX_CPU_C::LOAD_Vss, &BX_CPU_C::RCPSS_VssWssR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_RCPSS_VssWssM, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::RCPSS_VssWssR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_ADDPS_VpsWpsR, &BX_CPU_C::ADDPS_VpsWpsR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_ADDPS_VpsWpsM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::ADDPS_VpsWpsR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_ADDPS_VpsWpsM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ADDPS_VpsWpsR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_ADDSS_VssWssR, &BX_CPU_C::ADDSS_VssWssR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_ADDSS_VssWssM, &BX_CPU_C::LOAD_Vss, &BX_CPU_C::ADDSS_VssWssR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_ADDSS_VssWssM, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::ADDSS_VssWssR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MULPS_VpsWpsR, &BX_CPU_C::MULPS_VpsWpsR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MULPS_VpsWpsM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::MULPS_VpsWpsR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MULPS_VpsWpsM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MULPS_VpsWpsR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MULSS_VssWssR, &BX_CPU_C::MULSS_VssWssR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MULSS_VssWssM, &BX_CPU_C::LOAD_Vss, &BX_CPU_C::MULSS_VssWssR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MULSS_VssWssM, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::MULSS_VssWssR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_SUBPS_VpsWpsR, &BX_CPU_C::SUBPS_VpsWpsR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_SUBPS_VpsWpsM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::SUBPS_VpsWpsR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_SUBPS_VpsWpsM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SUBPS_VpsWpsR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_SUBSS_VssWssR, &BX_CPU_C::SUBSS_VssWssR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_SUBSS_VssWssM, &BX_CPU_C::LOAD_Vss, &BX_CPU_C::SUBSS_VssWssR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_SUBSS_VssWssM, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::SUBSS_VssWssR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MINPS_VpsWpsR, &BX_CPU_C::MINPS_VpsWpsR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MINPS_VpsWpsM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::MINPS_VpsWpsR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MINPS_VpsWpsM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MINPS_VpsWpsR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MINSS_VssWssR, &BX_CPU_C::MINSS_VssWssR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MINSS_VssWssM, &BX_CPU_C::LOAD_Vss, &BX_CPU_C::MINSS_VssWssR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MINSS_VssWssM, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::MINSS_VssWssR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_DIVPS_VpsWpsR, &BX_CPU_C::DIVPS_VpsWpsR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_DIVPS_VpsWpsM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::DIVPS_VpsWpsR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_DIVPS_VpsWpsM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::DIVPS_VpsWpsR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_DIVSS_VssWssR, &BX_CPU_C::DIVSS_VssWssR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_DIVSS_VssWssM, &BX_CPU_C::LOAD_Vss, &BX_CPU_C::DIVSS_VssWssR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_DIVSS_VssWssM, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::DIVSS_VssWssR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MAXPS_VpsWpsR, &BX_CPU_C::MAXPS_VpsWpsR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MAXPS_VpsWpsM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::MAXPS_VpsWpsR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MAXPS_VpsWpsM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MAXPS_VpsWpsR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MAXSS_VssWssR, &BX_CPU_C::MAXSS_VssWssR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MAXSS_VssWssM, &BX_CPU_C::LOAD_Vss, &BX_CPU_C::MAXSS_VssWssR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MAXSS_VssWssM, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::MAXSS_VssWssR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_PSHUFW_PqQqIb, &BX_CPU_C::PSHUFW_PqQqIb, NULL, BX_CPU_SSE | BX_CPU_3DNOW, 0)
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bx_define_opcode(BX_IA_PSHUFLW_VdqWdqIb, &BX_CPU_C::PSHUFLW_VdqWdqIb, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_CMPPS_VpsWpsIbR, &BX_CPU_C::CMPPS_VpsWpsIbR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_CMPPS_VpsWpsIbM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::CMPPS_VpsWpsIbR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_CMPPS_VpsWpsIbM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CMPPS_VpsWpsIbR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_CMPSS_VssWssIbR, &BX_CPU_C::CMPSS_VssWssIbR, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_CMPSS_VssWssIbM, &BX_CPU_C::LOAD_Vss, &BX_CPU_C::CMPSS_VssWssIbR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_CMPSS_VssWssIbM, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CMPSS_VssWssIbR, BX_CPU_SSE, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_PINSRW_PqEwIb, &BX_CPU_C::PINSRW_PqEwIb, NULL, BX_CPU_SSE | BX_CPU_3DNOW, 0)
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bx_define_opcode(BX_IA_PEXTRW_GdPqIb, &BX_CPU_C::PEXTRW_GdPqIb, NULL, BX_CPU_SSE | BX_CPU_3DNOW, 0)
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bx_define_opcode(BX_IA_SHUFPS_VpsWpsIb, &BX_CPU_C::SHUFPS_VpsWpsIb, NULL, BX_CPU_SSE, BX_PREPARE_SSE)
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@ -1086,17 +1086,17 @@ bx_define_opcode(BX_IA_UCOMISD_VsdWsd, &BX_CPU_C::UCOMISD_VsdWsd, NULL, BX_CPU_S
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bx_define_opcode(BX_IA_COMISD_VpdWpd, &BX_CPU_C::COMISD_VpdWpd, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MOVMSKPD_GdVRpd, &BX_CPU_C::MOVMSKPD_GdVRpd, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_SQRTPD_VpdWpdR, &BX_CPU_C::SQRTPD_VpdWpdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_SQRTPD_VpdWpdM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::SQRTPD_VpdWpdR, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_SQRTPD_VpdWpdM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SQRTPD_VpdWpdR, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_SQRTSD_VsdWsdR, &BX_CPU_C::SQRTSD_VsdWsdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_SQRTSD_VsdWsdM, &BX_CPU_C::LOAD_Vsd, &BX_CPU_C::SQRTSD_VsdWsdR, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_SQRTSD_VsdWsdM, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::SQRTSD_VsdWsdR, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_ADDPD_VpdWpdR, &BX_CPU_C::ADDPD_VpdWpdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_ADDPD_VpdWpdM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::ADDPD_VpdWpdR, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_ADDPD_VpdWpdM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ADDPD_VpdWpdR, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_ADDSD_VsdWsdR, &BX_CPU_C::ADDSD_VsdWsdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_ADDSD_VsdWsdM, &BX_CPU_C::LOAD_Vsd, &BX_CPU_C::ADDSD_VsdWsdR, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_ADDSD_VsdWsdM, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::ADDSD_VsdWsdR, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MULPD_VpdWpdR, &BX_CPU_C::MULPD_VpdWpdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MULPD_VpdWpdM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::MULPD_VpdWpdR, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MULPD_VpdWpdM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MULPD_VpdWpdR, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MULSD_VsdWsdR, &BX_CPU_C::MULSD_VsdWsdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MULSD_VsdWsdM, &BX_CPU_C::LOAD_Vsd, &BX_CPU_C::MULSD_VsdWsdR, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_MULSD_VsdWsdM, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::MULSD_VsdWsdR, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_CVTPS2PD_VpsWps, &BX_CPU_C::CVTPS2PD_VpsWps, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_CVTPD2PS_VpdWpd, &BX_CPU_C::CVTPD2PS_VpdWpd, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_CVTSD2SS_VsdWsd, &BX_CPU_C::CVTSD2SS_VsdWsd, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
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@ -1105,21 +1105,21 @@ bx_define_opcode(BX_IA_CVTDQ2PS_VpsWdq, &BX_CPU_C::CVTDQ2PS_VpsWdq, NULL, BX_CPU
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bx_define_opcode(BX_IA_CVTPS2DQ_VdqWps, &BX_CPU_C::CVTPS2DQ_VdqWps, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_CVTTPS2DQ_VdqWps, &BX_CPU_C::CVTTPS2DQ_VdqWps, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_SUBPD_VpdWpdR, &BX_CPU_C::SUBPD_VpdWpdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_SUBPD_VpdWpdM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::SUBPD_VpdWpdR, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_SUBPD_VpdWpdM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SUBPD_VpdWpdR, BX_CPU_SSE2, BX_PREPARE_SSE)
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bx_define_opcode(BX_IA_SUBSD_VsdWsdR, &BX_CPU_C::SUBSD_VsdWsdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
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||||
bx_define_opcode(BX_IA_SUBSD_VsdWsdM, &BX_CPU_C::LOAD_Vsd, &BX_CPU_C::SUBSD_VsdWsdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_SUBSD_VsdWsdM, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::SUBSD_VsdWsdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MINPD_VpdWpdR, &BX_CPU_C::MINPD_VpdWpdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MINPD_VpdWpdM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::MINPD_VpdWpdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MINPD_VpdWpdM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MINPD_VpdWpdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MINSD_VsdWsdR, &BX_CPU_C::MINSD_VsdWsdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MINSD_VsdWsdM, &BX_CPU_C::LOAD_Vsd, &BX_CPU_C::MINSD_VsdWsdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MINSD_VsdWsdM, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::MINSD_VsdWsdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_DIVPD_VpdWpdR, &BX_CPU_C::DIVPD_VpdWpdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_DIVPD_VpdWpdM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::DIVPD_VpdWpdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_DIVPD_VpdWpdM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::DIVPD_VpdWpdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_DIVSD_VsdWsdR, &BX_CPU_C::DIVSD_VsdWsdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_DIVSD_VsdWsdM, &BX_CPU_C::LOAD_Vsd, &BX_CPU_C::DIVSD_VsdWsdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_DIVSD_VsdWsdM, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::DIVSD_VsdWsdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MAXPD_VpdWpdR, &BX_CPU_C::MAXPD_VpdWpdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MAXPD_VpdWpdM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::MAXPD_VpdWpdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MAXPD_VpdWpdM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MAXPD_VpdWpdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MAXSD_VsdWsdR, &BX_CPU_C::MAXSD_VsdWsdR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MAXSD_VsdWsdM, &BX_CPU_C::LOAD_Vsd, &BX_CPU_C::MAXSD_VsdWsdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MAXSD_VsdWsdM, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::MAXSD_VsdWsdR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_UNPCKHPD_VpdWdq, &BX_CPU_C::PUNPCKHQDQ_VdqWdq, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_UNPCKLPD_VpdWdq, &BX_CPU_C::PUNPCKLQDQ_VdqWdq, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PUNPCKHDQ_VdqWdq, &BX_CPU_C::UNPCKHPS_VpsWdq, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
@ -1180,9 +1180,9 @@ bx_define_opcode(BX_IA_MOVD_EdVdM, &BX_CPU_C::MOVSS_WssVssM, NULL, BX_CPU_SSE2,
|
||||
bx_define_opcode(BX_IA_MOVQ_VqWqR, &BX_CPU_C::MOVQ_VqWqR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MOVQ_VqWqM, &BX_CPU_C::MOVQ_VqWqM, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CMPPD_VpdWpdIbR, &BX_CPU_C::CMPPD_VpdWpdIbR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CMPPD_VpdWpdIbM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::CMPPD_VpdWpdIbR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CMPPD_VpdWpdIbM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CMPPD_VpdWpdIbR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CMPSD_VsdWsdIbR, &BX_CPU_C::CMPSD_VsdWsdIbR, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CMPSD_VsdWsdIbM, &BX_CPU_C::LOAD_Vsd, &BX_CPU_C::CMPSD_VsdWsdIbR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_CMPSD_VsdWsdIbM, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CMPSD_VsdWsdIbR, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MOVNTI_MdGd, &BX_CPU_C::MOVNTI_MdGd, NULL, BX_CPU_SSE2, 0 /* CHECKED */)
|
||||
bx_define_opcode(BX_IA_PINSRW_VdqEwIb, &BX_CPU_C::PINSRW_VdqEwIb, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PEXTRW_GdUdqIb, &BX_CPU_C::PEXTRW_GdUdqIb, NULL, BX_CPU_SSE2, BX_PREPARE_SSE)
|
||||
@ -1252,23 +1252,23 @@ bx_define_opcode(BX_IA_MFENCE, &BX_CPU_C::NOP, NULL, BX_CPU_SSE2, 0 /* CHECKED *
|
||||
|
||||
// SSE3
|
||||
bx_define_opcode(BX_IA_MOVDDUP_VpdWqR, &BX_CPU_C::MOVDDUP_VpdWqR, NULL, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MOVDDUP_VpdWqM, &BX_CPU_C::LOAD_Vsd, &BX_CPU_C::MOVDDUP_VpdWqR, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MOVDDUP_VpdWqM, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::MOVDDUP_VpdWqR, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MOVSLDUP_VpsWpsR, &BX_CPU_C::MOVSLDUP_VpsWpsR, NULL, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MOVSLDUP_VpsWpsM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::MOVSLDUP_VpsWpsR, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MOVSLDUP_VpsWpsM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MOVSLDUP_VpsWpsR, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MOVSHDUP_VpsWpsR, &BX_CPU_C::MOVSHDUP_VpsWpsR, NULL, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MOVSHDUP_VpsWpsM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::MOVSHDUP_VpsWpsR, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MOVSHDUP_VpsWpsM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MOVSHDUP_VpsWpsR, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_HADDPD_VpdWpdR, &BX_CPU_C::HADDPD_VpdWpdR, NULL, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_HADDPD_VpdWpdM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::HADDPD_VpdWpdR, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_HADDPD_VpdWpdM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::HADDPD_VpdWpdR, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_HADDPS_VpsWpsR, &BX_CPU_C::HADDPS_VpsWpsR, NULL, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_HADDPS_VpsWpsM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::HADDPS_VpsWpsR, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_HADDPS_VpsWpsM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::HADDPS_VpsWpsR, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_HSUBPD_VpdWpdR, &BX_CPU_C::HSUBPD_VpdWpdR, NULL, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_HSUBPD_VpdWpdM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::HSUBPD_VpdWpdR, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_HSUBPD_VpdWpdM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::HSUBPD_VpdWpdR, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_HSUBPS_VpsWpsR, &BX_CPU_C::HSUBPS_VpsWpsR, NULL, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_HSUBPS_VpsWpsM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::HSUBPS_VpsWpsR, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_HSUBPS_VpsWpsM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::HSUBPS_VpsWpsR, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_ADDSUBPD_VpdWpdR, &BX_CPU_C::ADDSUBPD_VpdWpdR, NULL, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_ADDSUBPD_VpdWpdM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::ADDSUBPD_VpdWpdR, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_ADDSUBPD_VpdWpdM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ADDSUBPD_VpdWpdR, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_ADDSUBPS_VpsWpsR, &BX_CPU_C::ADDSUBPS_VpsWpsR, NULL, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_ADDSUBPS_VpsWpsM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::ADDSUBPS_VpsWpsR, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_ADDSUBPS_VpsWpsM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ADDSUBPS_VpsWpsR, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_LDDQU_VdqMdq, &BX_CPU_C::MOVUPS_VpsWpsM, NULL, BX_CPU_SSE3, BX_PREPARE_SSE)
|
||||
// SSE3
|
||||
|
||||
@ -1310,19 +1310,19 @@ bx_define_opcode(BX_IA_PALIGNR_VdqWdqIb, &BX_CPU_C::PALIGNR_VdqWdqIb, NULL, BX_C
|
||||
|
||||
// SSE4.1
|
||||
bx_define_opcode(BX_IA_PBLENDVB_VdqWdqR, &BX_CPU_C::PBLENDVB_VdqWdqR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PBLENDVB_VdqWdqM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::PBLENDVB_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PBLENDVB_VdqWdqM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PBLENDVB_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_BLENDVPS_VpsWpsR, &BX_CPU_C::BLENDVPS_VpsWpsR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_BLENDVPS_VpsWpsM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::BLENDVPS_VpsWpsR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_BLENDVPS_VpsWpsM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::BLENDVPS_VpsWpsR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_BLENDVPD_VpdWpdR, &BX_CPU_C::BLENDVPD_VpdWpdR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_BLENDVPD_VpdWpdM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::BLENDVPD_VpdWpdR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_BLENDVPD_VpdWpdM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::BLENDVPD_VpdWpdR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PTEST_VdqWdqR, &BX_CPU_C::PTEST_VdqWdqR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PTEST_VdqWdqM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::PTEST_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PTEST_VdqWdqM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PTEST_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMULDQ_VdqWdqR, &BX_CPU_C::PMULDQ_VdqWdqR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMULDQ_VdqWdqM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::PMULDQ_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMULDQ_VdqWdqM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMULDQ_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PCMPEQQ_VdqWdqR, &BX_CPU_C::PCMPEQQ_VdqWdqR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PCMPEQQ_VdqWdqM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::PCMPEQQ_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PCMPEQQ_VdqWdqM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPEQQ_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PACKUSDW_VdqWdqR, &BX_CPU_C::PACKUSDW_VdqWdqR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PACKUSDW_VdqWdqM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::PACKUSDW_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PACKUSDW_VdqWdqM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PACKUSDW_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMOVSXBW_VdqWq, &BX_CPU_C::PMOVSXBW_VdqWq, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMOVSXBD_VdqWd, &BX_CPU_C::PMOVSXBD_VdqWd, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMOVSXBQ_VdqWw, &BX_CPU_C::PMOVSXBQ_VdqWw, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
@ -1336,39 +1336,39 @@ bx_define_opcode(BX_IA_PMOVZXWD_VdqWq, &BX_CPU_C::PMOVZXWD_VdqWq, NULL, BX_CPU_S
|
||||
bx_define_opcode(BX_IA_PMOVZXWQ_VdqWd, &BX_CPU_C::PMOVZXWQ_VdqWd, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMOVZXDQ_VdqWq, &BX_CPU_C::PMOVZXDQ_VdqWq, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMINSB_VdqWdqR, &BX_CPU_C::PMINSB_VdqWdqR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMINSB_VdqWdqM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::PMINSB_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMINSB_VdqWdqM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMINSB_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMINSD_VdqWdqR, &BX_CPU_C::PMINSD_VdqWdqR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMINSD_VdqWdqM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::PMINSD_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMINSD_VdqWdqM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMINSD_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMINUW_VdqWdqR, &BX_CPU_C::PMINUW_VdqWdqR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMINUW_VdqWdqM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::PMINUW_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMINUW_VdqWdqM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMINUW_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMINUD_VdqWdqR, &BX_CPU_C::PMINUD_VdqWdqR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMINUD_VdqWdqM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::PMINUD_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMINUD_VdqWdqM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMINUD_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMAXSB_VdqWdqR, &BX_CPU_C::PMAXSB_VdqWdqR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMAXSB_VdqWdqM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::PMAXSB_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMAXSB_VdqWdqM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMAXSB_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMAXSD_VdqWdqR, &BX_CPU_C::PMAXSD_VdqWdqR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMAXSD_VdqWdqM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::PMAXSD_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMAXSD_VdqWdqM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMAXSD_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMAXUW_VdqWdqR, &BX_CPU_C::PMAXUW_VdqWdqR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMAXUW_VdqWdqM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::PMAXUW_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMAXUW_VdqWdqM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMAXUW_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMAXUD_VdqWdqR, &BX_CPU_C::PMAXUD_VdqWdqR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMAXUD_VdqWdqM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::PMAXUD_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMAXUD_VdqWdqM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMAXUD_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMULLD_VdqWdqR, &BX_CPU_C::PMULLD_VdqWdqR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMULLD_VdqWdqM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::PMULLD_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PMULLD_VdqWdqM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMULLD_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PHMINPOSUW_VdqWdqR, &BX_CPU_C::PHMINPOSUW_VdqWdqR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PHMINPOSUW_VdqWdqM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::PHMINPOSUW_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PHMINPOSUW_VdqWdqM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PHMINPOSUW_VdqWdqR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_ROUNDPS_VpsWpsIbR, &BX_CPU_C::ROUNDPS_VpsWpsIbR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_ROUNDPS_VpsWpsIbM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::ROUNDPS_VpsWpsIbR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_ROUNDPS_VpsWpsIbM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ROUNDPS_VpsWpsIbR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_ROUNDPD_VpdWpdIbR, &BX_CPU_C::ROUNDPD_VpdWpdIbR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_ROUNDPD_VpdWpdIbM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::ROUNDPD_VpdWpdIbR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_ROUNDPD_VpdWpdIbM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ROUNDPD_VpdWpdIbR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_ROUNDSS_VssWssIbR, &BX_CPU_C::ROUNDSS_VssWssIbR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_ROUNDSS_VssWssIbM, &BX_CPU_C::LOAD_Vss, &BX_CPU_C::ROUNDSS_VssWssIbR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_ROUNDSS_VssWssIbM, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::ROUNDSS_VssWssIbR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_ROUNDSD_VsdWsdIbR, &BX_CPU_C::ROUNDSD_VsdWsdIbR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_ROUNDSD_VsdWsdIbM, &BX_CPU_C::LOAD_Vsd, &BX_CPU_C::ROUNDSD_VsdWsdIbR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_ROUNDSD_VsdWsdIbM, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::ROUNDSD_VsdWsdIbR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_BLENDPS_VpsWpsIbR, &BX_CPU_C::BLENDPS_VpsWpsIbR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_BLENDPS_VpsWpsIbM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::BLENDPS_VpsWpsIbR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_BLENDPS_VpsWpsIbM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::BLENDPS_VpsWpsIbR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_BLENDPD_VpdWpdIbR, &BX_CPU_C::BLENDPD_VpdWpdIbR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_BLENDPD_VpdWpdIbM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::BLENDPD_VpdWpdIbR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_BLENDPD_VpdWpdIbM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::BLENDPD_VpdWpdIbR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PBLENDW_VdqWdqIbR, &BX_CPU_C::PBLENDW_VdqWdqIbR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PBLENDW_VdqWdqIbM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::PBLENDW_VdqWdqIbR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PBLENDW_VdqWdqIbM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PBLENDW_VdqWdqIbR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PEXTRB_EbdVdqIbR, &BX_CPU_C::PEXTRB_EbdVdqIbR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PEXTRB_EbdVdqIbM, &BX_CPU_C::PEXTRB_EbdVdqIbM, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PEXTRW_EwdVdqIbR, &BX_CPU_C::PEXTRW_EwdVdqIbR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
@ -1382,11 +1382,11 @@ bx_define_opcode(BX_IA_INSERTPS_VpsWssIb, &BX_CPU_C::INSERTPS_VpsWssIb, NULL, BX
|
||||
bx_define_opcode(BX_IA_PINSRD_VdqEdIbR, &BX_CPU_C::PINSRD_VdqEdIbR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PINSRD_VdqEdIbM, &BX_CPU_C::PINSRD_VdqEdIbM, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_DPPS_VpsWpsIbR, &BX_CPU_C::DPPS_VpsWpsIbR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_DPPS_VpsWpsIbM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::DPPS_VpsWpsIbR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_DPPS_VpsWpsIbM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::DPPS_VpsWpsIbR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_DPPD_VpdWpdIbR, &BX_CPU_C::DPPD_VpdWpdIbR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_DPPD_VpdWpdIbM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::DPPD_VpdWpdIbR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_DPPD_VpdWpdIbM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::DPPD_VpdWpdIbR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MPSADBW_VdqWdqIbR, &BX_CPU_C::MPSADBW_VdqWdqIbR, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MPSADBW_VdqWdqIbM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::MPSADBW_VdqWdqIbR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MPSADBW_VdqWdqIbM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::MPSADBW_VdqWdqIbR, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_MOVNTDQA_VdqMdq, &BX_CPU_C::MOVAPS_VpsWpsM, NULL, BX_CPU_SSE4_1, BX_PREPARE_SSE)
|
||||
// SSE4.1
|
||||
|
||||
@ -1399,15 +1399,15 @@ bx_define_opcode(BX_IA_CRC32_GdEd, &BX_CPU_C::CRC32_GdEd, NULL, BX_CPU_SSE4_2, 0
|
||||
bx_define_opcode(BX_IA_CRC32_GdEq, &BX_CPU_C::CRC32_GdEq, NULL, BX_CPU_SSE4_2 | BX_CPU_X86_64, 0)
|
||||
#endif
|
||||
bx_define_opcode(BX_IA_PCMPGTQ_VdqWdqR, &BX_CPU_C::PCMPGTQ_VdqWdqR, NULL, BX_CPU_SSE4_2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PCMPGTQ_VdqWdqM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::PCMPGTQ_VdqWdqR, BX_CPU_SSE4_2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PCMPGTQ_VdqWdqM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCMPGTQ_VdqWdqR, BX_CPU_SSE4_2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PCMPESTRM_VdqWdqIbR, &BX_CPU_C::PCMPESTRM_VdqWdqIbR, NULL, BX_CPU_SSE4_2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PCMPESTRM_VdqWdqIbM, &BX_CPU_C::LOADU_Vdq, &BX_CPU_C::PCMPESTRM_VdqWdqIbR, BX_CPU_SSE4_2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PCMPESTRM_VdqWdqIbM, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPESTRM_VdqWdqIbR, BX_CPU_SSE4_2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PCMPESTRI_VdqWdqIbR, &BX_CPU_C::PCMPESTRI_VdqWdqIbR, NULL, BX_CPU_SSE4_2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PCMPESTRI_VdqWdqIbM, &BX_CPU_C::LOADU_Vdq, &BX_CPU_C::PCMPESTRI_VdqWdqIbR, BX_CPU_SSE4_2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PCMPESTRI_VdqWdqIbM, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPESTRI_VdqWdqIbR, BX_CPU_SSE4_2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PCMPISTRM_VdqWdqIbR, &BX_CPU_C::PCMPISTRM_VdqWdqIbR, NULL, BX_CPU_SSE4_2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PCMPISTRM_VdqWdqIbM, &BX_CPU_C::LOADU_Vdq, &BX_CPU_C::PCMPISTRM_VdqWdqIbR, BX_CPU_SSE4_2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PCMPISTRM_VdqWdqIbM, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPISTRM_VdqWdqIbR, BX_CPU_SSE4_2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PCMPISTRI_VdqWdqIbR, &BX_CPU_C::PCMPISTRI_VdqWdqIbR, NULL, BX_CPU_SSE4_2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PCMPISTRI_VdqWdqIbM, &BX_CPU_C::LOADU_Vdq, &BX_CPU_C::PCMPISTRI_VdqWdqIbR, BX_CPU_SSE4_2, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PCMPISTRI_VdqWdqIbM, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::PCMPISTRI_VdqWdqIbR, BX_CPU_SSE4_2, BX_PREPARE_SSE)
|
||||
// SSE4.2
|
||||
|
||||
// MOVBE instruction
|
||||
@ -1445,19 +1445,19 @@ bx_define_opcode(BX_IA_XGETBV, &BX_CPU_C::XGETBV, NULL, BX_CPU_XSAVE, 0)
|
||||
|
||||
// AES instructions
|
||||
bx_define_opcode(BX_IA_AESIMC_VdqWdqR, &BX_CPU_C::AESIMC_VdqWdqR, NULL, BX_CPU_AES_PCLMULQDQ, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_AESIMC_VdqWdqM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::AESIMC_VdqWdqR, BX_CPU_AES_PCLMULQDQ, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_AESIMC_VdqWdqM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::AESIMC_VdqWdqR, BX_CPU_AES_PCLMULQDQ, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_AESENC_VdqWdqR, &BX_CPU_C::AESENC_VdqWdqR, NULL, BX_CPU_AES_PCLMULQDQ, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_AESENC_VdqWdqM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::AESENC_VdqWdqR, BX_CPU_AES_PCLMULQDQ, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_AESENC_VdqWdqM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::AESENC_VdqWdqR, BX_CPU_AES_PCLMULQDQ, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_AESENCLAST_VdqWdqR, &BX_CPU_C::AESENCLAST_VdqWdqR, NULL, BX_CPU_AES_PCLMULQDQ, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_AESENCLAST_VdqWdqM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::AESENCLAST_VdqWdqR, BX_CPU_AES_PCLMULQDQ, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_AESENCLAST_VdqWdqM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::AESENCLAST_VdqWdqR, BX_CPU_AES_PCLMULQDQ, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_AESDEC_VdqWdqR, &BX_CPU_C::AESDEC_VdqWdqR, NULL, BX_CPU_AES_PCLMULQDQ, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_AESDEC_VdqWdqM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::AESDEC_VdqWdqR, BX_CPU_AES_PCLMULQDQ, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_AESDEC_VdqWdqM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::AESDEC_VdqWdqR, BX_CPU_AES_PCLMULQDQ, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_AESDECLAST_VdqWdqR, &BX_CPU_C::AESDECLAST_VdqWdqR, NULL, BX_CPU_AES_PCLMULQDQ, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_AESDECLAST_VdqWdqM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::AESDECLAST_VdqWdqR, BX_CPU_AES_PCLMULQDQ, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_AESDECLAST_VdqWdqM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::AESDECLAST_VdqWdqR, BX_CPU_AES_PCLMULQDQ, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_AESKEYGENASSIST_VdqWdqIbR, &BX_CPU_C::AESKEYGENASSIST_VdqWdqIbR, NULL, BX_CPU_AES_PCLMULQDQ, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_AESKEYGENASSIST_VdqWdqIbM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::AESKEYGENASSIST_VdqWdqIbR, BX_CPU_AES_PCLMULQDQ, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_AESKEYGENASSIST_VdqWdqIbM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::AESKEYGENASSIST_VdqWdqIbR, BX_CPU_AES_PCLMULQDQ, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PCLMULQDQ_VdqWdqIbR, &BX_CPU_C::PCLMULQDQ_VdqWdqIbR, NULL, BX_CPU_AES_PCLMULQDQ, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PCLMULQDQ_VdqWdqIbM, &BX_CPU_C::LOAD_Vdq, &BX_CPU_C::PCLMULQDQ_VdqWdqIbR, BX_CPU_AES_PCLMULQDQ, BX_PREPARE_SSE)
|
||||
bx_define_opcode(BX_IA_PCLMULQDQ_VdqWdqIbM, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCLMULQDQ_VdqWdqIbR, BX_CPU_AES_PCLMULQDQ, BX_PREPARE_SSE)
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
bx_define_opcode(BX_IA_ADD_GqEqM, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::ADD_GqEqR, BX_CPU_X86_64, 0)
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: load.cc,v 1.4 2010-12-25 15:00:20 sshwarts Exp $
|
||||
// $Id: load.cc,v 1.5 2010-12-25 19:34:43 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2008-2011 Stanislav Shwartsman
|
||||
@ -56,7 +56,18 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Eq(bxInstruction_c *i)
|
||||
}
|
||||
#endif
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Vss(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Ww(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
Bit16u val_16 = read_virtual_word(i->seg(), eaddr);
|
||||
BX_WRITE_XMM_REG_LO_WORD(BX_TMP_REGISTER, val_16);
|
||||
|
||||
BX_CPU_CALL_METHOD(i->execute2, (i));
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Wss(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
@ -67,7 +78,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Vss(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Vsd(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Wsd(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
@ -78,7 +89,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Vsd(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Vdq(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Wdq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
BxPackedXmmRegister op;
|
||||
@ -97,7 +108,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Vdq(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOADA_Vdq(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOADA_Wdq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
BxPackedXmmRegister op;
|
||||
@ -109,7 +120,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOADA_Vdq(bxInstruction_c *i)
|
||||
#endif
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOADU_Vdq(bxInstruction_c *i)
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOADU_Wdq(bxInstruction_c *i)
|
||||
{
|
||||
#if BX_CPU_LEVEL >= 6
|
||||
BxPackedXmmRegister op;
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: mmx.cc,v 1.97 2010-12-25 17:04:36 sshwarts Exp $
|
||||
// $Id: mmx.cc,v 1.98 2010-12-25 19:34:43 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2002-2009 Stanislav Shwartsman
|
||||
// Copyright (c) 2002-2010 Stanislav Shwartsman
|
||||
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
|
||||
//
|
||||
// This library is free software; you can redistribute it and/or
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: xmm.h,v 1.35 2010-12-25 07:59:15 sshwarts Exp $
|
||||
// $Id: xmm.h,v 1.36 2010-12-25 19:34:43 sshwarts Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (c) 2003-2010 Stanislav Shwartsman
|
||||
@ -105,6 +105,10 @@ typedef union bx_xmm_reg_t {
|
||||
#define BX_WRITE_XMM_REG_LO_DWORD(index, reg32) \
|
||||
{ (BX_CPU_THIS_PTR xmm[index]).xmm32u(0) = (reg32); }
|
||||
|
||||
/* store only low 16 bit of the register, rest of the register unchanged */
|
||||
#define BX_WRITE_XMM_REG_LO_WORD(index, reg16) \
|
||||
{ (BX_CPU_THIS_PTR xmm[index]).xmm16u(0) = (reg16); }
|
||||
|
||||
|
||||
/* MXCSR REGISTER */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user