Stanislav Shwartsman
75bda1d5cd
implemented SVM emulation support for Bochs (incomplete yet)
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I am merging the code in order to start making shortcuts between VMX emulation and SVM emulation.
Of course SVM emulation is incomplete, completely untested and not expected to work.
But someone could already take a look one the code and give some suggestions.
Also looking for anybody with existing SVM kernels - as simple as possible - for testing.
Status:
- exceptions intercept is not implemented yet
- IO intercept is not implemented yet
- MSR intercept is not implemented yet
- virtual interrupts are not implemented yet
- CPUID is not implemented yet
No advanced SVM featurez planned - I am implementing the very basic 'Pacifica' document from 2005 using QEMU code as reference.
2011-12-25 19:35:29 +00:00
Stanislav Shwartsman
9be8552b80
- Implemented VM Functions support and EPTP-Switching VM Functions
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- Added VMEXIT conditions for INVPCID instruction
Now Bochs is fully aligned with latest pulished Intel's SDM rev040.
2011-11-05 07:31:51 +00:00
Stanislav Shwartsman
5cc04b9955
Implemented AMDs Buldozer XOP and TBM extensions.
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XOP: few instructions are still missing, coming soon
BX_PANIC(("VPERMILPS_VpsHpsWpsVIbR: not implemented yet"));
BX_PANIC(("VPERMILPD_VpdHpdWpdVIbR: not implemented yet"));
BX_PANIC(("VPMADCSSWD_VdqHdqWdqVIbR: not implemented yet"));
BX_PANIC(("VPMADCSWD_VdqHdqWdqVIbR: not implemented yet"));
BX_PANIC(("VFRCZPS_VpsWpsR: not implemented yet"));
BX_PANIC(("VFRCZPD_VpdWpdR: not implemented yet"));
BX_PANIC(("VFRCZSS_VssWssR: not implemented yet"));
BX_PANIC(("VFRCZSD_VsdWsdR: not implemented yet"));
2011-10-19 20:54:04 +00:00
Stanislav Shwartsman
e000b61cfd
make RDTSC 'end of trace' instruction - guarantee that any pair ot RDTSC/RDTSCP on same CPU do not belong to same trace (and therefore will always update time and etc) - required for Win7 Thin
2011-09-06 14:13:39 +00:00
Stanislav Shwartsman
44241a1e56
- Added support for AVX and AVX2 instructions emulation, to enable configure
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with --enable-avx option. When compiled in, AVX still has to be enabled
using .bochsrc CPUID option. AVX2 FMA instructions still not implemented.
- Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
instructions support can be enabled using .bochsrc CPUID option.
2011-08-27 13:47:16 +00:00
Volker Ruppert
c78026a9a2
- deleted executable properties from source files
2011-04-03 10:29:19 +00:00
Stanislav Shwartsman
f0a3cce1e2
added XSAVEOPT instruction emulation (for now with no state tracking according to Intel docs, just alias it to XSAVE)
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update CHANGES
2011-03-25 20:32:07 +00:00
Stanislav Shwartsman
7ced718040
implemented AVX instructions support
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many changes - some cleanup will follow
please report ay found bugs !
2011-03-19 20:09:34 +00:00
Stanislav Shwartsman
5a8c57fe65
end trace on setbv instruction
2011-02-25 15:19:12 +00:00
Stanislav Shwartsman
7d80a6ebe0
Adding Id and Rev property to all files
2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
2d3f3668c7
Fixed IRET 64-bit mode bug
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Support for 32 float copare methods for AVX
ckeanups in fetchdecode
2011-02-13 06:10:11 +00:00
Stanislav Shwartsman
a31103e7d8
optimize fetchdecode tables - part2
2011-01-21 16:07:51 +00:00
Stanislav Shwartsman
fbc9b8b190
phase1 of opcode tables optimization
2011-01-20 16:24:42 +00:00
Stanislav Shwartsman
040a8e1a3a
split bunch of SSE opcodes
2010-12-24 08:35:00 +00:00
Stanislav Shwartsman
43600f3756
complete rework of SSE code
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next step - split all SSE opcodes by ModC0
2010-12-22 21:16:02 +00:00
Stanislav Shwartsman
29a674e520
split rd/wr CR opcodes for simplicity
2010-12-19 22:36:19 +00:00
Stanislav Shwartsman
91ac0df65c
implemented GS/FS BASE access instructions published in _319433-007.pdf document
2010-07-22 16:41:59 +00:00
Stanislav Shwartsman
3dfcfd0ccd
Split shift opcodes | optimize SAR opcode
2010-05-18 07:28:05 +00:00
Stanislav Shwartsman
7319d2eee1
FENCE instructions are SSE2 only
2010-04-18 09:21:24 +00:00
Stanislav Shwartsman
62b5c27e1b
compilation fixes
2010-04-07 14:49:18 +00:00
Stanislav Shwartsman
9cece96d14
fixes
2010-04-04 18:46:03 +00:00
Stanislav Shwartsman
c201a53c76
cleanup and optimization
2010-02-15 14:04:48 +00:00
Stanislav Shwartsman
7f7b2cfcf0
cleanup
2010-02-08 15:22:53 +00:00
Stanislav Shwartsman
a2a080894b
split fetchdecode.h for better readability
2010-02-08 10:39:30 +00:00
Stanislav Shwartsman
eae084920a
optimized decode tables
2010-01-31 09:45:27 +00:00
Stanislav Shwartsman
dc02d836ce
Fix POPCNT decode tables
2010-01-29 10:16:28 +00:00
Stanislav Shwartsman
c403090327
! Implemented PCLMULQDQ AES instruction
2009-12-20 09:00:40 +00:00
Stanislav Shwartsman
553ca8af01
split more SSE ops
2009-11-25 20:49:47 +00:00
Stanislav Shwartsman
6819ab4eb7
split sse opcodes
2009-11-23 18:21:23 +00:00
Stanislav Shwartsman
868e716411
instrumentation fixes + new example
2009-11-04 15:48:28 +00:00
Stanislav Shwartsman
78e4b3d616
split SSE move instructions
2009-10-24 11:17:51 +00:00
Stanislav Shwartsman
7254ea36a1
copyright fixes + small optimization
2009-10-14 20:45:29 +00:00
Stanislav Shwartsman
8e3276cf14
split opcodes by ModC0
2009-08-22 11:47:42 +00:00
Stanislav Shwartsman
d5b93041e4
added prefixSSE for few opcodes
2009-08-15 15:43:40 +00:00
Stanislav Shwartsman
867ef05705
The same for G15R
2009-05-16 09:26:16 +00:00
Stanislav Shwartsman
9339740d8b
G15M have SSE prefix style
2009-05-16 09:11:14 +00:00
Stanislav Shwartsman
6dac964b27
Two more prefix66 opcodes
2009-02-28 09:28:18 +00:00
Stanislav Shwartsman
b9de22961c
minimize SSE tables, minor speedup in SSE code
2009-02-26 21:57:01 +00:00
Stanislav Shwartsman
de5814a22d
Fixed compilation err
2009-01-31 15:01:29 +00:00
Stanislav Shwartsman
f8185a6bc6
Added Intel VMX emulation to Bochs CPU
2009-01-31 10:43:24 +00:00
Stanislav Shwartsman
0325c120b2
Separate PAUSE instruction from regular NOP
2009-01-27 20:29:05 +00:00
Stanislav Shwartsman
9929e6ed78
- updated FSF address
2009-01-16 18:18:59 +00:00
Stanislav Shwartsman
0ff68a2aa2
Fixed XSAVE decode in x86-64 mode
2009-01-10 16:01:55 +00:00
Stanislav Shwartsman
7566faf948
A bit simplify FPU decoding
2008-09-16 18:28:53 +00:00
Stanislav Shwartsman
a0e395188f
Fixed merge error
2008-08-29 20:43:05 +00:00
Stanislav Shwartsman
b96f78dc0a
Some kind of big change in fetchdecode tables invented in order to compress the tables for better host data cache utilization
2008-08-29 19:23:03 +00:00
Stanislav Shwartsman
70c7c5ceca
Use LOAD_Eb approach to remove duplicated GbEb methods
2008-08-11 20:34:05 +00:00
Stanislav Shwartsman
a8adb36dc2
Implemented MOVBE Intel Atom(R) instruction
2008-08-11 18:53:24 +00:00
Stanislav Shwartsman
b61017e5b6
Split more opcodes using new LOAD technique
2008-08-10 21:16:12 +00:00
Stanislav Shwartsman
0d90ab0478
Completely new way to handle LD+OP cases - allows to significantly reduce number of BX_CPU_C methods
2008-08-09 21:05:07 +00:00
