Stanislav Shwartsman
ff79cbd596
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
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The end goal will be also merging of disasm and cpu decoder to one module and remove the disasm.
Two bug fixes on the way:
TBM: fixed 64-bit TBM instructions with memory access (did 32-bit load instead of 64-bit)
BMI2: fixed operands order for PEXT/PDEP instructions
AVX2: fixed gather instruction decoding bug from decoder alias commit
2013-09-24 05:21:00 +00:00
Stanislav Shwartsman
33a7063e60
bug fixes
2013-08-05 15:33:41 +00:00
Stanislav Shwartsman
0da1d659d3
CMPXHG should always write to memory dest - affects APIC virtualization VMEXIT conditions
2013-07-24 21:06:24 +00:00
Stanislav Shwartsman
cc694377b9
Standartization of Bochs instruction handlers.
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Bochs instruction emulation handlers won't refer to direct fields of instructions like MODRM.NNN or MODRM.RM anymore.
Use generic source/destination indications like SRC1, SRC2 and DST.
All handlers are modified to support new notation. In addition fetchDecode module was modified to assign sources to instructions properly.
Immediate benefits:
- Removal of several duplicated handlers (FMA3 duplicated with FMA4 is a trivial example)
- Simpler to understand fetch-decode code
Future benefits:
- Integration of disassembler into Bochs CPU module, ability to disasm bx_instruction_c instance (planned)
Huge patch. Almost all source files wre modified.
2012-08-05 13:52:40 +00:00
Stanislav Shwartsman
f5d55f5eb6
- Implemented Task Switch intercept in SVM, cleanup in task switch handling code
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- Changed (c) year in several cpu files
- Cleanup and indent fixes in VMX code
2012-01-11 20:21:29 +00:00
Stanislav Shwartsman
2900956327
Split back some frequently used arithmetic and logic opcodes (which were done as Load+Op before).
2012-01-09 13:09:59 +00:00
Stanislav Shwartsman
02e1a0f23c
Merge lazy flags optimization by Darek Mihocka.
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I measure slight but consistent speedup of ~1-3% for all guests.
Tested: Windows XP/7 boot 32/64 bit, various Linux live CD
2011-09-12 19:36:53 +00:00
Stanislav Shwartsman
002c86660a
reword all the CPU code in preparation for future CPU speedup implementation.
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Bochs emulation can be another 10-15% faster using technique described in paper
"Fast Microcode Interpretation with Transactional Commit/Abort"
http://amas-bt.cs.virginia.edu/2011proceedings/amasbt2011-p3.pdf
2011-07-06 20:01:18 +00:00
Stanislav Shwartsman
a02d8cfe67
cleanups, simplications, copyright updates
2011-04-23 20:39:27 +00:00
Stanislav Shwartsman
7d80a6ebe0
Adding Id and Rev property to all files
2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
5915d92775
very small optimizations + indent
2011-01-25 20:59:26 +00:00
Stanislav Shwartsman
d60b7c0919
rename accessor for opcodeReg() in instruction
2010-12-06 21:45:56 +00:00
Stanislav Shwartsman
cffe32dd2c
remove unused param from exception() call
2010-03-14 15:51:27 +00:00
Stanislav Shwartsman
927c3594d6
enable compilation with CPU_LEVEL <= 6
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converted SEP to runtime option as well
2010-02-26 11:44:50 +00:00
Stanislav Shwartsman
bd60e0264c
change Copyright to Bochs Project
2009-12-04 16:53:12 +00:00
Stanislav Shwartsman
9929e6ed78
- updated FSF address
2009-01-16 18:18:59 +00:00
Stanislav Shwartsman
0d90ab0478
Completely new way to handle LD+OP cases - allows to significantly reduce number of BX_CPU_C methods
2008-08-09 21:05:07 +00:00
Stanislav Shwartsman
5dd02b26e3
Make even more efficient RmAddr calculation - good optimizing compiler could make more efficient code than it was before
2008-08-08 09:22:49 +00:00
Stanislav Shwartsman
709d74728d
Call #UD exception directly instead of UndefinedOpcode function - for future use
2008-07-13 15:35:10 +00:00
Stanislav Shwartsman
0127415ba6
Clear some duplicated arithmetic opcodes - difference only in operands order
2008-07-13 09:59:59 +00:00
Stanislav Shwartsman
48d45518eb
Fixed CMPXCHG code bug from yesterday
2008-05-06 05:06:32 +00:00
Stanislav Shwartsman
eedf26627f
Fixes in CMPXHG8B instruction - slight speedup and correct #AC check
2008-05-05 21:48:07 +00:00
Stanislav Shwartsman
2aaafa76a2
Reorganize fetchdecode tables with another level of redirection - a leap toward future improvements
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Currently no speedup and no slowdown - about the same results on my Bochs benchmarking
A lot of code reorganization in fetchdecode
2008-04-04 22:39:45 +00:00
Stanislav Shwartsman
167c7075fb
Use fastcall gcc attribute for all cpu execution functions - this pure "compiler helper" optimization brings additional 2% speedup to Bochs code
2008-03-22 21:29:41 +00:00
Stanislav Shwartsman
37fbb82baa
Cleanups. Move bxInstruction_c definition to separate file instr.h
2008-01-29 17:13:10 +00:00
Stanislav Shwartsman
7b80c5f481
I merged and succeded to remove some similar execution functions - less code, less chance for branch misprediction
2008-01-25 19:34:30 +00:00
Stanislav Shwartsman
d9984bb3a1
Eliminate BxResolve call from the heart of cpu loop and move into instructions that really require this calculation. Yes, it blows the code of EVERY CPU method but it has >15% speedup !
2008-01-10 19:37:56 +00:00
Stanislav Shwartsman
d891f0d8ec
Fixed more VC2008 warnings - hopefully last ones
2007-12-30 17:53:12 +00:00
Stanislav Shwartsman
838fb2a048
Fixing V2008 warnings - they found a bug in sse_pfp.cc !
2007-12-23 17:21:28 +00:00
Stanislav Shwartsman
5d4e32b8da
Avoid pointer params for every read_virtual_* except 16-byte SSE and 10-byte x87 reads
2007-12-20 20:58:38 +00:00
Stanislav Shwartsman
b516589e4e
Changes in write_virtual_* and pop_* functions -> avoid moving parameteres by pointer
2007-12-20 18:29:42 +00:00
Stanislav Shwartsman
6ac7fa7106
MMX - modify masked write to RMW - faster execution
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CMPXCHG8B/16B - fixed possible problem. Instruction not allowed to fault after some part of it written to the memory
2007-12-19 23:21:11 +00:00
Stanislav Shwartsman
88899cf617
Changes for lazy flags handling -> 1st stap in transition to new lazy flags handling by Darek Mihocka (www.emulators.com)
2007-12-04 19:27:23 +00:00
Stanislav Shwartsman
dbfa7a51e9
Do not affect CPU state if any exception occured - in this case do not write to MEM and flags
2007-12-03 20:48:02 +00:00
Stanislav Shwartsman
7ca78b88e9
configure/compile changes + small optimizations
2007-12-01 16:45:17 +00:00
Stanislav Shwartsman
0a1063ad77
Split GvEv opcode groups
2007-11-21 22:36:02 +00:00
Stanislav Shwartsman
1af7010e50
Optimized memory access for 64-bit mode
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Starting convergence to new lazy flags scheme by Darek Mihocka (www.emulators.com). The new flags code is still being validated and perfected but I try to minimize the diff between 2 versionS
2007-11-20 17:15:33 +00:00
Stanislav Shwartsman
cdc9a09090
Split more opcodes
2007-11-18 18:24:46 +00:00
Stanislav Shwartsman
5ec15df46d
Split more opcodes EbIb opcodes
2007-11-17 18:08:46 +00:00
Stanislav Shwartsman
d5a58e1df2
Split more opcodes - G3 group
2007-11-17 16:20:37 +00:00
Stanislav Shwartsman
d9e58bd598
split11b on opcode tables level - split almost eevery splittable instruction
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will be continued
2007-11-17 12:44:10 +00:00
Stanislav Shwartsman
393018cdf8
More split11b
2007-11-16 17:45:58 +00:00
Stanislav Shwartsman
351244d1ea
Rename splitmod11b methods
2007-11-16 08:30:22 +00:00
Stanislav Shwartsman
dc5c25133f
Fixes in registers read/write -> fixed zero upper of register in POP_Ed
2007-11-13 21:07:08 +00:00
Stanislav Shwartsman
494189e822
Small optimization for ADD lazy flags calculations.
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Because most likely flags are not needed after ADD instruction - it is better to store less data for lazy flags and reconstruct it if needed
2007-11-06 08:39:25 +00:00
Stanislav Shwartsman
5a172541e2
Small cleanup
2007-11-01 20:43:53 +00:00
Stanislav Shwartsman
68ef783632
reduce amount of used temp variables
2007-10-21 23:35:11 +00:00
Stanislav Shwartsman
42fdd8a3a1
During Bochs benchmarking I figured out that hostasm actually slow down the emulation ... so remove this ugly code which also doesn't help :)
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speedup flags update for some instructions - idea was taken from DT patch by h.johansson
2007-10-21 22:07:33 +00:00
Stanislav Shwartsman
8221fa6838
- Fixed zero upper 32-bit part of GPR in x86-64 mode
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- CMOV_GdEd should zero upper 32-bit part of GPR register even if the
'cmov' condition was false !
2007-01-26 22:12:05 +00:00
Stanislav Shwartsman
da3d26d7f4
Preliminary implemntation of SMM save statei
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Fixed fetchModeMask for load32bitOsStack
2006-03-27 18:02:07 +00:00
