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3657 Commits

Author SHA1 Message Date
Stanislav Shwartsman
bf16e720f8 add faststring mode for REP MOVSW in 32-bit mode 2019-10-14 18:12:37 +00:00
Stanislav Shwartsman
fe7acbb6a0 more faststring cleanup 2019-10-14 14:54:07 +00:00
Stanislav Shwartsman
ee3f1b91a3 allow fast string only for forward strings and simplify the code 2019-10-14 14:45:01 +00:00
Stanislav Shwartsman
f0245b5f2b introduce special handlers for zero-idiom instructions - ~1% speedup to simulation. infra for fast string emulation in 64-bit mode 2019-10-14 06:40:19 +00:00
Stanislav Shwartsman
d6e08702e4 add Icelake-U model to CPUDB database. TODO: verify its VMX features 2019-09-24 20:26:14 +00:00
Stanislav Shwartsman
2ae332cce8 patch by Luigu.B - significantly speedup multi-threaded guest simulation 2019-08-09 19:57:13 +00:00
Stanislav Shwartsman
2eb47f866f added minor clarifications based on most recent AMD SDM published 2019-07-30 18:17:21 +00:00
Stanislav Shwartsman
49ebaf8397 typofix: attached MASK_K0 attr to wrong opcode 2019-05-25 19:10:55 +00:00
Stanislav Shwartsman
bc4af1b08d add missing break statement in disasm.cc 2019-05-25 19:08:39 +00:00
Stanislav Shwartsman
4d10852c04 impemented recently published VP2INTERSECTD/Q instructions 2019-05-25 19:07:09 +00:00
Stanislav Shwartsman
85780d939a extract MONITOR/MWAIT stuff to separate trsnlation unit 2019-05-25 18:32:17 +00:00
Stanislav Shwartsman
55d2dc6b0c add some CPUID and VMCS definitions from latest SDM 2019-05-22 18:22:22 +00:00
Stanislav Shwartsman
0c28705b18 fixed compilation under MAC env 2019-05-18 04:50:07 +00:00
Stanislav Shwartsman
662b252507 added missing endif 2019-04-17 16:04:34 +00:00
Stanislav Shwartsman
a022d71774 fixed compilation 2019-04-14 04:05:04 +00:00
Stanislav Shwartsman
54bdb24e4b remove MOVDIRI opcode extension for now until fugured out how nicely do MOVDIR64B, they better to be both done with same CPUID feature name 2019-02-22 19:15:53 +00:00
Stanislav Shwartsman
3e007fbdea fixed copy-pasted issue with decoding 2019-02-17 21:54:38 +00:00
Stanislav Shwartsman
c3f7a34cf5 fixed copy-pasted issue with decoding 2019-02-17 21:41:45 +00:00
Stanislav Shwartsman
3da93728b3 split some opcode reference tables in new decoder between x86-64 and 32 for better perf 2019-02-17 21:22:54 +00:00
Stanislav Shwartsman
cd79d22113 fixes for 32-bit mode only compilation 2019-02-16 19:42:04 +00:00
Stanislav Shwartsman
bfd7bb2c13 remove redundant VL512 runtime check, redundant with new decoder 2019-02-16 19:25:32 +00:00
Stanislav Shwartsman
4f625b23e0 enable yet another Bochs new decoder. It is a bit slower than old one but it is much more extendable so adding new opcode won't be nightmare anymore 2019-02-16 15:23:24 +00:00
Stanislav Shwartsman
61dcc4ace7 remove unreferenced decode table 2019-01-29 13:44:39 +00:00
Stanislav Shwartsman
f8ec18acd5 fix decode/disasm of AVX512-VBMI2 VPSH*D* opcodes 2019-01-27 18:52:03 +00:00
Stanislav Shwartsman
0b18a42e4e fixed decoding of AVX-512 opcodes 2019-01-27 17:35:21 +00:00
Stanislav Shwartsman
5cb4639891 fixed decoding of AVX-512 opcodes 2019-01-27 17:31:28 +00:00
Stanislav Shwartsman
6dc5cfe80b fixed typo in opcode name 2019-01-24 20:10:46 +00:00
Stanislav Shwartsman
af75c2a81e fixed comment in the opcode table for EVEX 2019-01-22 18:31:39 +00:00
Stanislav Shwartsman
9bc7faf493 dump all supported CPU fetures into Bochs log from CPUID object 2019-01-05 20:17:39 +00:00
Stanislav Shwartsman
264b797363 fixed compilation without VMX=2 2019-01-03 06:28:15 +00:00
Stanislav Shwartsman
098791bf95 report MONITOR/MWAITX for Ryzen configuration in CPUID 2018-12-01 12:15:57 +00:00
Stanislav Shwartsman
7a183ab520 fixed PDE4M reserved bits checking if physical address wider than 40 bit 2018-11-22 11:51:33 +00:00
Stanislav Shwartsman
eff201773f convert some defines to enums and const expressions 2018-11-17 12:45:44 +00:00
Stanislav Shwartsman
e387876145 Enable PML VMX feature in Skylake-X 2018-10-26 19:54:22 +00:00
Stanislav Shwartsman
2e192372c0 fixes for CNL CPUID 2018-10-26 19:46:56 +00:00
Stanislav Shwartsman
a9aa1040c1 add Intel Cannonlake CPU model to CPUDB featuring AVF512FMA52 and SHA instructions 2018-10-26 09:23:58 +00:00
Stanislav Shwartsman
cf41679b53 closing bug report: Missing TLB_flush on VMX_VMEXIT_EPT_VIOLATION 2018-08-30 20:18:27 +00:00
Stanislav Shwartsman
3995dc13aa fixed compilation of CLZERO pn cpu-level<6 2018-08-26 18:11:10 +00:00
Stanislav Shwartsman
965bcc2606 support 64-bit in 'info tab' debugger command and also speed it up significantly 2018-08-14 08:09:09 +00:00
Stanislav Shwartsman
eebdb4d63a avoid gcc 7.3 warning 2018-05-27 19:09:59 +00:00
Stanislav Shwartsman
a8413aa838 update comments base on latest AMD spec 2018-05-27 18:13:24 +00:00
Stanislav Shwartsman
fcd9ce1634 fix compilation without x86_64 2018-04-15 14:22:16 +00:00
Stanislav Shwartsman
d000e21001 added MOVDIRI opcode implementation 2018-04-06 05:06:36 +00:00
Stanislav Shwartsman
fd15b61d94 keep def of YMM/ZMM register even if AVX or EVEX are not compiled in and let reading/writing them to MEM 2018-04-04 19:31:56 +00:00
Stanislav Shwartsman
8c9f7f54b6 update CPUID definitions with recently published EAS-33 extensions document 2018-04-04 18:15:44 +00:00
Stanislav Shwartsman
0cd49ddae4 fixed compilation with EVEX disabled 2018-03-29 08:50:38 +00:00
Stanislav Shwartsman
773f1b7e42 cleanup return value of all instruction handlers 2018-02-16 07:57:32 +00:00
Stanislav Shwartsman
2bca4cc310 improve debug print for SPP access 2018-01-27 21:25:46 +00:00
Stanislav Shwartsman
afc2ee6bfd Implemented SPP: EPT-Based Subpage Protection. Cleaned code duplication between FXSAVE/FXRSTORE and XSAVE/XRSTOR (save/restore of SSE code is the same) 2018-01-27 21:20:33 +00:00
Stanislav Shwartsman
a9ac81e092 convert defines to const and enum in paging.cc 2018-01-27 19:31:39 +00:00
Stanislav Shwartsman
769ed3ef88 fixed MOVBE instruction decoding 2018-01-23 19:53:34 +00:00
Stanislav Shwartsman
7d1a524ff0 fix indentation after tab2space 2018-01-11 08:47:02 +00:00
Stanislav Shwartsman
6d93ba14ec tab2space 2018-01-11 08:45:00 +00:00
Stanislav Shwartsman
3c08cfedf2 fixed buffer overflow when printing instruction disasm for opcode bytes which cannot be decoded 2017-12-31 21:22:04 +00:00
Stanislav Shwartsman
6566cab8aa fixed new disasm for avx2 opcodes 2017-12-30 18:45:21 +00:00
Stanislav Shwartsman
4c03fe3e2c fixed disasm of vcvtps2ph/ph2ps opcodes 2017-12-28 19:59:42 +00:00
Stanislav Shwartsman
27a7925810 fix for MOV to CR3 in long mode with PCID enabled - patch by Kent Williams 2017-12-25 19:49:45 +00:00
Stanislav Shwartsman
ed8fa8ac61 fix compilation with no AVX enabled 2017-12-24 15:38:21 +00:00
Stanislav Shwartsman
ca034f0642 fixed disasm of sse insertps instruction 2017-12-21 18:18:10 +00:00
Stanislav Shwartsman
59c542fb06 fix disasm of FISTTP opcodes 2017-12-19 20:36:55 +00:00
Stanislav Shwartsman
4337a062e2 disasm memsize for gather opcodes 2017-12-19 19:51:55 +00:00
Stanislav Shwartsman
15187110ef implement disasm of implicit memory reference for maskmovdqu/maskmovq opcodes. fix vmaskmovdqu disasm for legacy disasm as well 2017-12-19 19:45:30 +00:00
Stanislav Shwartsman
e086f7ba19 split INSERTPS opcode to reg and mem forms 2017-12-19 19:25:40 +00:00
Stanislav Shwartsman
ce3eafa535 disasm fix 2017-12-17 18:47:21 +00:00
Stanislav Shwartsman
79ec183ff6 fixup for MMX opcodes disasm 2017-12-17 17:21:02 +00:00
Stanislav Shwartsman
5dc5e01a12 disasm fixes and reorg of pinsr* opcodes 2017-12-16 18:34:20 +00:00
Stanislav Shwartsman
6a4e8ff2f1 fixed typo in prev commit 2017-12-13 21:08:10 +00:00
Stanislav Shwartsman
f362f34ed6 correctly decode PINSRQ instruction 2017-12-13 20:59:41 +00:00
Stanislav Shwartsman
50a799ea11 split handlers for PINSRD/Q opcodes. fix disasm for MULX instruction 2017-12-13 20:18:59 +00:00
Stanislav Shwartsman
07bff3be43 fixed decoding of VPINSRB/W/D/Q and VINSERTPS with EVEX prefix 2017-12-13 20:02:12 +00:00
Stanislav Shwartsman
8a311515dd correctly decode VPEXTRB/W/D/Q - these opcodes allowed to be with VEX.L=0 only 
fixed disasm module compilation with no AVX enabled
remove duplicate opcode handlers
 2017-12-13 19:51:25 +00:00
Stanislav Shwartsman
2f3c9d3c8c correct disasm for movsxd opcode 2017-12-13 18:44:13 +00:00
Stanislav Shwartsman
c1dc514c2a clarify disasm of movlhps/movhlps opcodes 2017-12-12 08:55:09 +00:00
Stanislav Shwartsman
fd953421f4 new disasm: add correct memaccess size for FLDCW 2017-12-11 19:58:09 +00:00
Stanislav Shwartsman
a84d9cf1c7 disasm: fix crc32 operand description 2017-12-11 19:45:50 +00:00
Stanislav Shwartsman
a028ef7c9c bugfix for decoder with EVEX enabled 2017-12-11 19:29:11 +00:00
Stanislav Shwartsman
e46f37b40e fixed disasm of memsize for sse legacy instructions 2017-12-11 18:33:33 +00:00
Stanislav Shwartsman
404a5f2c53 bugfix for previous commit 2017-12-11 16:41:48 +00:00
Stanislav Shwartsman
b03f78d652 updates for bochs decoder and decoder based disasm 2017-12-11 15:45:43 +00:00
Stanislav Shwartsman
c80e587ded properly handle kmask registers in modrm form 2017-12-05 19:33:23 +00:00
Stanislav Shwartsman
8f15cfb514 fixed link err with debugger enabled 2017-12-05 19:23:41 +00:00
Stanislav Shwartsman
31ea453921 fixed bogus assert 2017-12-02 16:40:03 +00:00
Stanislav Shwartsman
eaa05c32e8 link without LOGIO for standalone decoder mode 2017-12-01 21:27:30 +00:00
Stanislav Shwartsman
60591800f1 handle lock mov cr0 amd feature out decoder critical path 2017-12-01 21:18:16 +00:00
Stanislav Shwartsman
01067cb4b9 another compilation fix for new disasm stand-alone module 2017-11-29 19:24:00 +00:00
Stanislav Shwartsman
a7e58973ce fixed typo 2017-11-27 20:26:54 +00:00
Stanislav Shwartsman
c8d9aeb377 mark blocks of code which not supposed to be compiled for stand-alone bochs cpu decoder 2017-11-27 20:25:04 +00:00
Stanislav Shwartsman
cef6c7fb98 fix for new disasm 2017-11-26 19:38:58 +00:00
Stanislav Shwartsman
596b3b6eb8 reduce CPU dependencies from fetchdecode module 2017-11-25 20:20:34 +00:00
Stanislav Shwartsman
0c604d27d1 fixed compilation with no PKEYS enabled 2017-11-12 20:15:48 +00:00
Stanislav Shwartsman
875c38a05c POPFD/POPFQ always clear RF flag (instead of reading it from stack image) 2017-11-11 12:27:50 +00:00
Stanislav Shwartsman
045a1cd637 XSAVEC/XSAVES should be supported in SKL-X CPUID 2017-11-11 12:04:26 +00:00
Stanislav Shwartsman
180386cd74 VMOVSS/VMOVSD are VEX.VL ignore form and not VEX.L0 2017-11-11 11:58:07 +00:00
Stanislav Shwartsman
f89b8a2742 fixed opcode of ADOX instr 2017-11-11 10:42:21 +00:00
Stanislav Shwartsman
8261a91ce9 implemented GFNI instructions 2017-10-21 19:57:12 +00:00
Stanislav Shwartsman
b7f62a291c fixed compressed displ form for more avx512 instructions 2017-10-20 19:41:32 +00:00
Stanislav Shwartsman
da8d6e793f fixed compilation issues 2017-10-20 19:24:10 +00:00
Stanislav Shwartsman
bca076889b decode all the vbmi2 opcodes, fix vpcompress/vpexpand instruction handler names (affects disasm) 2017-10-20 18:50:10 +00:00
Stanislav Shwartsman
77a62a4dcd implemented (experimental, still untested) AVX512 VBMI2 extensions 2017-10-20 18:38:15 +00:00
Stanislav Shwartsman
0afbb6cd3d fixed compilation when AVX is not configured in 2017-10-20 12:27:42 +00:00
Stanislav Shwartsman
5439647254 small change to extract ia_opcodes.h from instr.h to dedicated file. this would remove compilation dep of all files on ia_opcodes.h (now called ia_opcdes.def). regenerating dep ober all files in Makefiles.in 2017-10-19 21:27:25 +00:00
Stanislav Shwartsman
ba1e5bbffa fixed accidentially broken XMM versions of AES instrructions 2017-10-19 20:25:05 +00:00
Stanislav Shwartsman
15ba88c195 implemented VAES/VPCLMULDQ instructions - VEX/EVEX extensions of AES/PCLMULQDQ 2017-10-19 19:12:55 +00:00
Stanislav Shwartsman
ac442009aa lazy flags code small refactoring 2017-10-15 22:01:32 +00:00
Stanislav Shwartsman
6daa1ba9ba fixed compilation issue with EVEX enabled 2017-10-15 20:40:56 +00:00
Stanislav Shwartsman
944f37b1f2 implemented AVX-512 BITALG instructions/bugfix for VPOPCNT instructions 2017-10-15 20:33:19 +00:00
Stanislav Shwartsman
0d190eec8e implemented AVX-512 VNNI instructions 2017-10-15 19:17:07 +00:00
Stanislav Shwartsman
4179e6f939 add some const 2017-10-14 18:42:12 +00:00
Stanislav Shwartsman
69f27439db added new cpuid flags mentioned in new Intel SDM future extensions rev030 doc 2017-10-13 20:27:52 +00:00
Stanislav Shwartsman
2d3d62db5f cleaned cr2 print in 32-bit mode 2017-08-22 21:14:39 +00:00
Stanislav Shwartsman
2a55ba0a39 Merge set of debugger improvements by Doug Gale <doug16k> 
Here is his original comment:

I have made several improvements in the debugger.
I have fixed several issues with proper handling of 64-bit addresses, and added support for 64 bit symbols.
I also have added several symbol lookups.
 2017-08-22 21:03:58 +00:00
Stanislav Shwartsman
f490b00beb added support for conditional breakpoints in Bochs debugger 2017-08-22 18:47:18 +00:00
Stanislav Shwartsman
7f4a9b4b08 skylake CPUID should compile also with no EVEX 2017-08-09 21:04:15 +00:00
Stanislav Shwartsman
7f01a7d9b6 remove obsolete comment 2017-08-09 20:37:43 +00:00
Stanislav Shwartsman
b2fdbd1274 added Skylake-X model to CPUDB -> with EVEX and AVX512 support 2017-08-09 20:36:17 +00:00
Stanislav Shwartsman
54e969b749 disasm update 2017-06-05 21:05:47 +00:00
Stanislav Shwartsman
20e9e33662 internal disasm updates 2017-06-05 20:49:04 +00:00
Stanislav Shwartsman
3f4f18de7a internal disasm updates 2017-06-05 20:28:33 +00:00
Stanislav Shwartsman
46ef85ce0f avoid using magic constants for disasm source metadata 2017-06-05 19:55:40 +00:00
Stanislav Shwartsman
555bb8f8b6 updates to prev commit 2017-06-01 08:41:41 +00:00
Stanislav Shwartsman
6ab4fd597b implement another form of AR field packing used in SKL, in addition on present NHM format 2017-06-01 08:31:20 +00:00
Stanislav Shwartsman
bde8a1f69d fixed ifdef typo 2017-06-01 07:48:54 +00:00
Stanislav Shwartsman
22e9051716 implemented correct VM-exit instruction information for INVPCID, RDRAND/RDSEED and XSAVES/XRSTORS instruction Vmexits 2017-05-31 13:16:49 +00:00
Stanislav Shwartsman
bb43ac527b fixed decoder issue when decoding opcode 8f (aka xop prefix) as well 2017-05-27 10:32:44 +00:00
Stanislav Shwartsman
54c109ceb4 VEX and EVEX opcodes should be considered as 2-byte opcode, always attempt to fetch 2nd byte even if #UD is already detected 2017-05-26 11:46:02 +00:00
Stanislav Shwartsman
af76e0c412 fixes for debugger and disasm 2017-05-10 18:31:59 +00:00
Stanislav Shwartsman
1ca366609f add memsize for non-evex memory refrences in disasm 2017-05-09 19:49:27 +00:00
Stanislav Shwartsman
f8abddafcf bugfix in disasm 2017-05-09 19:34:03 +00:00
Stanislav Shwartsman
1d48973c80 updates in fetchdecode.h to help automatic disasm to determined memaccess size 2017-05-09 12:06:02 +00:00
Stanislav Shwartsman
e357da9150 update (c) for fpu files 2017-05-05 21:09:27 +00:00
Stanislav Shwartsman
1abfcd39ff implement FOPCODE and FDP deprecation CPU features 2017-05-05 20:56:13 +00:00
Stanislav Shwartsman
fce7476bda convert magic defines into static const variables 2017-05-03 18:20:13 +00:00
Stanislav Shwartsman
3d51439090 fixed compilation err for CPU_LEVEL=5 2017-04-13 05:33:29 +00:00
Stanislav Shwartsman
1a3ff4b438 fixed bogus error message 2017-04-11 18:35:17 +00:00
Stanislav Shwartsman
bad84e48cd remove redundant memory access from IRET 2017-04-01 05:49:01 +00:00
Stanislav Shwartsman
e351aaa28a update (c) for tlb.h 2017-03-31 07:34:44 +00:00
Stanislav Shwartsman
a51eb1cc39 added more debug info for TLB through param tree, update year in the (c) 2017-03-31 07:34:08 +00:00
Stanislav Shwartsman
c9c3672509 allow monitor to UC memory type but not MONITORX 2017-03-31 07:00:36 +00:00
Stanislav Shwartsman
566a7aa82b fixed softfloat FUZ condition. fixed/optimized pmaddwd computing function 2017-03-30 22:11:38 +00:00
Stanislav Shwartsman
a6e7ffb284 implemented undefined flags behavior for SHRD instruction matching HW 2017-03-30 22:03:38 +00:00
Stanislav Shwartsman
097310cd00 fixed integer overflow while computing shift flags, avoid using bx_bool while working with flags for more robust code 2017-03-30 21:53:39 +00:00
Stanislav Shwartsman
862e817884 fixed typo caused compilation err 2017-03-28 19:13:20 +00:00
Stanislav Shwartsman
31d29734d6 some comments about more CPUID leaf 80000008.EBX by Ryzen 2017-03-28 19:11:42 +00:00
Stanislav Shwartsman
b7b0165d3c new naming convention for UD opcodes 2017-03-28 19:00:00 +00:00
Stanislav Shwartsman
a673612784 fixed permission checks performed by CLFLUSH/CLFLUSHOPT/MONITOR* instructions 2017-03-28 18:52:53 +00:00
Stanislav Shwartsman
e5c64b3b56 cleanup of warning messages from cpuid code 2017-03-26 20:12:14 +00:00
Stanislav Shwartsman
2b79061127 Implemented MONITORX/MWAITX instructions (AMD), enabled in Ryzen CPU model 2017-03-26 19:14:15 +00:00
Volker Ruppert
dd2d03ec0a The 'del' command doesn't like forward slashes, so the MSVC nmake 'clean' 
target skipped files in subfolders. Updated cpu makefile dependencies.
 2017-03-26 15:55:57 +00:00
Stanislav Shwartsman
411ea954b4 implemented CLZERO instruction from AMD Ryzen CPU 2017-03-25 20:12:31 +00:00
Volker Ruppert
9bef555f3e Updated build test script and fixed compilation without FPU. 2017-03-19 09:50:16 +00:00
Volker Ruppert
640f5e2ce9 Fixed compilation error. 2017-03-19 07:26:56 +00:00
Stanislav Shwartsman
2c5588cda0 convert some defines to enums and consts 2017-03-18 21:25:06 +00:00
Stanislav Shwartsman
2809e7f5ad fixed warnings in the cpu code 2017-03-18 07:32:17 +00:00
Stanislav Shwartsman
15d9b068a3 fix msvc warnings 2017-03-17 17:35:15 +00:00
Stanislav Shwartsman
99bfbdf139 add xss exiting bitmap to save/restore 2017-03-16 20:23:49 +00:00
Stanislav Shwartsman
3f80447a10 fixed compilation err with x86-64 disabled 2017-03-16 20:13:42 +00:00
Stanislav Shwartsman
be4c6c7ae5 SMAP opcodes are No-SSE-Prefix 2017-03-16 16:20:58 +00:00
Stanislav Shwartsman
172b0106ac imvent a bochs feature for AMD TCE and enable EFER.TCE bit 2017-03-15 22:52:08 +00:00
Stanislav Shwartsman
6edf22e754 finally figured out what TCE means in AMD CPUID - and it has EFER.TCE bit related to it 2017-03-15 22:48:27 +00:00
Stanislav Shwartsman
ebbf8f9e0f adjustments in AMD Ryzen CPUID 2017-03-15 22:14:10 +00:00
Stanislav Shwartsman
3a033fa6db implemented xsaves/xrstors extensions (supported by Intel Skylake core and AMD Ryzen) 2017-03-15 21:44:15 +00:00
Volker Ruppert
8796abeea6 Some fixes in the build system. 
- Makefile: cleanup of the 'clean' target (adds missing 'bxhub').
- configure script: create cpudb subdirectories if necessary for building
  outside of the source tree.
- cpudb Makefile: clean object files from new location.
 2017-03-15 16:51:32 +00:00
Stanislav Shwartsman
c0701a6d42 fixup for Ryzen cpuid 2017-03-13 20:23:39 +00:00
Stanislav Shwartsman
402e2cfad0 move cpuid warning messages to base cpuid class - reduce code cleanup 2017-03-13 19:59:48 +00:00
Stanislav Shwartsman
07166f14b7 reorg of cpudb folder, added AMD Ryzen CPUID placeholder module (still not 100% correct) 2017-03-13 19:44:14 +00:00
Stanislav Shwartsman
980eaa7937 move cpuid leaf 80000008 to base bx_cpuid_t class to remove code dupolication 2017-03-09 21:25:18 +00:00
Stanislav Shwartsman
8664f8f21e add vex.w into bxInstruction to be used in disasm 2017-01-28 19:25:30 +00:00
Stanislav Shwartsman
49c537521a simplify disasm code by splitting it into functions 2017-01-22 19:53:42 +00:00
Volker Ruppert
6cf6f6967a Fixed cpu "make clean" target. 2017-01-13 16:13:42 +00:00
Stanislav Shwartsman
af1d83f35d update (c) 2017-01-11 20:54:09 +00:00
Stanislav Shwartsman
521d2d10c4 correctly fixed x32 emu compilation err + bugfix for AVX decoder 2017-01-11 20:51:58 +00:00
Stanislav Shwartsman
72e5213ff4 compilation fix and code simplifcation 2017-01-11 19:12:06 +00:00
Stanislav Shwartsman
90c4cb31c5 add SVN header to newly added files 2017-01-10 20:16:24 +00:00
Stanislav Shwartsman
10eb193e01 step 1 of rewrite Bochs decoder: legacy decoder tables done. TODO: avx/evex decoder tables, merge decoder and disasm together 2017-01-10 20:15:17 +00:00
Stanislav Shwartsman
9bd99a604f implemented recently announced AVX-512 extension VPOPCNT 2016-12-17 13:47:45 +00:00
Stanislav Shwartsman
e613e9ff86 fixed compilation err when no AVX is enabled 2016-12-12 06:18:57 +00:00
Stanislav Shwartsman
7b2a8bb340 added missing EPT misconfig condition check 2016-12-10 05:06:59 +00:00
Stanislav Shwartsman
46b4a76cd3 fetchdecode rework step 0.1, no impact on correctness, small speedup 2016-12-09 12:34:37 +00:00
Stanislav Shwartsman
bd24d7fb17 fixed reset value of xcr0 as published in latest Intel SDM update 2016-10-08 15:17:12 +00:00
Stanislav Shwartsman
1543034fb7 in the latest intel docs PCOMMIT CPUID bit doesn't exists anymore 2016-10-02 11:56:18 +00:00
Stanislav Shwartsman
239f793f37 in the latest intel docs PCOMMIT CPUID bit doesn't exists anymore 2016-10-02 11:54:19 +00:00
Stanislav Shwartsman
42b0714992 rename fetchdecode.cc -> fetchdecode32.cc 2016-09-25 18:25:47 +00:00
Stanislav Shwartsman
d9e818cd5d refactoring in the Bochs decoder code 2016-09-25 18:19:59 +00:00
Stanislav Shwartsman
8f20cecbae fixed code style in fetchdecode.cc, avoid code duplication 2016-09-08 17:29:09 +00:00
Stanislav Shwartsman
b7091b09f6 cleanup in fetchdecode functions 2016-09-08 15:09:29 +00:00
Stanislav Shwartsman
14b7fff442 remove unexpected change in fetchdecode.cc 2016-08-30 18:43:36 +00:00
Stanislav Shwartsman
032da78e52 remove SMP and AVX from Android build script. reduce the binary size and make faster binary (SMP makes binary a lot slower) 2016-08-30 18:42:39 +00:00
Volker Ruppert
cd68194269 Added Android host platform support to Bochs based on SF patch #534. 
- added Android case to the configure script.
- renamed file memory.h to memory-bochs.h to fix conflict with NDK.
- fixed Android issues in some files.
 2016-08-12 17:06:14 +00:00
Stanislav Shwartsman
46e932d04e fixed INIT cpu state according to clarification published in SDM rev059 2016-07-17 19:16:58 +00:00
Stanislav Shwartsman
88637aa9ef fixed potential uninitialized variable access when decoding AVX/XOP/EVEX 2016-07-06 09:09:49 +00:00
Stanislav Shwartsman
6761495f7e second step if Bochs decoder refactoring: extracted assign_srcs code to separate methods 2016-07-05 20:42:25 +00:00
Stanislav Shwartsman
bccc0d40a3 more correct fix for load segment register instruction 2016-07-05 19:37:37 +00:00
Stanislav Shwartsman
2a98e7bc63 fixed decoder bug introduced in svn rev12927 2016-07-05 18:04:23 +00:00
Stanislav Shwartsman
152591469b bugfix in lfs/lgs in long mode, introduced in svn rev12923 2016-07-05 17:47:36 +00:00
Stanislav Shwartsman
033303399d properly set segment register for 64-bit decode 2016-07-03 20:07:16 +00:00
Stanislav Shwartsman
98da36a63f extract decoding of modrm into dedicated function in decoder 2016-07-03 19:51:33 +00:00
Volker Ruppert
586031ca9f Fixed makefile error. 2016-06-13 18:42:27 +00:00
Stanislav Shwartsman
7a34f00f99 extracted fetchdecode into separated folder under cpu and also out of BX_CPU_C class into stand-alone module. Next step: wrap it up nicely and define clear interace to CPU model to minimize dependencies. Ideally I need fetchdecode to not include CPU at all 2016-06-12 21:23:48 +00:00
Stanislav Shwartsman
8824539630 fix code duplication in segload instr emulation 2016-06-01 20:11:54 +00:00
Stanislav Shwartsman
09e6ee3143 compile disasm module when x86-64 is not compiled in 2016-05-12 11:16:05 +00:00
Stanislav Shwartsman
12ece81e19 look only on valid tlb entries in check_addr_in_tlb_buffers and tlb invalidation methods 2016-05-06 06:57:00 +00:00
Stanislav Shwartsman
dff5e9587b fixed SMP mode compilation err 2016-05-05 14:15:17 +00:00
Stanislav Shwartsman
009bc7388b implement more correct vmentry to shutdown sanity check 2016-05-03 19:29:22 +00:00
Stanislav Shwartsman
6a35ceb51a fixed err msg description 2016-05-03 19:24:52 +00:00
Stanislav Shwartsman
405d7776e8 fixed typo 2016-05-03 19:20:26 +00:00
Stanislav Shwartsman
e1532260e4 fixe compilation on cpu model missing cr4 2016-05-02 17:33:06 +00:00
Stanislav Shwartsman
e24c7e403a take a funtion from BX_CPU_C:: into fetchdecode.cc standalone function 2016-04-30 19:13:15 +00:00
Stanislav Shwartsman
793ceb0d8c fix massive code dupliction between disasm, debugger and cpu by introducing new cpu decoder.h header 2016-04-29 21:01:28 +00:00
Stanislav Shwartsman
cc49b504b3 fix small issue on the way to Bochs decoder separation into stand-alone module 2016-04-26 12:46:44 +00:00
Stanislav Shwartsman
ca5882b310 fixed compilation with cpu-level < 5 2016-04-21 15:39:49 +00:00
Stanislav Shwartsman
87cb831a37 fixed compilation w/o x86-64 enabled 2016-04-20 14:46:02 +00:00
Stanislav Shwartsman
adc143684b implemented Intel architecture extensions published in recently published SDM 058: 
! Implemented UMIP: User Mode Instruction Prevention (don't allow execution of SLDT/SIDT/SGDT/STR/SMSW with CPL>0)
! Implemented RDPID instruction

Bugfixes in RDPKRU/WRPKRU instructions implementation (Protection Keys feature)
 2016-04-15 11:35:32 +00:00
Stanislav Shwartsman
e4832af5ab clean pkeys when not enabled to avoid side-effects 2016-03-19 21:15:56 +00:00
Stanislav Shwartsman
5b481fe34d correctly set up pkeys when enabling through cr4 2016-03-19 19:48:38 +00:00
Stanislav Shwartsman
cbe50a9539 enable PKE bit in CR4 2016-03-16 19:44:24 +00:00
Stanislav Shwartsman
8fe26816dc recalculate protection keys if cr0.wp change 2016-03-04 11:59:32 +00:00
Stanislav Shwartsman
bcb36e81fa experimental implementation of protection keys paging extension published in SDM rev054. to enable configure with --enable-protection-keys 2016-03-02 20:44:42 +00:00
Stanislav Shwartsman
9308ad31c6 remove unused param from serveIcacheMiss 2016-02-22 19:57:24 +00:00
Stanislav Shwartsman
591039e588 removed debug print 2016-02-21 20:14:15 +00:00
Stanislav Shwartsman
de85547932 update popcnt functions to faster versions 2016-02-21 18:39:10 +00:00
Stanislav Shwartsman
88be61c3d9 add new cpuid bit announced in sdm rev057 2015-12-29 20:21:08 +00:00
Stanislav Shwartsman
9557cafcef revertng commit #12854 because it broke MT simulation with debugger enabled. Until investigted. 2015-12-20 22:44:54 +00:00
Stanislav Shwartsman
a8a325f2f5 #define to enum or inline function convertion 2015-10-09 19:33:36 +00:00
Stanislav Shwartsman
ea3c1c77eb added vmx consistency checks related to recently implemented support for vm-entering shutdown/wait-for-sipi state 2015-10-09 06:18:14 +00:00
Stanislav Shwartsman
cd2129ec3b avoid calling prefetch() each time when linking traces cross page 2015-10-09 05:33:44 +00:00
Stanislav Shwartsman
9f77a6c3b0 full debugger support together with handler-chaining speedups optimization enabled (experimental) 
should speedup emulation with debugger enabled
 2015-10-09 05:28:47 +00:00
Stanislav Shwartsman
12f6857968 fixed smm restore of segment register's selector 2015-09-30 18:55:21 +00:00
Stanislav Shwartsman
18fced44ae clean wrongly committed line 2015-09-30 18:45:01 +00:00
Stanislav Shwartsman
8d13b61319 implemented TSC Scaling VMX feature according to timestamp-counter for virtualization whitepaper published by Intel 2015-09-30 18:44:01 +00:00
Stanislav Shwartsman
ad52e15860 added few tlb specific cpustat counters 2015-09-28 19:09:32 +00:00
Stanislav Shwartsman
0e37969e32 stop flooding log by messages which not necesary indicate guest code error 2015-09-28 18:45:26 +00:00
Stanislav Shwartsman
dd1ec977c2 enable vmenter to wait-for-sipi state 2015-09-28 18:42:05 +00:00
Stanislav Shwartsman
3a563a6573 use segment rok4g and wok4g in the fast string optimizations for correctness 2015-09-28 18:37:35 +00:00
Stanislav Shwartsman
8232928096 small code optimization and simplification 2015-09-23 19:25:07 +00:00
Stanislav Shwartsman
c44cb6ed81 more cases applicable for BX_TLB_ENTRY_OF 2015-09-22 20:10:22 +00:00
Stanislav Shwartsman
a66ed15d26 added missing tlb.h 2015-09-21 20:07:06 +00:00
Stanislav Shwartsman
be4b73c6d2 extracted tlb specific code to tlb.h; extracted xsave cpuid leaf function to base cpuid class 2015-09-21 13:16:17 +00:00
Stanislav Shwartsman
da39e57196 comment fixes 2015-09-08 19:14:58 +00:00
Stanislav Shwartsman
f76b972fed bugfix in call gate handling from call far instruction - found with rdos 2015-09-02 19:14:47 +00:00
Stanislav Shwartsman
250cf02981 x86-64: Fixed bug in OR_EqGqM handler used with FS or GS segment 2015-07-26 19:20:21 +00:00
Stanislav Shwartsman
f6af0443bb small optimization and elimination of several defines from cpu.h - replace by inline functions and const variables 2015-07-13 20:24:14 +00:00
Stanislav Shwartsman
ea255b5bf7 fixed VMCS memory type calculation 2015-07-12 20:10:43 +00:00
Stanislav Shwartsman
129db3bfaf fixed typo in the list of the vmcs exits 2015-07-12 15:26:34 +00:00
Stanislav Shwartsman
9315742f3d cleanups of vmcs mapping related stuff 2015-07-07 21:06:56 +00:00
Stanislav Shwartsman
e9f9f824be return value from clear/set_mapping functions 2015-07-06 20:16:34 +00:00
Stanislav Shwartsman
28c19ecec7 more interfaces to VMCS Mapping class 2015-07-06 20:14:56 +00:00
Stanislav Shwartsman
5fe1423ab6 introducr new class for VMCS mapping so it can be customized per cpuid 2015-07-06 18:46:57 +00:00
Stanislav Shwartsman
b86f01d410 update TODO 2015-06-29 19:57:04 +00:00
Stanislav Shwartsman
3fef7f32f6 added new bits definitions recently published 2015-06-29 19:53:56 +00:00
Stanislav Shwartsman
bc25883087 add new definitions from most recent AMD Software Developers Manual update. TODO: implement new AMD's MONITORX/MWAITX extensions 2015-06-22 21:46:50 +00:00