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convert some defines to enums and const expressions

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This commit is contained in:
Stanislav Shwartsman 2018-11-17 12:45:44 +00:00
parent e387876145
commit eff201773f
4 changed files with 64 additions and 53 deletions
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48
bochs/cpu/apic.h
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@ -25,10 +25,13 @@
#if BX_SUPPORT_APIC
#define APIC_LEVEL_TRIGGERED 1
#define APIC_EDGE_TRIGGERED 0
enum {
APIC_EDGE_TRIGGERED = 0,
APIC_LEVEL_TRIGGERED = 1
};
const bx_phy_address BX_LAPIC_BASE_ADDR = 0xfee00000; // default Local APIC address
#define BX_LAPIC_BASE_ADDR 0xfee00000 // default Local APIC address
#define BX_NUM_LOCAL_APICS BX_SMP_PROCESSORS
#define BX_LAPIC_MAX_INTS 256
@ -108,6 +111,28 @@ typedef Bit32u apic_dest_t; /* same definition in ioapic.h */
#define BX_LAPIC_IER7 0x4E0
#define BX_LAPIC_IER8 0x4F0
/* APIC delivery modes */
enum {
APIC_DM_FIXED = 0,
APIC_DM_LOWPRI = 1,
APIC_DM_SMI = 2,
APIC_DM_RESERVED = 3,
APIC_DM_NMI = 4,
APIC_DM_INIT = 5,
APIC_DM_SIPI = 6,
APIC_DM_EXTINT = 7
};
#define APIC_LVT_ENTRIES 6
enum {
APIC_LVT_TIMER = 0,
APIC_LVT_THERMAL = 1,
APIC_LVT_PERFMON = 2,
APIC_LVT_LINT0 = 3,
APIC_LVT_LINT1 = 4,
APIC_LVT_ERROR = 5
};
class BOCHSAPI bx_local_apic_c : public logfunctions
{
bx_phy_address base_addr;
@ -160,14 +185,7 @@ class BOCHSAPI bx_local_apic_c : public logfunctions
Bit32u icr_hi; // Interrupt command register (ICR)
Bit32u icr_lo;
#define APIC_LVT_ENTRIES 6
Bit32u lvt[APIC_LVT_ENTRIES];
#define APIC_LVT_TIMER 0
#define APIC_LVT_THERMAL 1
#define APIC_LVT_PERFMON 2
#define APIC_LVT_LINT0 3
#define APIC_LVT_LINT1 4
#define APIC_LVT_ERROR 5
Bit32u timer_initial; // Initial timer count (in order to reload periodic timer)
Bit32u timer_current; // Current timer count
@ -180,16 +198,6 @@ class BOCHSAPI bx_local_apic_c : public logfunctions
bx_bool timer_active;
int timer_handle;
/* APIC delivery modes */
#define APIC_DM_FIXED 0
#define APIC_DM_LOWPRI 1
#define APIC_DM_SMI 2
/* RESERVED 3 */
#define APIC_DM_NMI 4
#define APIC_DM_INIT 5
#define APIC_DM_SIPI 6
#define APIC_DM_EXTINT 7
#if BX_SUPPORT_VMX >= 2
int vmx_timer_handle;
Bit32u vmx_preemption_timer_value;

6
bochs/cpu/i387.h
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@ -258,10 +258,10 @@ typedef BxPackedRegister BxPackedMmxRegister;
#define BX_READ_MMX_REG(index) \
(*((const BxPackedMmxRegister*)(&(BX_MMX_REG(index)))))
#define BX_WRITE_MMX_REG(index, value) \
#define BX_WRITE_MMX_REG(index, value) \
{ \
(BX_FPU_REG(index)).fraction = MMXUQ(value); \
(BX_FPU_REG(index)).exp = 0xffff; \
(BX_FPU_REG(index)).fraction = MMXUQ(value); \
(BX_FPU_REG(index)).exp = 0xffff; \
}
#endif /* BX_SUPPORT_FPU */

29
bochs/cpu/tlb.h
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@ -32,25 +32,26 @@
// When there are collisions, the old entry is overwritten with
// one for the newest access.
#define BX_TLB_SIZE 1024
#define BX_TLB_MASK ((BX_TLB_SIZE-1) << 12)
const Bit32u BX_TLB_SIZE = 1024;
const Bit32u BX_TLB_MASK = ((BX_TLB_SIZE-1) << 12);
#define BX_TLB_INDEX_OF(lpf, len) ((((unsigned)(lpf) + (len)) & BX_TLB_MASK) >> 12)
typedef bx_ptr_equiv_t bx_hostpageaddr_t;
#if BX_SUPPORT_X86_64
#define BX_INVALID_TLB_ENTRY BX_CONST64(0xffffffffffffffff)
const bx_address BX_INVALID_TLB_ENTRY = BX_CONST64(0xffffffffffffffff);
#else
#define BX_INVALID_TLB_ENTRY 0xffffffff
const bx_address BX_INVALID_TLB_ENTRY = 0xffffffff;
#endif
// accessBits
#define TLB_SysReadOK (0x01)
#define TLB_UserReadOK (0x02)
#define TLB_SysWriteOK (0x04)
#define TLB_UserWriteOK (0x08)
#define TLB_SysExecuteOK (0x10)
#define TLB_UserExecuteOK (0x20)
const Bit32u TLB_SysReadOK = 0x01;
const Bit32u TLB_UserReadOK = 0x02;
const Bit32u TLB_SysWriteOK = 0x04;
const Bit32u TLB_UserWriteOK = 0x08;
const Bit32u TLB_SysExecuteOK = 0x10;
const Bit32u TLB_UserExecuteOK = 0x20;
#if BX_SUPPORT_PKEYS
@ -121,15 +122,15 @@ typedef struct {
} bx_TLB_entry;
#if BX_SUPPORT_X86_64
#define LPF_MASK BX_CONST64(0xfffffffffffff000)
const bx_address LPF_MASK = BX_CONST64(0xfffffffffffff000);
#else
#define LPF_MASK (0xfffff000)
const bx_address LPF_MASK = 0xfffff000;
#endif
#if BX_PHY_ADDRESS_LONG
#define PPF_MASK BX_CONST64(0xfffffffffffff000)
const bx_phy_address PPF_MASK = BX_CONST64(0xfffffffffffff000);
#else
#define PPF_MASK (0xfffff000)
const bx_phy_address PPF_MASK = 0xfffff000;
#endif
BX_CPP_INLINE Bit32u PAGE_OFFSET(bx_address laddr)

34
bochs/cpu/vmx.h
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@ -443,10 +443,12 @@ const Bit64u VMX_VMFUNC_EPTP_SWITCHING_MASK = (BX_CONST64(1) << VMX_VMFUNC_EPTP_
// bits 11:10 of VMCS field encoding indicate field's type
#define VMCS_FIELD_TYPE(encoding) (((encoding) >> 10) & 3)
#define VMCS_FIELD_TYPE_CONTROL 0x0
#define VMCS_FIELD_TYPE_READ_ONLY 0x1
#define VMCS_FIELD_TYPE_GUEST_STATE 0x2
#define VMCS_FIELD_TYPE_HOST_STATE 0x3
enum {
VMCS_FIELD_TYPE_CONTROL = 0x0,
VMCS_FIELD_TYPE_READ_ONLY = 0x1,
VMCS_FIELD_TYPE_GUEST_STATE = 0x2,
VMCS_FIELD_TYPE_HOST_STATE = 0x3
};
// bits 14:13 of VMCS field encoding indicate field's width
#define VMCS_FIELD_WIDTH(encoding) (((encoding) >> 13) & 3)
@ -1063,18 +1065,18 @@ const Bit32u VMX_MISC_PREEMPTION_TIMER_RATE = 0;
// allowed 0-setting in CR0 in VMX mode
// bits PE(0), NE(5) and PG(31) required to be set in CR0 to enter VMX mode
#define VMX_MSR_CR0_FIXED0_LO (0x80000021)
#define VMX_MSR_CR0_FIXED0_HI (0x00000000)
const Bit32u VMX_MSR_CR0_FIXED0_LO = 0x80000021;
const Bit32u VMX_MSR_CR0_FIXED0_HI = 0x00000000;
#define VMX_MSR_CR0_FIXED0 \
((((Bit64u) VMX_MSR_CR0_FIXED0_HI) << 32) | VMX_MSR_CR0_FIXED0_LO)
const Bit64u VMX_MSR_CR0_FIXED0 =
((((Bit64u) VMX_MSR_CR0_FIXED0_HI) << 32) | VMX_MSR_CR0_FIXED0_LO);
// allowed 1-setting in CR0 in VMX mode
#define VMX_MSR_CR0_FIXED1_LO (0xFFFFFFFF)
#define VMX_MSR_CR0_FIXED1_HI (0x00000000)
const Bit32u VMX_MSR_CR0_FIXED1_LO = 0xFFFFFFFF;
const Bit32u VMX_MSR_CR0_FIXED1_HI = 0x00000000;
#define VMX_MSR_CR0_FIXED1 \
((((Bit64u) VMX_MSR_CR0_FIXED1_HI) << 32) | VMX_MSR_CR0_FIXED1_LO)
const Bit64u VMX_MSR_CR0_FIXED1 =
((((Bit64u) VMX_MSR_CR0_FIXED1_HI) << 32) | VMX_MSR_CR0_FIXED1_LO);
//
// IA32_VMX_CR4_FIXED0 MSR (0x488) IA32_VMX_CR4_FIXED1 MSR (0x489)
@ -1082,11 +1084,11 @@ const Bit32u VMX_MISC_PREEMPTION_TIMER_RATE = 0;
// allowed 0-setting in CR0 in VMX mode
// bit VMXE(13) required to be set in CR4 to enter VMX mode
#define VMX_MSR_CR4_FIXED0_LO (0x00002000)
#define VMX_MSR_CR4_FIXED0_HI (0x00000000)
const Bit32u VMX_MSR_CR4_FIXED0_LO = 0x00002000;
const Bit32u VMX_MSR_CR4_FIXED0_HI = 0x00000000;
#define VMX_MSR_CR4_FIXED0 \
((((Bit64u) VMX_MSR_CR4_FIXED0_HI) << 32) | VMX_MSR_CR4_FIXED0_LO)
const Bit64u VMX_MSR_CR4_FIXED0 =
((((Bit64u) VMX_MSR_CR4_FIXED0_HI) << 32) | VMX_MSR_CR4_FIXED0_LO);
// allowed 1-setting in CR0 in VMX mode
#define VMX_MSR_CR4_FIXED1_LO (BX_CPU_THIS_PTR cr4_suppmask)