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fixed new disasm for avx2 opcodes

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This commit is contained in:
Stanislav Shwartsman 2017-12-30 18:45:21 +00:00
parent 6469e9d717
commit 6566cab8aa
1 changed files with 7 additions and 6 deletions
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13
bochs/cpu/decoder/ia_opcodes.def
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@ -2131,18 +2131,19 @@ bx_define_opcode(BX_IA_VMOVQ_VqWq, &BX_CPU_C::MOVSD_VsdWsdM, &BX_CPU_C::MOVQ_VqW
bx_define_opcode(BX_IA_VCVTPH2PS_VpsWps, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VCVTPH2PS_VpsWpsR, BX_ISA_AVX_F16C, OP_Vps, OP_mVHV, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VCVTPS2PH_WpsVpsIb, &BX_CPU_C::VCVTPS2PH_WpsVpsIb, &BX_CPU_C::VCVTPS2PH_WpsVpsIb, BX_ISA_AVX_F16C, OP_mVHV, OP_Vps, OP_Ib, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVSXBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVSXBW_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVSXBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVSXBW_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_mVHV, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVSXBD_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVSXBD_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVSXBQ_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPMOVSXBQ_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wd, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVSXWD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVSXWD_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVSXWD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVSXWD_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_mVHV, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVSXWQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVSXWQ_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVSXDQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVSXDQ_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVZXBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVZXBW_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVSXDQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVSXDQ_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_mVHV, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVZXBW_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVZXBW_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_mVHV, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVZXBD_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVZXBD_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVZXBQ_VdqWd, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::VPMOVZXBQ_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wd, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVZXWD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVZXWD_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVZXWD_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVZXWD_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_mVHV, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVZXWQ_VdqWq, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::VPMOVZXWQ_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVZXDQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVZXDQ_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVZXDQ_VdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPMOVZXDQ_VdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_mVHV, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPERM2I128_VdqHdqWdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERM2F128_VdqHdqWdqIbR, BX_ISA_AVX2, OP_Vdq, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VINSERTI128_VdqHdqWdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF128_VdqHdqWdqIbR, BX_ISA_AVX2, OP_Vdq, OP_Hdq, OP_Wdq, OP_Ib, BX_PREPARE_AVX)