fixed softfloat FUZ condition. fixed/optimized pmaddwd computing function
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@ -883,7 +883,7 @@ static float32 addFloat32Sigs(float32 a, float32 b, int zSign, float_status_t &s
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zSig = (aSig + bSig) >> 6;
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if (aSig | bSig) {
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float_raise(status, float_flag_denormal);
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if (get_flush_underflow_to_zero(status)) {
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if (get_flush_underflow_to_zero(status) && (extractFloat32Frac(zSig) == zSig)) {
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float_raise(status, float_flag_underflow | float_flag_inexact);
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return packFloat32(zSign, 0, 0);
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}
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@ -2109,7 +2109,7 @@ static float64 addFloat64Sigs(float64 a, float64 b, int zSign, float_status_t &s
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zSig = (aSig + bSig) >> 9;
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if (aSig | bSig) {
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float_raise(status, float_flag_denormal);
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if (get_flush_underflow_to_zero(status)) {
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if (get_flush_underflow_to_zero(status) && (extractFloat64Frac(zSig) == zSig)) {
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float_raise(status, float_flag_underflow | float_flag_inexact);
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return packFloat64(zSign, 0, 0);
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}
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@ -1009,13 +1009,8 @@ BX_CPP_INLINE void xmm_pmaddwd(BxPackedXmmRegister *op1, const BxPackedXmmRegist
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{
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for(unsigned n=0; n<4; n++)
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{
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if((op1->xmm32u(n) & op2->xmm32u(n)) == 0x80008000) {
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op1->xmm32u(n) = 0x80000000;
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}
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else {
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op1->xmm32u(n) = Bit32s(op1->xmm16s(n*2)) * Bit32s(op2->xmm16s(n*2)) +
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Bit32s(op1->xmm16s(n*2+1)) * Bit32s(op2->xmm16s(n*2+1));
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}
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op1->xmm32u(n) = Bit32s(op1->xmm16s(n*2)) * Bit32s(op2->xmm16s(n*2)) +
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Bit32s(op1->xmm16s(n*2+1)) * Bit32s(op2->xmm16s(n*2+1));
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}
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}
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