convert defines to const and enum in paging.cc
This commit is contained in:
Stanislav Shwartsman
parent
fd70b46136
commit
a9ac81e092
@ -277,12 +277,11 @@ static const Bit8u priv_check[BX_PRIV_CHECK_SIZE] =
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#endif
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};
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#define BX_PAGING_PHY_ADDRESS_RESERVED_BITS \
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(BX_PHY_ADDRESS_RESERVED_BITS & BX_CONST64(0xfffffffffffff))
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const Bit64u BX_PAGING_PHY_ADDRESS_RESERVED_BITS = BX_PHY_ADDRESS_RESERVED_BITS & BX_CONST64(0xfffffffffffff);
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#define PAGE_DIRECTORY_NX_BIT (BX_CONST64(0x8000000000000000))
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const Bit64u PAGE_DIRECTORY_NX_BIT = BX_CONST64(0x8000000000000000);
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#define BX_CR3_PAGING_MASK (BX_CONST64(0x000ffffffffff000))
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const Bit64u BX_CR3_PAGING_MASK = BX_CONST64(0x000ffffffffff000);
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// Each entry in the TLB cache has 3 entries:
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//
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@ -502,11 +501,13 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INVLPG(bxInstruction_c* i)
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}
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// error checking order - page not present, reserved bits, protection
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#define ERROR_NOT_PRESENT 0x00
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#define ERROR_PROTECTION 0x01
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#define ERROR_RESERVED 0x08
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#define ERROR_CODE_ACCESS 0x10
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#define ERROR_PKEY 0x20
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enum {
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ERROR_NOT_PRESENT = 0x00,
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ERROR_PROTECTION = 0x01,
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ERROR_RESERVED = 0x08,
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ERROR_CODE_ACCESS = 0x10,
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ERROR_PKEY = 0x20
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};
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void BX_CPU_C::page_fault(unsigned fault, bx_address laddr, unsigned user, unsigned rw)
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{
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@ -543,10 +544,12 @@ void BX_CPU_C::page_fault(unsigned fault, bx_address laddr, unsigned user, unsig
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exception(BX_PF_EXCEPTION, error_code);
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}
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#define BX_LEVEL_PML4 3
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#define BX_LEVEL_PDPTE 2
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#define BX_LEVEL_PDE 1
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#define BX_LEVEL_PTE 0
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enum {
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BX_LEVEL_PML4 = 3,
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BX_LEVEL_PDPTE = 2,
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BX_LEVEL_PDE = 1,
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BX_LEVEL_PTE = 0
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};
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static const char *bx_paging_level[4] = { "PTE", "PDE", "PDPE", "PML4" }; // keep it 4 letters
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@ -569,11 +572,10 @@ static const char *bx_paging_level[4] = { "PTE", "PDE", "PDPE", "PML4" }; // kee
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// 63 | Execute-Disable (XD) (if EFER.NXE=1, reserved otherwise)
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// -----------------------------------------------------------
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#define PAGING_PAE_RESERVED_BITS (BX_PAGING_PHY_ADDRESS_RESERVED_BITS)
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const Bit64u PAGING_PAE_RESERVED_BITS = BX_PAGING_PHY_ADDRESS_RESERVED_BITS;
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// in legacy PAE mode bits [62:52] are reserved. bit 63 is NXE
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#define PAGING_LEGACY_PAE_RESERVED_BITS \
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(BX_PAGING_PHY_ADDRESS_RESERVED_BITS | BX_CONST64(0x7ff0000000000000))
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const Bit64u PAGING_LEGACY_PAE_RESERVED_BITS = BX_PAGING_PHY_ADDRESS_RESERVED_BITS | BX_CONST64(0x7ff0000000000000);
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// Format of a PDPTE that References a 1-GByte Page
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// -----------------------------------------------------------
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@ -595,8 +597,7 @@ static const char *bx_paging_level[4] = { "PTE", "PDE", "PDPE", "PML4" }; // kee
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// 63 | Execute-Disable (XD) (if EFER.NXE=1, reserved otherwise)
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// -----------------------------------------------------------
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#define PAGING_PAE_PDPTE1G_RESERVED_BITS \
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(BX_PAGING_PHY_ADDRESS_RESERVED_BITS | BX_CONST64(0x3FFFE000))
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const Bit64u PAGING_PAE_PDPTE1G_RESERVED_BITS = BX_PAGING_PHY_ADDRESS_RESERVED_BITS | BX_CONST64(0x3FFFE000);
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// Format of a PAE PDE that Maps a 2-MByte Page
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// -----------------------------------------------------------
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@ -618,8 +619,7 @@ static const char *bx_paging_level[4] = { "PTE", "PDE", "PDPE", "PML4" }; // kee
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// 63 | Execute-Disable (XD) (if EFER.NXE=1, reserved otherwise)
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// -----------------------------------------------------------
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#define PAGING_PAE_PDE2M_RESERVED_BITS \
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(BX_PAGING_PHY_ADDRESS_RESERVED_BITS | BX_CONST64(0x001FE000))
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const Bit64u PAGING_PAE_PDE2M_RESERVED_BITS = BX_PAGING_PHY_ADDRESS_RESERVED_BITS | BX_CONST64(0x001FE000);
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// Format of a PAE PTE that Maps a 4-KByte Page
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// -----------------------------------------------------------
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@ -836,8 +836,7 @@ void BX_CPU_C::update_access_dirty_PAE(bx_phy_address *entry_addr, Bit64u *entry
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// 63-PA | Reserved (must be zero)
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// -----------------------------------------------------------
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#define PAGING_PAE_PDPTE_RESERVED_BITS \
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(BX_PAGING_PHY_ADDRESS_RESERVED_BITS | BX_CONST64(0xFFF00000000001E6))
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const Bit64u PAGING_PAE_PDPTE_RESERVED_BITS = BX_PAGING_PHY_ADDRESS_RESERVED_BITS | BX_CONST64(0xFFF00000000001E6);
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bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::CheckPDPTR(bx_phy_address cr3_val)
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{
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@ -1043,8 +1042,7 @@ bx_phy_address BX_CPU_C::translate_linear_PAE(bx_address laddr, Bit32u &lpf_mask
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// 31-22 | Bits 31-22 of physical address of the 4-MByte page
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// -----------------------------------------------------------
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#define PAGING_PDE4M_RESERVED_BITS \
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(((1 << (41-BX_PHY_ADDRESS_WIDTH))-1) << (13 + BX_PHY_ADDRESS_WIDTH - 32))
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const Bit32u PAGING_PDE4M_RESERVED_BITS = ((1 << (41-BX_PHY_ADDRESS_WIDTH))-1) << (13 + BX_PHY_ADDRESS_WIDTH - 32);
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// Translate a linear address to a physical address in legacy paging mode
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bx_phy_address BX_CPU_C::translate_linear_legacy(bx_address laddr, Bit32u &lpf_mask, unsigned user, unsigned rw)
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@ -1701,9 +1699,11 @@ bx_phy_address BX_CPU_C::nested_walk(bx_phy_address guest_paddr, unsigned rw, bx
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#if BX_SUPPORT_VMX >= 2
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/* EPT access type */
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#define BX_EPT_READ 0x01
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#define BX_EPT_WRITE 0x02
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#define BX_EPT_EXECUTE 0x04
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enum {
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BX_EPT_READ = 0x01,
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BX_EPT_WRITE = 0x02,
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BX_EPT_EXECUTE = 0x04
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};
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/* EPT access mask */
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#define BX_EPT_ENTRY_NOT_PRESENT 0x00
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@ -1715,7 +1715,7 @@ bx_phy_address BX_CPU_C::nested_walk(bx_phy_address guest_paddr, unsigned rw, bx
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#define BX_EPT_ENTRY_WRITE_EXECUTE 0x06
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#define BX_EPT_ENTRY_READ_WRITE_EXECUTE 0x07
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#define BX_SUPPRESS_EPT_VIOLATION_EXCEPTION BX_CONST64(0x8000000000000000)
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const Bit64u BX_SUPPRESS_EPT_VIOLATION_EXCEPTION = BX_CONST64(0x8000000000000000);
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#define BX_VMX_EPT_ACCESS_DIRTY_ENABLED (BX_CPU_THIS_PTR vmcs.eptptr & 0x40)
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@ -1735,7 +1735,7 @@ bx_phy_address BX_CPU_C::nested_walk(bx_phy_address guest_paddr, unsigned rw, bx
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// 63-52 | (ignored)
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// -----------------------------------------------------------
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#define PAGING_EPT_RESERVED_BITS (BX_PAGING_PHY_ADDRESS_RESERVED_BITS)
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const Bit64u PAGING_EPT_RESERVED_BITS = BX_PAGING_PHY_ADDRESS_RESERVED_BITS;
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bx_phy_address BX_CPU_C::translate_guest_physical(bx_phy_address guest_paddr, bx_address guest_laddr, bx_bool guest_laddr_valid, bx_bool is_page_walk, unsigned rw)
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{
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