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finally figured out what TCE means in AMD CPUID - and it has EFER.TCE bit related to it

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This commit is contained in:
Stanislav Shwartsman 2017-03-15 22:48:27 +00:00
parent ebbf8f9e0f
commit 6edf22e754
4 changed files with 11 additions and 5 deletions
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4
bochs/cpu/cpudb/amd/ryzen.cc
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@ -500,7 +500,7 @@ void ryzen_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
// [14:14] Reserved
// [15:15] LWP: Light weight profiling
// [16:16] FMA4: Four-operand FMA instructions support
// * [17:17] Reserved
// * [17:17] Translation Cache Extensions
// [18:18] Reserved
// [19:19] NodeId: Indicates support for NodeId MSR (0xc001100c)
// [20:20] Reserved
@ -527,7 +527,9 @@ void ryzen_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
BX_CPUID_EXT2_MISALIGNED_SSE |
BX_CPUID_EXT2_PREFETCHW |
BX_CPUID_EXT2_OSVW |
/* BX_CPUID_EXT2_SKINIT | */ // not implemented
BX_CPUID_EXT2_WDT |
BX_CPUID_EXT2_TCE |
BX_CPUID_EXT2_TOPOLOGY_EXTENSIONS |
BX_CPUID_EXT2_PERFCTR_EXT_CORE |
BX_CPUID_EXT2_PERFCTR_EXT_NB |

3
bochs/cpu/cpudb/amd/trinity_apu.cc
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@ -464,7 +464,7 @@ void trinity_apu_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
// [14:14] Reserved
// * [15:15] LWP: Light weight profiling
// * [16:16] FMA4: Four-operand FMA instructions support
// * [17:17] Reserved
// * [17:17] Translation Cache Extensions
// [18:18] Reserved
// * [19:19] NodeId: Indicates support for NodeId MSR (0xc001100c)
// [20:20] Reserved
@ -492,6 +492,7 @@ void trinity_apu_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
BX_CPUID_EXT2_WDT |
/* BX_CPUID_EXT2_LWP | */ // not implemented
BX_CPUID_EXT2_FMA4 |
BX_CPUID_EXT2_TCE |
BX_CPUID_EXT2_NODEID |
BX_CPUID_EXT2_TBM |
BX_CPUID_EXT2_TOPOLOGY_EXTENSIONS |

5
bochs/cpu/cpuid.h
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@ -449,7 +449,8 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
// [14:14] reserved
// [15:15] LWP: Light weight profiling
// [16:16] FMA4: Four-operand FMA instructions support
// [18:17] reserved
// [17:17] Translation Cache Extensions (reserved?)
// [18:18] reserved
// [19:19] NodeId: Indicates support for NodeId MSR (0xc001100c)
// [20:20] reserved
// [21:21] TBM: trailing bit manipulation instruction support
@ -480,7 +481,7 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
#define BX_CPUID_EXT2_RESERVED14 (1 << 14)
#define BX_CPUID_EXT2_LWP (1 << 15)
#define BX_CPUID_EXT2_FMA4 (1 << 16)
#define BX_CPUID_EXT2_RESERVED17 (1 << 17)
#define BX_CPUID_EXT2_TCE (1 << 17)
#define BX_CPUID_EXT2_RESERVED18 (1 << 18)
#define BX_CPUID_EXT2_NODEID (1 << 19)
#define BX_CPUID_EXT2_RESERVED20 (1 << 20)

4
bochs/cpu/crregs.h
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@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2007-2015 Stanislav Shwartsman
// Copyright (c) 2007-2017 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -211,6 +211,7 @@ struct bx_dr7_t {
#define BX_EFER_SVME_MASK (1 << 12)
#define BX_EFER_LMSLE_MASK (1 << 13)
#define BX_EFER_FFXSR_MASK (1 << 14)
#define BX_EFER_TCE_MASK (1 << 15)
struct bx_efer_t {
Bit32u val32; // 32bit value of register
@ -225,6 +226,7 @@ struct bx_efer_t {
IMPLEMENT_CRREG_ACCESSORS(SVME, 12); /* AMD Secure Virtual Machine */
IMPLEMENT_CRREG_ACCESSORS(LMSLE, 13); /* AMD Long Mode Segment Limit */
IMPLEMENT_CRREG_ACCESSORS(FFXSR, 14);
IMPLEMENT_CRREG_ACCESSORS(TCE, 15); /* AMD Translation Cache Extensions */
#endif
BX_CPP_INLINE Bit32u get32() const { return val32; }