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92e254d047
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518 Commits

Author SHA1 Message Date
Alexander von Gluck IV
92e254d047 intel_extreme: Improve PCH detection 
* Detect PCH model based on ISA bridge and save
  into shared info for later use.
* On CougarPoint PCH systems, assign pipes via
  special CPT registers
* Drop HasPlatformControlHub as PCH should be
  based on more than just generation.
 2016-07-10 21:02:01 -05:00
Alexander von Gluck IV
30d631c821 radeon_hd: Add new Polaris GPU, untested 2016-06-30 15:09:59 -05:00
Alexander von Gluck IV
8fe5054828 intel_extreme: Extend DDI port probing to A-E 
* The Linux code made this a bit hard to figure out via
  complex define functions, however there can be up to
  5 DDI ports (A-E)
 2016-05-08 15:40:57 -05:00
Alexander von Gluck IV
8d1cb54aac intel_extreme: Add in some code for the lakes (unused) 2016-04-22 22:41:52 -05:00
Alexander von Gluck IV
ca95e9dad9 intel_extreme: Add initial work for DDI ports 2016-03-15 18:12:28 -05:00
Alexander von Gluck IV
3d1bd895ad intel_extreme: Properly use VBIOS panel mode 
* Move current_mode into the accelerant as the
  driver doesn't care.
* Record panel_mode in driver and present to accelerant
* eDP, if no EDID and mobile, leave edid incomplete.
  Mode set should notice that and fall back to panel_mode
 2016-03-11 18:20:28 -06:00
Alexander von Gluck IV
a81f65eae5 Merge branch 'master' into intel-extreme 2016-03-09 17:11:08 -06:00
Alexander von Gluck IV
721ba9af43 intel_extreme: Clean up DisplayPort Port class 
* DisplayPort != DigitalPort
* i2c needs wrapped in DP AUX transaction code
* Mode-setting comes with DP link training as well
* We need to try and share DP code with radeon_hd
 2016-02-23 14:10:14 -06:00
Alexander von Gluck IV
9975620612 intel_extreme: Prepare for DisplayPort AUX comms 2016-02-23 13:39:10 -06:00
Jérôme Duval
f369957d03 via.accelerant: move enums out of the struct. 2016-02-19 22:33:41 +01:00
Alexander von Gluck IV
bab64f65bb Merge remote-tracking branch 'upstream/master' into intel-extreme 2016-02-19 10:17:42 -06:00
Alexander von Gluck IV
c9c61669ea intel_extreme: Add general pipe configuration and adjust color space 2016-02-19 00:09:43 -06:00
Rudolf Cornelissen
0fa7d5c4df VIA gfx driver: overlay engine on K8M800 responds now, wip. 2016-01-23 23:46:22 +01:00
Rudolf Cornelissen
14de50bad7 VIA gfx driver:K8M800 now works (fixed PLL), fixed info in GetDeviceInfo 2016-01-13 01:01:32 +01:00
Rudolf Cornelissen
b0c69e8490 nVidia driver: added option to block EDID resolution restrictions (check_edid) 2016-01-05 23:49:00 +01:00
RudolfC
063436816d nVidia driver: Added basic dualhead support for native Haiku ScreenPrefs app 2016-01-04 22:17:48 +00:00
Alexander von Gluck IV
d35a52e8e2 intel_extreme: Fix i965 LVDS panel programming 
* polarity regs move on LVDS vs analog
* add knowledge or transcoder registers, they
  exist seperately on PCH-split
* Native resolutions now work on LVDS under i965
 2016-01-03 10:46:13 -06:00
Alexander von Gluck IV
0ea662e5e9 intel_extreme: Correct panel control register on non-pch 2015-12-15 07:23:21 -06:00
Alexander von Gluck IV
3cfe299798 intel_extreme: Rework PLL and id PineView as PIN 2015-12-04 13:34:33 -06:00
Alexander von Gluck IV
e6fefa6cbf intel_extreme: More FDI training work 
* IvyBridge or higher can auto-train.
* Linux doesn't use this feature, however
  manual FDI link training is *really*
  complex... lets try auto-training first.
 2015-11-19 17:49:51 -06:00
Alexander von Gluck IV
aa06863ccd intel_extreme: Enable / Disable FDI TX/RX 2015-11-19 13:26:55 -06:00
Alexander von Gluck IV
00e0982f68 intel_extreme: First work at programming FDI 2015-11-17 23:28:09 -06:00
Alexander von Gluck IV
e5494f1bb2 intel_extreme: Fix DP / HDMI gpu register location mixup on die 2015-11-16 20:41:14 -06:00
Alexander von Gluck IV
202ffc8cca intel_extreme: Bump the VLV offset back a bit and fix port defines 2015-11-16 19:58:51 -06:00
Alexander von Gluck IV
f979e62e54 intel_extreme: Program more LVDS regs. Set +/- @ lvds port 2015-11-12 18:30:21 -06:00
Alexander von Gluck IV
92bcdd7935 intel_extreme: Add initial TMDS modesetting code 2015-11-09 09:26:07 -06:00
Alexander von Gluck IV
d442692fab intel_extreme: Correct DP port registers 2015-11-09 09:15:16 -06:00
Alexander von Gluck IV
61fbdb0667 intel_extreme: Set mode and pll via pipe-aware class functions 2015-11-08 23:14:46 -06:00
Alexander von Gluck IV
37b903fbc8 intel_extreme: Add pipe selection for ports 2015-11-08 10:39:07 -06:00
Alexander von Gluck IV
b809fb52ed intel_extreme: Add some missing panel registers, masks, shifts 2015-11-04 17:48:06 -06:00
Alexander von Gluck IV
9cd46c7372 intel_extreme: Fix PCH_PANEL STS/CTL register location and define more 2015-11-04 17:29:06 -06:00
Alexander von Gluck IV
fb255821eb intel_extreme: Correct generations based on some Intel help 2015-11-04 16:11:22 -06:00
Alexander von Gluck IV
fa1d593323 intel_gart: Clean up trace code, break apart gtt probe functions 2015-11-03 17:18:58 -06:00
Alexander von Gluck IV
47fba246cc intel_extreme: Fix IsMobile. That's not how masks work 2015-11-02 20:14:00 -06:00
Alexander von Gluck IV
c86f3dba23 intel_extreme: LVDS cleanup and fixes for later gens 2015-11-02 18:01:18 -06:00
Alexander von Gluck IV
e2e5daf25b intel_extreme: Add generation index + begin to use in gart 2015-11-02 15:55:05 -06:00
Alexander von Gluck IV
53f5bffe84 intel_gart: Fix gart detection and begin using DeviceType 
* Correctly identify newly re-assigned cards families
* Begin using new DeviceType class in intel gart code
 2015-11-01 20:17:20 -06:00
Alexander von Gluck IV
84b7116da8 intel_extreme: Rework card identification defines 
* Be more verbose on flag type
* Add additional groups
* Add additional families
* Correctly assign later models
 2015-11-01 12:20:10 -06:00
Alexander von Gluck IV
57b86ef335 intel_extreme: Clean up PLL reg defines 2015-10-30 13:52:09 -05:00
Alexander von Gluck IV
163e66f763 intel_extreme: Add pipe base register 2015-10-27 19:49:17 -05:00
Alexander von Gluck IV
b3f14fb7c7 intel_extreme: Start doing mode-setting at port level 
* I really hope we can kill head_mode some day
* Break pll code out from mode code
* The LVDS and Digital are smooshed together and
  likely need broken apart.
 2015-10-25 20:56:08 -05:00
Alexander von Gluck IV
e747cbe116 intel_extreme: Fix regs, remove PCH for VLV, Expand Type 
* Fix some incorrect HDMI reg locations
* PCH goes away on later Intel chips
* Add more mask room for Intel Groups
 2015-10-24 09:53:14 -05:00
Alexander von Gluck IV
bc5cad7395 intel_extreme: Correct card identification, add gen4 hdmi regs 2015-10-22 14:48:53 -05:00
Alexander von Gluck IV
50f0b3fe76 intel_extreme: Rebase and refactor mmlr's work from 2013 
* New port storage classes and cleaner logic
 2015-10-22 14:48:45 -05:00
Alexander von Gluck IV
97aa078ef4 intel_extreme: Intial work for ValleyView support 
* No impact to non-ValleyView chipsets
* Bump some register locations for VLV
* Only have HDMI port to test with on my ValleyView GPU
  and our driver seems to be missing all HDMI and
  sideband functionality.
* As ValleyView chipsets seem to be UEFI only, we don't
  have VESA fallback, so this shouldn't cause regressions.
  (unless we get UEFI framebuffer support)
 2015-10-15 23:39:31 -05:00
Alexander von Gluck IV
1b69f3394b radeon_hd: Properly and consistently pick HPD ID 2015-07-14 20:38:15 -05:00
Alexander von Gluck IV
7ea1ad1028 radeon_hd: Fix dp aux request / response shifts 2015-07-13 23:26:24 -05:00
Alexander von Gluck IV
63b02c37d4 accelerants/common: Add displayport aux message struct 2015-07-08 00:03:38 -05:00
Alexander von Gluck IV
bf8fe3ddb3 radeon_hd: Add Hawaii,Topaz,Tonga,Carrizo chips/cards 2015-07-07 10:27:44 -05:00
Adrien Destugues
0f94784a5e intel_extreme: fix vblank interrupt on Ivy Bridge and later 
Intel changed the PCH interrupt bits between Sandy Bridge and Ivy Bridge
to make space for the 3rd display pipe. Take this into account and check
for the correct bits on the newer devices.

Fixes #11522.
 2015-03-01 22:57:43 +01:00