* Now pulling in latest amdgpu atombios.h headers
* Lots of DisplayPort cleanup and removal of legacy stuff
* Add obsolete atombios header for things that disappear
(amdgpu doesn't support older cards like we do)
* Introduce new code to support later encoder tables
* Drop radeon-specific encoder service from common dp_info
* Tested on HD 5450 hdmi
* Helps prevent mainboard explosions and other bad stuff.
* ...maybe not explosions, but bad things.
* The RX 480 reference design can pull as much as 90W
from its PCIe slot at load. PCIe is rated for 75W.
* This change overloads the PCIe power cables vs the PCIe
slot. The PCIe power cables can handle going over spec.
* Untested since we really can't come close to loading a
RX 480 without hardware OpenGL ^_^
* Should be able to test on real hardware within a week.
There was some mixup with the interrupt registers, still:
- The driver uses 16-bit read/write, but on SandyBridge the register is
32 bits
- There is a global interrupt enable bit, which must be set to unmask
everything else
- The bits for vblank interrupt are not the same on SNB and later PCH
based devices, and the code mixed the two.
Move the computation of the interrupt bits to an helper function, and
use it everywhere to make sure we always use the right bits.
Modesetting
===========
My previous hack was setting the transcoder registers, instead of the
display ones. Do that the way it is designed in the driver instead:
- If there is a transcoder, set its registers, but do not set the
display timings. The display will remain set at its native (and only)
resolution, and panel fitting will adjust the output of the transcoder
to match.
- If there is no transcoder, set the display registers directly to the
native resolution, as it was done on previous generation devices.
- fPipeOffset hacks no longer needed
DPMS
====
It seems the panel control register is not readable on PCH? Anyway, the
code would loop forever waiting for the bit to become unset when turning
the display off. Waiting seems to not be needed, so just remove it as
well as the "unlock" bit, which does not work for me and results in a
black screen.
Remaining hacks
===============
I still need to force HEAD_MODE_A_ANALOG to get output on pipe B (LVDS
display) working. I suspect something is common to the two pipes or not
allocated to the right one.
This version will have less side effects on other generations and help
with getting things to work on SandyBridge and possibly later devices.
Please test and report.
* Detect PCH model based on ISA bridge and save
into shared info for later use.
* On CougarPoint PCH systems, assign pipes via
special CPT registers
* Drop HasPlatformControlHub as PCH should be
based on more than just generation.
* Move current_mode into the accelerant as the
driver doesn't care.
* Record panel_mode in driver and present to accelerant
* eDP, if no EDID and mobile, leave edid incomplete.
Mode set should notice that and fall back to panel_mode
* DisplayPort != DigitalPort
* i2c needs wrapped in DP AUX transaction code
* Mode-setting comes with DP link training as well
* We need to try and share DP code with radeon_hd
* polarity regs move on LVDS vs analog
* add knowledge or transcoder registers, they
exist seperately on PCH-split
* Native resolutions now work on LVDS under i965
* IvyBridge or higher can auto-train.
* Linux doesn't use this feature, however
manual FDI link training is *really*
complex... lets try auto-training first.
