Commit Graph

998 Commits

Author SHA1 Message Date
matt
5e67131b91 Start using a Makefile.mips. Use a combination of makeoptions and
Makefile.sgimips.inc which has sgimips specific stuff.
2000-12-03 02:07:04 +00:00
tsutsui
936191481d Prepare cpu_exec_ecoff_probe() for mips which just returns ENOEXEC,
as per discussion on tech-kern.
2000-11-27 13:25:24 +00:00
soren
a5dad0db13 Correct a few cpu/fpu ids. 2000-11-27 06:38:54 +00:00
nisimura
fdfe3556de Use only one TLB entry to wire down process's USPACE since it's
now guranteed to be aligned on 8KB boundary in kernel virutal
address.  Retain one more free TLB entry.
2000-11-27 06:37:32 +00:00
chs
b5142d6841 increase PAGER_MAP_SIZE to 16MB and move it to uvm_pager.h
since the alpha and mips pmaps use it.
2000-11-24 22:41:38 +00:00
soren
4927de268a Adjust for p_emul change. 2000-11-21 02:26:07 +00:00
jdolecek
baae0324b9 restructure struct emul and execsw, in preparation to make emulations LKMable:
* move all exec-type specific information from struct emul to execsw[] and
  provide single struct emul per emulation
* elf:
  - kern/exec_elf32.c:probe_funcs[] is gone, execsw[] how has one entry
    per emulation and contains pointer to respective probe function
  - interp is allocated via MALLOC() rather than on stack
  - elf_args structure is allocated via MALLOC() rather than malloc()
* ecoff: the per-emulation hooks moved from alpha and mips specific code
  to OSF1 and Ultrix compat code as appropriate, execsw[] has one entry per
  emulation supporting ecoff with appropriate probe function
* the makecmds/probe functions don't set emulation, pointer to emulation is
  part of appropriate execsw[] entry
* constify couple of structures
2000-11-21 00:37:49 +00:00
thorpej
cb38ab39ab We use 4K pages on MIPS systems (see mips_param.h), so override
PAGE_SIZE and friends to be compile-time constants.
2000-11-14 18:55:16 +00:00
thorpej
e654e96593 Use 64-bit printf formats for paddr_t's (for arc port). 2000-11-09 06:02:40 +00:00
jeffs
196e858c40 Add mips_pagecopy/zero assembly loops for use by pmap_copy/zero_page*()
to allow the almost-64-bit compilation use ld/sd.
2000-10-31 23:39:24 +00:00
jeffs
50e0133709 At the end of pmap_zero/copy_page() use hit instead of index op when
running with multi-way caches.  Since we know the ops will mostly
hit as we just dirtied those lines a single hit op is cheaper than
an index op for each way.
2000-10-31 23:16:31 +00:00
jeffs
5ca84b9d89 Add MIPS3_NO_PV_UNCACHED option to handle virtual coherency issues by
only allowing one mapping at a time instead of mapping uncached.  Done
by removing conflicting mappings from the pmap when entering a new
mapping.  UVM will remember and re-fault the requested page when needed
for the original mapping.  Originally done to support our internal machine
that does not support uncached memory completely.  Not enabled by default
currently.  It may make sense to try on the cobalt or sgi ports.
2000-10-31 22:46:35 +00:00
jeffs
11ef576801 Add mips_indexof() macro to make code for checking the cache index
easier to read.
2000-10-31 21:21:10 +00:00
shin
1ddfbf7e96 fix cp0 hazard.
R4000 requires 3 nops between tlbr and dmfc0.
2000-10-29 08:01:29 +00:00
castor
2a04de9c03 In mips3_TBIS(va) do not invalidate the other half of the JTLB entry if
the page is wired down.  Flushing both halves of a wired TLB entry resulted
in hangs when in programs called for and released kernel memory
soon after being invoked.  In particular, we see this when single-stepping
a process using GDB.

It would be better if we could arrange to use both halves of the TLB
entry for the PCB, but for some reason we frequently end up with things
on an odd page boundary.
2000-10-24 03:23:19 +00:00
jeffs
ade1f640e1 Go to to splhigh() in trap when panicing before calling debugger as break
handling does.
2000-10-23 05:49:05 +00:00
jeffs
bdbb241be6 Fix race between pmap_enter() and pagedaemon. If we are low on memory and
pmap_enter() cannot allocate the segmap return failure if PMAP_CANFAIL
instead of sleeping.  Otherwise panic.  Both alpha and i386 do this.  Do
not pmap_enter_pv() until after this is done so the data structures are
not partially allocated.  This should prevent pmap_page_protect() from
getting stuck when called from pagedaemon.
2000-10-10 20:39:42 +00:00
nisimura
778081cbf4 Add mtc0 insn to load TX3900 config register value to determine Dcache size. 2000-10-09 10:14:23 +00:00
nisimura
89e5c346a4 mips1_ConfigCache() has gone. 2000-10-09 07:33:31 +00:00
cgd
59706f1322 clean up and consistency for CP0 Count, Compare, Wired, and Config
access function names and prototypes.
2000-10-05 02:36:44 +00:00
cgd
b1b364243d always have to declare cpu_arch and the related constants (since setting
it isn't conditionalized).  (d'oh!)
2000-10-05 02:13:14 +00:00
cgd
7fefa594f7 add two blank lines 2000-10-05 01:17:20 +00:00
cgd
36123017cb nuke mips3_clearBEV(). There's really no point in coding a
special-purpose assembly routine for things like this.
2000-10-05 01:06:06 +00:00
cgd
3f1d3c3066 tweak cpu_arch. Eliminate all direct checks of it (making them
use the macro CPUISMIPS3 -- which is badly misnamed), and set it
from #defines named CPU_ARCH_N (where N is 1..5, 32, 64).
2000-10-05 00:52:59 +00:00
cgd
e9e1084ea3 rename mips_read_causereg -> mips_cp0_cause_read. nuke prototype
for mips_read_statusreg (which was apparently never implemented).
Provide prototypes and implementations for mips_cp0_cause_write,
mips_cp0_status_read, and mips_cp0_status_write.  (Writing can, of
course, be quite dangerous.)
2000-10-04 22:44:01 +00:00
cgd
8b8afc8d07 the generic MIPS code doesn't even play at doing anything useful
with a MIPS4 option at this point -- all the code except for one single
spot is conditionalized with MIPS3.  So, don't even pretend about
MIPS4 for now, until it all gets cleaned up.
2000-10-04 21:41:47 +00:00
cgd
13eb329ef1 provide indicators of a few more things that might go in opt_cputype.h 2000-10-04 21:31:06 +00:00
nisimura
8d263719b9 Merge exception return path of SystemCall and UserGenException into
proc_trampoline.
2000-10-04 08:46:21 +00:00
cgd
11e8e89dd4 add some additional info re: MIPS32 PRID encoding, derived from
the ``MIPS32 4K Processor Core Family Software User's Manual
Revision 01.07 June 19, 2000", available on the web from:
http://www.mips.com/declassified/Declassified_2000/MD00016-2B-4K-SUM-01.07.pdf
2000-10-03 23:15:58 +00:00
cgd
8dbc5c0c51 provide mips3_ld() and mips3_sd(), functions which provide safe wrappers
for mips3 (and later) 'ld' and 'sd' instructions.  These currently
only are properly implemented for the _MIPS_BSD_API_LP32 and
_MIPS_BSD_API_LP32_64CLEAN 'API's.  They're pretty messy, but when you
need them, you really need them.
2000-10-02 22:13:38 +00:00
jeffs
1bf0f4630f Use a cast to handle syscall() copyin case with 64b clean ctx save/restore. 2000-09-26 18:24:45 +00:00
jeffs
d6f992112d No longer save $at on syscall entry. v1 does appear to be used as if
you do not save it and pass it along in rval the system will start
to fail running user programs.  This finishes the suggestion by cgd to
not save some registers on syscall entry.
2000-09-26 18:22:12 +00:00
uch
a21df3ae8e fix R3900 FlushCache bug. 2000-09-26 17:47:40 +00:00
jeffs
e13c3f735f In trap(), do not lower spl for T_BREAK. This lets ddb always run at
splhigh() so nothing can happen behind it's back.
2000-09-21 20:59:58 +00:00
thorpej
b008f5f25a Make PMAP_PAGEIDLEZERO() return a boolean value. FALSE indidcates
that the page being zero'd was not completed and that page zeroing
should be aborted.  This may be used by machine-dependent code doing
slow page access to reduce the latency of running a process that has
become runnable while in the middle of doing a slow page zero.
2000-09-21 17:46:04 +00:00
jeffs
f1173a05e0 Add trace/t pid support for mips. 2000-09-19 06:22:51 +00:00
uch
0500ddb633 [R3900/R3920] sync with
| Module Name:	syssrc
 | Committed By:	nisimura
 | Date:		Sat Sep 16 07:20:17 UTC 2000
2000-09-18 18:17:32 +00:00
nisimura
70a97ab16c Introduce new MIPS1 direct mapped cache capacity detection logics. 2000-09-16 07:20:16 +00:00
jeffs
36c4252a17 Re-enable SR IE bit before calling syscall(). Matches Tohru's mips1 change. 2000-09-16 06:57:21 +00:00
nisimura
2982d7707b There is no need to handle processor master interrupt mask SR_INT_IE
in syscall() anymore.  By defition, processor was in SR_INT_IE turn
on prior to have syscall exception.  MIPS1 assembler hook arranges
to enable the bit for its own.  MIPS3 does the same effect by
turning off EXL bit.
2000-09-16 05:07:06 +00:00
nisimura
f4b74d3898 - Reimplement MIPS1 cache size dectection logic taking advantage of the
fact the direct mapped cache makes address alias effect.
- Just turn on processor master interrupt mask IEc (SR_INT_IE) bit prior
  to call syscall() kernel entry point.  IEp is always 1 in this case
  by defition.
2000-09-16 04:54:44 +00:00
chuck
9dc2f5ced0 IDT32364's Config register uses a different base for IC/DC (instruction
and data cache sizes).   R4000 uses 2^(12+IC) and 2^(12+DC).  IDT32364
uses 2^(9+IC) and 2^(9+DC).

abstract around the problem by making the base a parameter to the
MIPS3_CONFIG_CACHE_SIZE macro.   we pass the base down from mips_vector_init
to mips3_vector_init and to mips3_ConfigCache (where it is used).

XXX: someone with an MIPS3_4100 should switch to this and get rid
of the ugly ifdefs in cpuregs.h
2000-09-16 00:04:57 +00:00
jeffs
bdad8bae5b Handle R4K trap faults in user mode like overflows (deliver SIGFPE). This
prevents a panic running crashme.  Better comment for VCE define.
2000-09-15 06:50:46 +00:00
jeffs
efef8a5aa6 Do not save t* registers in syscall stub as suggested by cgd. Saves
a whole 0.01us in lmbench lat_syscall null on our 250Mhz QED system.
$at is still saved just to be safe, although it looks like it does
not need to be.  $v1 is used in syscall(), although I'm not sure why.
2000-09-13 06:48:04 +00:00
nisimura
0ba2036eee Introduce 'segbase' global variable to hold the pointer to current
process's segtab, retiring 'pcb_segtab' field from 'struct pcb'.
This would be another MULTIPROCESSOR unfriendly and the necessity
might be eliminated when the way to hold PTE is redesigned.
2000-09-13 01:53:00 +00:00
chuck
0dcdf1214c kill mips3_write_xcontext_upper 2000-09-13 01:20:41 +00:00
chuck
6f9229b2e6 modify mips3 locore to elminate the abuse of XContext
so that we can run on systems that do not have XContext
(e.g. IDT 32364).
2000-09-13 01:12:47 +00:00
soren
99418ce05f Remove old comment. 2000-09-12 15:40:36 +00:00
jeffs
bbcf1beea0 In outofworld, keep $sp for DDB case if it looks like a kernel address
so the stacktrace is ok.
2000-09-08 07:24:42 +00:00
jeffs
8f8a7ca780 Shuichiro URATA pointed out that the R4000 needs 3 nops. Other OSs make
it look at casual inspection like 1 nop is needed but play other tricks.
Still have reduced by 1 nop.  Hopefully this covers the NEC 41[x]1.  Could
not find info for those processors.
2000-09-07 20:31:02 +00:00
jeffs
8f2cc012b5 Remove 3 of the nops between tlbwr and eret in tlb miss handlers. They
were added early when adding the QED support.  RM5231 seems to work fine
w/o the extra nops.  Noticed by Chuck Cranor.
2000-09-06 06:33:42 +00:00
soren
c5ce14be0a Back out (most of) previous. I was using an 1.5 asm.h and hadn't
noticed cgd's fix..
2000-09-05 01:24:51 +00:00
soren
c3150dc3dc Add nop after PANIC macros. 2000-09-05 00:55:48 +00:00
jeffs
f8d9f59ed9 Correct _KERN_MCOUNT restoration of $t9.
From Ethan Solomita (ethan@geocast.com).
2000-08-30 22:31:12 +00:00
thorpej
4db6fc7542 Make need_resched() take a "struct cpu_info *" argument. This
causes gives a primitive form of processor affinity.  Its use in
roundrobin() still needs some work.
2000-08-25 01:04:06 +00:00
uch
2111496e74 Rewrote TX39 series cache routines. 2000-08-24 05:31:59 +00:00
thorpej
a86d1f4891 Add a lock around the scheduler, and use it as necessary, including
in the non-MULTIPROCESSOR case (LOCKDEBUG requires it).  Scheduler
lock is held upon entry to mi_switch() and cpu_switch(), and
cpu_switch() releases the lock before returning.

Largely from Bill Sommerfeld, with some minor bug fixes and
machine-dependent code hacking from me.
2000-08-20 21:50:06 +00:00
wdk
1e59559e3e intrcnt[] counters should be handled by the port specific interrupt handlers.
This change facilitates the migration from intrcnt[] to the new evcnt(9)
framework without breaking all of the mips based ports.
2000-08-14 04:36:34 +00:00
jeffs
95ac0dc817 In db_disasm() use fuword() to fetch user addresses. Mainly to avoid
bad EPCs from losing the initial ddb context when panicing, but also
helps with typos.
2000-08-10 22:31:26 +00:00
jeffs
6f9d8d6cd3 Tweak to compile with printf format changes. 2000-08-10 08:01:24 +00:00
jeffs
22bda73efd To be safe when called from interupt, [fs]uswintr need to preserve
cpu_onfault.  By Etan Solomita (ethan@geocast.com).
2000-08-09 23:03:24 +00:00
jeffs
0b5e00636a Fix a bug in how .S routines call _mcount to allocate stack before
use.  By Ethan Solomita (ethan@geocast.com).
2000-08-09 22:52:36 +00:00
tshiozak
51a53de0d5 Preparation for the future introduction of multibyte locale.
- MB_LEN_MAX is increased to 32.
 - To ensure binary compatibility for old executables
   under multibyte locale, versioned setlocale is added.
 - __mb_len_cur definision is added in setlocale.c
   and enable it in stdlib.h .
   It is also important for multibyte locale stuffs,
   but I just forgot.
2000-08-08 22:31:13 +00:00
shin
f0803f8192 protect doubleword register from interrupt. 2000-08-06 12:30:36 +00:00
jeffs
8d300a3b14 setregs() cache sync turns out not to be needed with kern_exec 1.104
(which was 2 weeks after our internal trees full sync).
2000-08-02 06:46:47 +00:00
jeffs
e1cf55c8a8 Make mips3_FlushICache() convert a0 into a KSEG0 + virtual index like
the _2way and mips3_FlushDCache(). This lets all mips3 cache ops accept
user virtual addresss w/o a tlb miss.  Since this is now done in both
ICache flush routines, no need to do it in pmap.c.  Fixed R4400
stability problems with setregs() cache flushing.
2000-08-01 23:38:26 +00:00
jeffs
e6bdec31fd Fix vmapbuf() to call uvm_km_valloc_perfer_wait() call, but trunc_page()
to the prefer arg so we free the correct page.
2000-08-01 22:45:05 +00:00
cgd
b63ed164a1 convert PRID handling to use macros on an int, not bit-fields.
there's no reason to use bit-fields, and they just complexity to
the header.
2000-07-27 17:29:05 +00:00
jeffs
3eae1609f1 Fix to actually compile MIPS1 only. 2000-07-27 08:28:36 +00:00
jeffs
e4a0934c13 Do not attempt mips3 style cache flush on mips1 in setregs() as it
is illegal to flush on user addresses.  In theory the race exists
on MIPS1, but it is rather unlikely in common use.  I have
seen it with regress/sys/kern/sigtramp on a QED 5231 system.
2000-07-27 06:28:06 +00:00
cgd
4adc7b9704 add nops after jals in PANIC and PRINTF. (these macros are often used in
code which has noreorder set, and they're not used with nops afterwards,
as is appropriate in that case, so put the nops in the macros.)
2000-07-27 05:01:06 +00:00
jeffs
ca2a49c4cf Back-out vmapbuf() change for now as locally it has been found to sleep
in some circumstances that don't sleep when not using pmap_prefer().
2000-07-26 16:24:38 +00:00
jeffs
71538e8894 Fix mips3 outofworld to panic cleanly even if shutdown path misses K2.
Previously we jal to panic which never cleared the tlb fault, so if
on the course of shutdown (like a doshutdownhooks() callback) missed
K2, it would panic again.  Fix by setting EPC to panic() and eret.
2000-07-25 18:06:49 +00:00
jeffs
3a90817270 Add option to apply additional mask to the SR at run-time for MIPS3 platforms.
By default this is off, and only slightly changes the code to load SR when
a temp register is available.  This can be used by the platform code to
handle slow to clear interrupts (our case) or to mask off any interrupt
any interrupt at run-time.  This can be very useful for embedded platforms
that have less than desirable interrupt properties.
2000-07-25 17:56:05 +00:00
jeffs
7dad7ceb84 Use new uvm_km_valloc_prefer_wait() in vmapbuf(). This lets the K2
mapping of b_data have the same virtual index, so the mapping does
not degenerate into uncached in pmap_enter().
2000-07-24 20:16:29 +00:00
jeffs
2ebdfcd251 Make pmap_prefer() use a global setting based on cache size
instead of assuming 64KB.   This allows best fit and will
support bigger caches.
2000-07-20 18:33:40 +00:00
jeffs
c8b819c2ed Include kgdb hooks in trap.c. Include bits of DDB code for kgdb also. Remove
some local prototypes that are in headers now.
2000-07-20 18:14:46 +00:00
jeffs
d8d3c52075 Move masked status and instr into jal cpu_intr delay slot. 2000-07-20 00:43:07 +00:00
jeffs
5938072101 In FPU excepton code, send SIGILL if no one claims the instruction.
SIGFPE is still delivered where appropriate.
2000-07-19 22:05:02 +00:00
jeffs
64d555c075 Improve outofworld: to include the vaddr. Removed unused mips3_Set64bit
and an #if 1.
2000-07-19 20:46:00 +00:00
jeffs
32ee71ac65 Fix stacktrace() to have an 8 byte aligned stack. On our platform previously
it would hang-up.  logstacktrace() actually was the same as stacktrace() so
just make it an XLEAF() for now.  Include some DDB code for KGDB compilation.
2000-07-19 18:56:36 +00:00
jeffs
8b8bf4501b At the start of the kernel, keep the MIPS3_SR_DIAG_BEV setting
on mips3 systems, until the kernel actually hooks the vectors.
This makes it easier to debug early problems if the firmware
has provides an exception handler.
2000-07-19 18:38:41 +00:00
jeffs
f7dacc7a8e Use spl*_noprof routines to raise and lower spl for kernel profiling.
This keeps the SR management more contained in locore, and should
be roughly the same performance as the .text size is less.  Talked
to simonb and he was ok with this change.
2000-07-18 06:25:32 +00:00
jeffs
8e5b35a55a Fix FP exception handling that was recently broken and would not
run src/regress cleanly.  Need to save and restore the frame pointer
for fpemul_sig*().
2000-07-18 00:41:18 +00:00
jeffs
5961b67774 if MIPS3_ENABLE_CLOCK_INTR is defined, set MIPS3_[HARD_]INT_MASK
appropriately.  This supports ports that use the internal clock.
Add 2 diag register defines that are specific to QED processors.
2000-07-17 23:35:13 +00:00
jeffs
0e0c4d24e8 Move platform db_trap callback from arch/mips into ddb as suggested by
jhawk.  This callback is used by platform code to manage things like
watchdogs that should be disabled while in ddb.  Done as a callback
for processors such as mips that support lots of different systems.
2000-07-17 19:57:49 +00:00
jeffs
efabca31b5 Make memcpy() the favored interface an swizzle the args for ovbcopy. Also
move bcopy XLEAF here from locore.S.  For 64b clean compilation add a
ld/sd section to the block copy.
2000-07-17 07:37:50 +00:00
jeffs
2fd0d88f44 Use <uvm/uvm_extern.h> instead of vm/vm.h 2000-07-17 07:06:13 +00:00
jeffs
116a6f8233 Pull in geocast mips ddb improvements and start bringing in kgdb support.
Add ddb support for QED opcodes, fill in enough routines so "next" usually
works, kdbpoke support for any size.  Add callback that ports can hook when
entering and leaving ddb.  This can be used for things like turning
off watchdogs while in ddb.
2000-07-17 07:04:19 +00:00
jeffs
ef9531850e Add comment that overriding the sysctl defines in machine/cpu.h
breaks userland binary compatiabiltiy between mips ports.  Move
check down so common values are always defined here.
2000-07-13 07:37:11 +00:00
jeffs
f6812b853b Only define machdep sysctls if CPU_MAXID is not defined by machine/cpu.h.
This lets mips ports have additional machdep sysctl.  Define CPUISMIPS3
for MIPS1+MIPS2 as cpu_arch >= 3 to support mips4.  Add cpu_intr()
prototype so this is defined in one place.
2000-07-11 06:34:57 +00:00
jeffs
6b28794054 Add support for 3 QED special2 opcodes. 2000-07-11 06:27:58 +00:00
jeffs
54a85cb3af For 64b clean 32b compilation, do not bother setting SX And KX.
The current code does not maintain these in SR, and they are not
needed by 32b kernel code for mips3/4 instructions.
2000-07-11 06:26:08 +00:00
soren
77e30d85bf Oops. 2000-07-11 01:15:47 +00:00
jeffs
dcbf69bf94 Update mips3_locore_vec cache functions for mips3_L1TwoWayCache. Add cast
for clean compilation with _MIPS_BSD_API_LP32_64CLEAN set.
2000-07-10 23:21:16 +00:00
jeffs
010c198b37 In setregs() flush sigreturn trampoline code from the d (MIPS3) and i cache.
Tested on geocast RM5231 platform.  This fixes a race in
regress/sys/kern/sigtramp.  Some other ports do the same thing.
2000-07-10 21:12:13 +00:00
uch
e8ebb2a377 use mips3 cache op.
invalidate -> write-back invalidate
(although NetBSD/hpcmips run on write-through mode.)
suggested by cgd.
2000-07-10 16:23:18 +00:00
cgd
a5c13f9ad4 Kwality control:
* put #includes of opt headers and headers to get protos used by
  net/netisr_dispatch.h in net/netisr.h (if !defined(_LOCORE)) (rather than
  in netisr_dispatch.h itself, and potentially nowhere, respectively).
* require netisr.h to be included before netisr_dispatch.h.
* minor additional cleanup of both netisr.h and netisr_dispatch.h.
* clean up uses to remove now-unnecessary header file inclusions, and
  local prototypes of the fns.
* convert netisr dispatch implementations which didn't use
  netisr_dispatch.h (pc532) to use it.
2000-07-02 04:40:33 +00:00
mrg
28d898391b remove include of <vm/vm.h>. <vm/vm.h> -> <uvm/uvm_extern.h> 2000-06-29 08:10:45 +00:00
cgd
7e975cacbe un-__P, clean up spacing a little bit, put fwd struct decl(s) near top
rather than embedded.  no functional changes.
2000-06-29 06:00:43 +00:00