2021-06-01 22:35:17 +03:00
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#
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# Power ISA decode for 32-bit insns (opcode space 0)
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#
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# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2.1 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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2021-06-01 22:35:18 +03:00
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2022-05-17 15:39:22 +03:00
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&A frt fra frb frc rc:bool
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@A ...... frt:5 fra:5 frb:5 frc:5 ..... rc:1 &A
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target/ppc: Move floating-point arithmetic instructions to decodetree.
This patch moves the below instructions to decodetree specification :
f{add, sub, mul, div, re, rsqrte, madd, msub, nmadd, nmsub}[s][.] : A-form
ft{div, sqrt} : X-form
With this patch, all the floating-point arithmetic instructions have been
moved to decodetree.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-15 09:44:22 +03:00
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&A_tab frt fra frb rc:bool
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@A_tab ...... frt:5 fra:5 frb:5 ..... ..... rc:1 &A_tab
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&A_tac frt fra frc rc:bool
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@A_tac ...... frt:5 fra:5 ..... frc:5 ..... rc:1 &A_tac
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2022-09-05 15:37:44 +03:00
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&A_tb frt frb rc:bool
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@A_tb ...... frt:5 ..... frb:5 ..... ..... rc:1 &A_tb
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target/ppc: Move cmp{rb, eqb}, tw[i], td[i], isel instructions to decodetree.
Moving the following instructions to decodetree specification :
cmp{rb, eqb}, t{w, d} : X-form
t{w, d}i : D-form
isel : A-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured using the '-d in_asm,op' flag.
Also for CMPRB, following review comments :
Replaced repetition of arithmetic right shifting (tcg_gen_shri_i32) followed
by extraction of last 8 bits (tcg_gen_ext8u_i32) with extraction of the required
bits using offsets (tcg_gen_extract_i32).
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
[np: 32-bit compile fix]
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-04-23 09:32:33 +03:00
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&A_tab_bc rt ra rb bc
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@A_tab_bc ...... rt:5 ra:5 rb:5 bc:5 ..... . &A_tab_bc
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2021-06-01 22:35:18 +03:00
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&D rt ra si:int64_t
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2022-06-29 19:28:54 +03:00
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@D ...... rt:5 ra:5 si:s16 &D
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2021-06-01 22:35:18 +03:00
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target/ppc: Move logical fixed-point instructions to decodetree.
Moving the below instructions to decodetree specification :
andi[s]., {ori, xori}[s] : D-form
{and, andc, nand, or, orc, nor, xor, eqv}[.],
exts{b, h, w}[.], cnt{l, t}z{w, d}[.],
popcnt{b, w, d}, prty{w, d}, cmp, bpermd : X-form
With this patch, all the fixed-point logical instructions have been
moved to decodetree.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
[np: 32-bit compile fix]
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-04-23 09:32:34 +03:00
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&D_ui rt ra ui:uint64_t
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@D_ui ...... rt:5 ra:5 ui:16 &D_ui
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2021-06-01 22:35:28 +03:00
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&D_bf bf l:bool ra imm
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2022-06-29 19:28:54 +03:00
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@D_bfs ...... bf:3 . l:1 ra:5 imm:s16 &D_bf
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@D_bfu ...... bf:3 . l:1 ra:5 imm:16 &D_bf
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2021-06-01 22:35:28 +03:00
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2021-10-29 23:23:55 +03:00
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%dq_si 4:s12 !function=times_16
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%dq_rtp 22:4 !function=times_2
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@DQ_rtp ...... ....0 ra:5 ............ .... &D rt=%dq_rtp si=%dq_si
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2021-11-04 15:37:06 +03:00
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%dq_rt_tsx 3:1 21:5
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@DQ_TSX ...... ..... ra:5 ............ .... &D si=%dq_si rt=%dq_rt_tsx
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2021-11-04 15:37:08 +03:00
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%rt_tsxp 21:1 22:4 !function=times_2
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@DQ_TSXP ...... ..... ra:5 ............ .... &D si=%dq_si rt=%rt_tsxp
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2021-06-01 22:35:20 +03:00
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%ds_si 2:s14 !function=times_4
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2022-06-29 19:28:54 +03:00
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@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
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2021-06-01 22:35:20 +03:00
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2021-10-29 23:23:55 +03:00
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%ds_rtp 22:4 !function=times_2
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@DS_rtp ...... ....0 ra:5 .............. .. &D rt=%ds_rtp si=%ds_si
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2021-12-17 19:57:13 +03:00
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&DX_b vrt b
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%dx_b 6:10 16:5 0:1
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@DX_b ...... vrt:5 ..... .......... ..... . &DX_b b=%dx_b
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2021-06-01 22:35:27 +03:00
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&DX rt d
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%dx_d 6:s10 16:5 0:1
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2022-06-29 19:28:54 +03:00
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@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
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2021-06-01 22:35:27 +03:00
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2021-11-04 15:37:03 +03:00
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&VA vrt vra vrb rc
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2022-06-29 19:28:54 +03:00
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@VA ...... vrt:5 vra:5 vrb:5 rc:5 ...... &VA
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2021-11-04 15:37:03 +03:00
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2022-03-02 08:51:37 +03:00
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&VC vrt vra vrb rc:bool
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@VC ...... vrt:5 vra:5 vrb:5 rc:1 .......... &VC
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2021-11-04 15:36:58 +03:00
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&VN vrt vra vrb sh
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@VN ...... vrt:5 vra:5 vrb:5 .. sh:3 ...... &VN
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2021-06-01 22:35:26 +03:00
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&VX vrt vra vrb
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2022-06-29 19:28:54 +03:00
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@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
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2021-06-01 22:35:26 +03:00
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2022-03-02 08:51:37 +03:00
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&VX_bf bf vra vrb
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@VX_bf ...... bf:3 .. vra:5 vrb:5 ........... &VX_bf
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2022-03-02 08:51:37 +03:00
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&VX_mp rt mp:bool vrb
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@VX_mp ...... rt:5 .... mp:1 vrb:5 ........... &VX_mp
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2022-03-02 08:51:37 +03:00
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&VX_n rt vrb n
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@VX_n ...... rt:5 .. n:3 vrb:5 ........... &VX_n
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2022-03-02 08:51:37 +03:00
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&VX_tb_rc vrt vrb rc:bool
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@VX_tb_rc ...... vrt:5 ..... vrb:5 rc:1 .......... &VX_tb_rc
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2021-11-04 15:37:00 +03:00
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&VX_uim4 vrt uim vrb
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2022-06-29 19:28:54 +03:00
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@VX_uim4 ...... vrt:5 . uim:4 vrb:5 ........... &VX_uim4
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2021-11-04 15:37:00 +03:00
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2021-12-17 19:57:13 +03:00
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&VX_tb vrt vrb
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2022-06-29 19:28:54 +03:00
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@VX_tb ...... vrt:5 ..... vrb:5 ........... &VX_tb
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2021-12-17 19:57:13 +03:00
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2021-06-01 22:35:20 +03:00
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&X rt ra rb
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2022-06-29 19:28:54 +03:00
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@X ...... rt:5 ra:5 rb:5 .......... . &X
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2021-06-01 22:35:20 +03:00
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2021-10-29 22:24:12 +03:00
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&X_rc rt ra rb rc:bool
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@X_rc ...... rt:5 ra:5 rb:5 .......... rc:1 &X_rc
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2022-06-29 19:29:03 +03:00
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&X_sa rs ra
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@X_sa ...... rs:5 ra:5 ..... .......... . &X_sa
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target/ppc: Move logical fixed-point instructions to decodetree.
Moving the below instructions to decodetree specification :
andi[s]., {ori, xori}[s] : D-form
{and, andc, nand, or, orc, nor, xor, eqv}[.],
exts{b, h, w}[.], cnt{l, t}z{w, d}[.],
popcnt{b, w, d}, prty{w, d}, cmp, bpermd : X-form
With this patch, all the fixed-point logical instructions have been
moved to decodetree.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
[np: 32-bit compile fix]
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-04-23 09:32:34 +03:00
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&X_sa_rc rs ra rc
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@X_sa_rc ...... rs:5 ra:5 ..... .......... rc:1 &X_sa_rc
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2021-10-29 22:24:12 +03:00
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%x_frtp 22:4 !function=times_2
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%x_frap 17:4 !function=times_2
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%x_frbp 12:4 !function=times_2
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@X_tp_ap_bp_rc ...... ....0 ....0 ....0 .......... rc:1 &X_rc rt=%x_frtp ra=%x_frap rb=%x_frbp
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@X_tp_a_bp_rc ...... ....0 ra:5 ....0 .......... rc:1 &X_rc rt=%x_frtp rb=%x_frbp
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2022-06-29 19:28:56 +03:00
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&X_t rt
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@X_t ...... rt:5 ..... ..... .......... . &X_t
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2022-03-30 20:59:31 +03:00
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&X_tb rt rb
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@X_tb ...... rt:5 ..... rb:5 .......... . &X_tb
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2022-06-29 19:28:58 +03:00
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&X_t_rc rt rc:bool
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@X_t_rc ...... rt:5 ..... ..... .......... rc:1 &X_t_rc
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2021-10-29 22:24:16 +03:00
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&X_tb_rc rt rb rc:bool
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@X_tb_rc ...... rt:5 ..... rb:5 .......... rc:1 &X_tb_rc
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@X_tbp_rc ...... ....0 ..... ....0 .......... rc:1 &X_tb_rc rt=%x_frtp rb=%x_frbp
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@X_tp_b_rc ...... ....0 ..... rb:5 .......... rc:1 &X_tb_rc rt=%x_frtp
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@X_t_bp_rc ...... rt:5 ..... ....0 .......... rc:1 &X_tb_rc rb=%x_frbp
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2021-06-01 22:35:24 +03:00
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&X_bi rt bi
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2022-06-29 19:28:54 +03:00
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@X_bi ...... rt:5 bi:5 ..... .......... . &X_bi
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2021-06-01 22:35:24 +03:00
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2021-10-29 22:24:13 +03:00
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&X_bf bf ra rb
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@X_bf ...... bf:3 .. ra:5 rb:5 .......... . &X_bf
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target/ppc: Move floating-point arithmetic instructions to decodetree.
This patch moves the below instructions to decodetree specification :
f{add, sub, mul, div, re, rsqrte, madd, msub, nmadd, nmsub}[s][.] : A-form
ft{div, sqrt} : X-form
With this patch, all the floating-point arithmetic instructions have been
moved to decodetree.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-15 09:44:22 +03:00
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&X_bf_b bf rb
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@X_bf_b ...... bf:3 .. ..... rb:5 .......... . &X_bf_b
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2021-10-29 22:24:13 +03:00
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@X_bf_ap_bp ...... bf:3 .. ....0 ....0 .......... . &X_bf ra=%x_frap rb=%x_frbp
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@X_bf_a_bp ...... bf:3 .. ra:5 ....0 .......... . &X_bf rb=%x_frbp
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&X_bf_uim bf uim rb
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@X_bf_uim ...... bf:3 . uim:6 rb:5 .......... . &X_bf_uim
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@X_bf_uim_bp ...... bf:3 . uim:6 ....0 .......... . &X_bf_uim rb=%x_frbp
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2021-06-01 22:35:28 +03:00
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&X_bfl bf l:bool ra rb
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2022-06-29 19:28:54 +03:00
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@X_bfl ...... bf:3 . l:1 ra:5 rb:5 .......... . &X_bfl
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2021-06-01 22:35:28 +03:00
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2022-06-29 19:28:55 +03:00
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&X_imm2 rt imm
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@X_imm2 ...... rt:5 ..... ... imm:2 .......... . &X_imm2
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2022-06-29 19:28:59 +03:00
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&X_imm3 rt imm
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@X_imm3 ...... rt:5 ..... .. imm:3 .......... . &X_imm3
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2021-11-04 15:37:13 +03:00
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%x_xt 0:1 21:5
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2022-03-02 08:51:38 +03:00
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&X_imm5 xt imm:uint8_t vrb
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@X_imm5 ...... ..... imm:5 vrb:5 .......... . &X_imm5 xt=%x_xt
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2021-11-04 15:37:13 +03:00
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&X_imm8 xt imm:uint8_t
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@X_imm8 ...... ..... .. imm:8 .......... . &X_imm8 xt=%x_xt
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2022-07-01 16:35:01 +03:00
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&X_ih ih:uint8_t
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@X_ih ...... .. ih:3 ..... ..... .......... . &X_ih
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2022-07-01 16:34:59 +03:00
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&X_rb rb
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@X_rb ...... ..... ..... rb:5 .......... . &X_rb
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2022-07-01 16:35:07 +03:00
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&X_rs_l rs l:bool
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@X_rs_l ...... rs:5 .... l:1 ..... .......... . &X_rs_l
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2021-11-04 15:37:18 +03:00
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&X_uim5 xt uim:uint8_t
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@X_uim5 ...... ..... ..... uim:5 .......... . &X_uim5 xt=%x_xt
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2021-10-29 22:24:17 +03:00
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&X_tb_sp_rc rt rb sp rc:bool
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@X_tb_sp_rc ...... rt:5 sp:2 ... rb:5 .......... rc:1 &X_tb_sp_rc
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@X_tbp_sp_rc ...... ....0 sp:2 ... ....0 .......... rc:1 &X_tb_sp_rc rt=%x_frtp rb=%x_frbp
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&X_tb_s_rc rt rb s:bool rc:bool
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@X_tb_s_rc ...... rt:5 s:1 .... rb:5 .......... rc:1 &X_tb_s_rc
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@X_tbp_s_rc ...... ....0 s:1 .... ....0 .......... rc:1 &X_tb_s_rc rt=%x_frtp rb=%x_frbp
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2021-11-04 15:37:07 +03:00
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%x_rt_tsx 0:1 21:5
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@X_TSX ...... ..... ra:5 rb:5 .......... . &X rt=%x_rt_tsx
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2021-11-04 15:37:09 +03:00
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@X_TSXP ...... ..... ra:5 rb:5 .......... . &X rt=%rt_tsxp
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2021-11-04 15:37:07 +03:00
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2022-07-15 23:54:38 +03:00
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%x_dw 0:1 21:5 !function=dw_compose_ea
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@X_DW ...... ..... ra:5 rb:5 .......... . &X rt=%x_dw
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2021-10-29 22:24:06 +03:00
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&X_frtp_vrb frtp vrb
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@X_frtp_vrb ...... ....0 ..... vrb:5 .......... . &X_frtp_vrb frtp=%x_frtp
|
|
|
|
|
|
2021-10-29 22:24:09 +03:00
|
|
|
&X_vrt_frbp vrt frbp
|
|
|
|
|
@X_vrt_frbp ...... vrt:5 ..... ....0 .......... . &X_vrt_frbp frbp=%x_frbp
|
|
|
|
|
|
2022-05-24 17:05:30 +03:00
|
|
|
&X_a ra
|
|
|
|
|
@X_a ...... ra:3 .. ..... ..... .......... . &X_a
|
|
|
|
|
|
2024-04-23 09:32:30 +03:00
|
|
|
&X_tl rt l
|
|
|
|
|
@X_tl ...... rt:5 ... l:2 ..... .......... . &X_tl
|
|
|
|
|
|
2024-02-14 12:40:27 +03:00
|
|
|
&XO rt ra rb oe:bool rc:bool
|
|
|
|
|
@XO ...... rt:5 ra:5 rb:5 oe:1 ......... rc:1 &XO
|
|
|
|
|
|
|
|
|
|
&XO_ta rt ra oe:bool rc:bool
|
|
|
|
|
@XO_ta ...... rt:5 ra:5 ..... oe:1 ......... rc:1 &XO_ta
|
|
|
|
|
|
2024-04-23 09:32:27 +03:00
|
|
|
&XO_tab_rc rt ra rb rc:bool
|
|
|
|
|
@XO_tab_rc ...... rt:5 ra:5 rb:5 . ......... rc:1 &XO_tab_rc
|
|
|
|
|
|
2021-12-17 19:57:18 +03:00
|
|
|
%xx_xt 0:1 21:5
|
|
|
|
|
%xx_xb 1:1 11:5
|
|
|
|
|
%xx_xa 2:1 16:5
|
2022-03-02 08:51:37 +03:00
|
|
|
%xx_xc 3:1 6:5
|
2022-03-02 08:51:38 +03:00
|
|
|
&XX2 xt xb
|
|
|
|
|
@XX2 ...... ..... ..... ..... ......... .. &XX2 xt=%xx_xt xb=%xx_xb
|
|
|
|
|
|
2022-05-17 15:39:25 +03:00
|
|
|
&XX2_uim xt xb uim:uint8_t
|
|
|
|
|
@XX2_uim2 ...... ..... ... uim:2 ..... ......... .. &XX2_uim xt=%xx_xt xb=%xx_xb
|
|
|
|
|
|
|
|
|
|
@XX2_uim4 ...... ..... . uim:4 ..... ......... .. &XX2_uim xt=%xx_xt xb=%xx_xb
|
2021-12-17 19:57:18 +03:00
|
|
|
|
target/ppc: Moved XVTSTDC[DS]P to decodetree
Moved XVTSTDCSP and XVTSTDCDP to decodetree an restructured the helper
to be simpler and do all decoding in the decodetree (so XB, XT and DCMX
are all calculated outside the helper).
Obs: The tests in this one are slightly different, these are the sum of
these instructions with all possible immediate and those instructions
are repeated 10 times.
xvtstdcsp:
rept loop master patch
8 12500 2,76402100 2,70699100 (-2.1%)
25 4000 2,64867100 2,67884100 (+1.1%)
100 1000 2,73806300 2,78701000 (+1.8%)
500 200 3,44666500 3,61027600 (+4.7%)
2500 40 5,85790200 6,47475500 (+10.5%)
8000 12 15,22102100 17,46062900 (+14.7%)
xvtstdcdp:
rept loop master patch
8 12500 2,11818000 1,61065300 (-24.0%)
25 4000 2,04573400 1,60132200 (-21.7%)
100 1000 2,13834100 1,69988100 (-20.5%)
500 200 2,73977000 2,48631700 (-9.3%)
2500 40 5,05067000 5,25914100 (+4.1%)
8000 12 14,60507800 15,93704900 (+9.1%)
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-11-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-19 15:50:38 +03:00
|
|
|
%xx_uim7 6:1 2:1 16:5
|
|
|
|
|
@XX2_uim7 ...... ..... ..... ..... .... . ... . .. &XX2_uim xt=%xx_xt xb=%xx_xb uim=%xx_uim7
|
|
|
|
|
|
target/ppc: Moved XSTSTDC[QDS]P to decodetree
Moved XSTSTDCSP, XSTSTDCDP and XSTSTDCQP to decodetree and moved some of
its decoding away from the helper as previously the DCMX, XB and BF were
calculated in the helper with the help of cpu_env, now that part was
moved to the decodetree with the rest.
xvtstdcsp:
rept loop master patch
8 12500 1,85393600 1,94683600 (+5.0%)
25 4000 1,78779800 1,92479000 (+7.7%)
100 1000 2,12775000 2,28895500 (+7.6%)
500 200 2,99655300 3,23102900 (+7.8%)
2500 40 6,89082200 7,44827500 (+8.1%)
8000 12 17,50585500 18,95152100 (+8.3%)
xvtstdcdp:
rept loop master patch
8 12500 1,39043100 1,33539800 (-4.0%)
25 4000 1,35731800 1,37347800 (+1.2%)
100 1000 1,51514800 1,56053000 (+3.0%)
500 200 2,21014400 2,47906000 (+12.2%)
2500 40 5,39488200 6,68766700 (+24.0%)
8000 12 13,98623900 18,17661900 (+30.0%)
xvtstdcdp:
rept loop master patch
8 12500 1,35123800 1,34455800 (-0.5%)
25 4000 1,36441200 1,36759600 (+0.2%)
100 1000 1,49763500 1,54138400 (+2.9%)
500 200 2,19020200 2,46196400 (+12.4%)
2500 40 5,39265700 6,68147900 (+23.9%)
8000 12 14,04163600 18,19669600 (+29.6%)
As some values are now decoded outside the helper and passed to it as an
argument the number of arguments of the helper increased, the number
of TCGop needed to load the arguments increased. I suspect that's why
the slow-down in the tests with a high REPT but low LOOP.
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-12-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-19 15:50:39 +03:00
|
|
|
&XX2_bf_uim bf xb uim
|
|
|
|
|
@XX2_bf_uim ...... bf:3 uim:7 ..... ......... . . &XX2_bf_uim
|
|
|
|
|
|
2022-03-02 08:51:38 +03:00
|
|
|
&XX2_bf_xb bf xb
|
|
|
|
|
@XX2_bf_xb ...... bf:3 .. ..... ..... ......... . . &XX2_bf_xb xb=%xx_xb
|
|
|
|
|
|
2021-12-17 19:57:18 +03:00
|
|
|
&XX3 xt xa xb
|
|
|
|
|
@XX3 ...... ..... ..... ..... ........ ... &XX3 xt=%xx_xt xa=%xx_xa xb=%xx_xb
|
2021-11-04 15:37:12 +03:00
|
|
|
|
2024-06-18 11:58:31 +03:00
|
|
|
&XX3_rc xt xa xb rc:bool
|
|
|
|
|
@XX3_rc ...... ..... ..... ..... rc:1 ....... ... &XX3_rc xt=%xx_xt xa=%xx_xa xb=%xx_xb
|
|
|
|
|
|
2022-05-24 17:05:31 +03:00
|
|
|
# 32 bit GER instructions have all mask bits considered 1
|
|
|
|
|
&MMIRR_XX3 xa xb xt pmsk xmsk ymsk
|
|
|
|
|
%xx_at 23:3
|
2022-05-24 17:05:33 +03:00
|
|
|
%xx_xa_pair 2:1 17:4 !function=times_2
|
2022-05-24 17:05:31 +03:00
|
|
|
@XX3_at ...... ... .. ..... ..... ........ ... &MMIRR_XX3 xt=%xx_at xb=%xx_xb \
|
|
|
|
|
pmsk=255 xmsk=15 ymsk=15
|
|
|
|
|
|
2022-03-02 08:51:38 +03:00
|
|
|
&XX3_dm xt xa xb dm
|
|
|
|
|
@XX3_dm ...... ..... ..... ..... . dm:2 ..... ... &XX3_dm xt=%xx_xt xa=%xx_xa xb=%xx_xb
|
|
|
|
|
|
2022-03-02 08:51:37 +03:00
|
|
|
&XX4 xt xa xb xc
|
|
|
|
|
@XX4 ...... ..... ..... ..... ..... .. .... &XX4 xt=%xx_xt xa=%xx_xa xb=%xx_xb xc=%xx_xc
|
|
|
|
|
|
2021-10-29 22:24:11 +03:00
|
|
|
&Z22_bf_fra bf fra dm
|
|
|
|
|
@Z22_bf_fra ...... bf:3 .. fra:5 dm:6 ......... . &Z22_bf_fra
|
|
|
|
|
|
|
|
|
|
%z22_frap 17:4 !function=times_2
|
|
|
|
|
@Z22_bf_frap ...... bf:3 .. ....0 dm:6 ......... . &Z22_bf_fra fra=%z22_frap
|
|
|
|
|
|
2021-10-29 22:24:17 +03:00
|
|
|
&Z22_ta_sh_rc rt ra sh rc:bool
|
|
|
|
|
@Z22_ta_sh_rc ...... rt:5 ra:5 sh:6 ......... rc:1 &Z22_ta_sh_rc
|
|
|
|
|
|
|
|
|
|
%z22_frtp 22:4 !function=times_2
|
|
|
|
|
@Z22_tap_sh_rc ...... ....0 ....0 sh:6 ......... rc:1 &Z22_ta_sh_rc rt=%z22_frtp ra=%z22_frap
|
|
|
|
|
|
2021-10-29 22:24:15 +03:00
|
|
|
&Z23_tab frt fra frb rmc rc:bool
|
|
|
|
|
@Z23_tab ...... frt:5 fra:5 frb:5 rmc:2 ........ rc:1 &Z23_tab
|
2021-10-29 22:24:14 +03:00
|
|
|
|
|
|
|
|
%z23_frtp 22:4 !function=times_2
|
2021-10-29 22:24:15 +03:00
|
|
|
%z23_frap 17:4 !function=times_2
|
2021-10-29 22:24:14 +03:00
|
|
|
%z23_frbp 12:4 !function=times_2
|
2021-10-29 22:24:15 +03:00
|
|
|
@Z23_tabp ...... ....0 ....0 ....0 rmc:2 ........ rc:1 &Z23_tab frt=%z23_frtp fra=%z23_frap frb=%z23_frbp
|
|
|
|
|
|
|
|
|
|
@Z23_tp_a_bp ...... ....0 fra:5 ....0 rmc:2 ........ rc:1 &Z23_tab frt=%z23_frtp frb=%z23_frbp
|
|
|
|
|
|
|
|
|
|
&Z23_tb frt frb r:bool rmc rc:bool
|
|
|
|
|
@Z23_tb ...... frt:5 .... r:1 frb:5 rmc:2 ........ rc:1 &Z23_tb
|
|
|
|
|
|
2021-10-29 22:24:14 +03:00
|
|
|
@Z23_tbp ...... ....0 .... r:1 ....0 rmc:2 ........ rc:1 &Z23_tb frt=%z23_frtp frb=%z23_frbp
|
|
|
|
|
|
|
|
|
|
&Z23_te_tb te frt frb rmc rc:bool
|
|
|
|
|
@Z23_te_tb ...... frt:5 te:5 frb:5 rmc:2 ........ rc:1 &Z23_te_tb
|
|
|
|
|
|
|
|
|
|
@Z23_te_tbp ...... ....0 te:5 ....0 rmc:2 ........ rc:1 &Z23_te_tb frt=%z23_frtp frb=%z23_frbp
|
|
|
|
|
|
2021-06-01 22:35:20 +03:00
|
|
|
### Fixed-Point Load Instructions
|
|
|
|
|
|
|
|
|
|
LBZ 100010 ..... ..... ................ @D
|
|
|
|
|
LBZU 100011 ..... ..... ................ @D
|
|
|
|
|
LBZX 011111 ..... ..... ..... 0001010111 - @X
|
|
|
|
|
LBZUX 011111 ..... ..... ..... 0001110111 - @X
|
|
|
|
|
|
|
|
|
|
LHZ 101000 ..... ..... ................ @D
|
|
|
|
|
LHZU 101001 ..... ..... ................ @D
|
|
|
|
|
LHZX 011111 ..... ..... ..... 0100010111 - @X
|
|
|
|
|
LHZUX 011111 ..... ..... ..... 0100110111 - @X
|
|
|
|
|
|
|
|
|
|
LHA 101010 ..... ..... ................ @D
|
|
|
|
|
LHAU 101011 ..... ..... ................ @D
|
|
|
|
|
LHAX 011111 ..... ..... ..... 0101010111 - @X
|
|
|
|
|
LHAXU 011111 ..... ..... ..... 0101110111 - @X
|
|
|
|
|
|
|
|
|
|
LWZ 100000 ..... ..... ................ @D
|
|
|
|
|
LWZU 100001 ..... ..... ................ @D
|
|
|
|
|
LWZX 011111 ..... ..... ..... 0000010111 - @X
|
|
|
|
|
LWZUX 011111 ..... ..... ..... 0000110111 - @X
|
|
|
|
|
|
|
|
|
|
LWA 111010 ..... ..... ..............10 @DS
|
|
|
|
|
LWAX 011111 ..... ..... ..... 0101010101 - @X
|
|
|
|
|
LWAUX 011111 ..... ..... ..... 0101110101 - @X
|
|
|
|
|
|
|
|
|
|
LD 111010 ..... ..... ..............00 @DS
|
|
|
|
|
LDU 111010 ..... ..... ..............01 @DS
|
|
|
|
|
LDX 011111 ..... ..... ..... 0000010101 - @X
|
|
|
|
|
LDUX 011111 ..... ..... ..... 0000110101 - @X
|
|
|
|
|
|
2021-10-29 23:23:55 +03:00
|
|
|
LQ 111000 ..... ..... ............ ---- @DQ_rtp
|
|
|
|
|
|
2021-06-01 22:35:22 +03:00
|
|
|
### Fixed-Point Store Instructions
|
|
|
|
|
|
|
|
|
|
STB 100110 ..... ..... ................ @D
|
|
|
|
|
STBU 100111 ..... ..... ................ @D
|
|
|
|
|
STBX 011111 ..... ..... ..... 0011010111 - @X
|
|
|
|
|
STBUX 011111 ..... ..... ..... 0011110111 - @X
|
|
|
|
|
|
|
|
|
|
STH 101100 ..... ..... ................ @D
|
|
|
|
|
STHU 101101 ..... ..... ................ @D
|
|
|
|
|
STHX 011111 ..... ..... ..... 0110010111 - @X
|
|
|
|
|
STHUX 011111 ..... ..... ..... 0110110111 - @X
|
|
|
|
|
|
|
|
|
|
STW 100100 ..... ..... ................ @D
|
|
|
|
|
STWU 100101 ..... ..... ................ @D
|
|
|
|
|
STWX 011111 ..... ..... ..... 0010010111 - @X
|
|
|
|
|
STWUX 011111 ..... ..... ..... 0010110111 - @X
|
|
|
|
|
|
|
|
|
|
STD 111110 ..... ..... ..............00 @DS
|
|
|
|
|
STDU 111110 ..... ..... ..............01 @DS
|
|
|
|
|
STDX 011111 ..... ..... ..... 0010010101 - @X
|
|
|
|
|
STDUX 011111 ..... ..... ..... 0010110101 - @X
|
|
|
|
|
|
2021-10-29 23:23:55 +03:00
|
|
|
STQ 111110 ..... ..... ..............10 @DS_rtp
|
|
|
|
|
|
2021-06-01 22:35:28 +03:00
|
|
|
### Fixed-Point Compare Instructions
|
|
|
|
|
|
|
|
|
|
CMP 011111 ... - . ..... ..... 0000000000 - @X_bfl
|
|
|
|
|
CMPL 011111 ... - . ..... ..... 0000100000 - @X_bfl
|
|
|
|
|
CMPI 001011 ... - . ..... ................ @D_bfs
|
|
|
|
|
CMPLI 001010 ... - . ..... ................ @D_bfu
|
target/ppc: Move cmp{rb, eqb}, tw[i], td[i], isel instructions to decodetree.
Moving the following instructions to decodetree specification :
cmp{rb, eqb}, t{w, d} : X-form
t{w, d}i : D-form
isel : A-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured using the '-d in_asm,op' flag.
Also for CMPRB, following review comments :
Replaced repetition of arithmetic right shifting (tcg_gen_shri_i32) followed
by extraction of last 8 bits (tcg_gen_ext8u_i32) with extraction of the required
bits using offsets (tcg_gen_extract_i32).
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
[np: 32-bit compile fix]
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-04-23 09:32:33 +03:00
|
|
|
CMPRB 011111 ... - . ..... ..... 0011000000 - @X_bfl
|
|
|
|
|
CMPEQB 011111 ... -- ..... ..... 0011100000 - @X_bf
|
|
|
|
|
|
|
|
|
|
### Fixed-Point Trap Instructions
|
|
|
|
|
|
|
|
|
|
TW 011111 ..... ..... ..... 0000000100 - @X
|
|
|
|
|
TD 011111 ..... ..... ..... 0001000100 - @X
|
|
|
|
|
TWI 000011 ..... ..... ................ @D
|
|
|
|
|
TDI 000010 ..... ..... ................ @D
|
|
|
|
|
|
|
|
|
|
### Fixed-Point Select Instruction
|
|
|
|
|
|
|
|
|
|
ISEL 011111 ..... ..... ..... ..... 01111 - @A_tab_bc
|
2021-06-01 22:35:28 +03:00
|
|
|
|
2021-06-01 22:35:18 +03:00
|
|
|
### Fixed-Point Arithmetic Instructions
|
|
|
|
|
|
2024-02-14 12:40:27 +03:00
|
|
|
ADD 011111 ..... ..... ..... . 100001010 . @XO
|
|
|
|
|
ADDC 011111 ..... ..... ..... . 000001010 . @XO
|
|
|
|
|
ADDE 011111 ..... ..... ..... . 010001010 . @XO
|
|
|
|
|
|
|
|
|
|
# ADDEX is Z23-form, with CY=0; all other values for CY are reserved.
|
|
|
|
|
# This works out the same as X-form.
|
|
|
|
|
ADDEX 011111 ..... ..... ..... 00 10101010 - @X
|
|
|
|
|
|
2021-06-01 22:35:18 +03:00
|
|
|
ADDI 001110 ..... ..... ................ @D
|
|
|
|
|
ADDIS 001111 ..... ..... ................ @D
|
2024-02-14 12:40:27 +03:00
|
|
|
ADDIC 001100 ..... ..... ................ @D
|
|
|
|
|
ADDIC_ 001101 ..... ..... ................ @D
|
2021-06-01 22:35:24 +03:00
|
|
|
|
2021-06-01 22:35:27 +03:00
|
|
|
ADDPCIS 010011 ..... ..... .......... 00010 . @DX
|
2024-02-14 12:40:27 +03:00
|
|
|
ADDME 011111 ..... ..... ----- . 011101010 . @XO_ta
|
|
|
|
|
ADDZE 011111 ..... ..... ----- . 011001010 . @XO_ta
|
|
|
|
|
|
|
|
|
|
SUBF 011111 ..... ..... ..... . 000101000 . @XO
|
|
|
|
|
SUBFIC 001000 ..... ..... ................ @D
|
|
|
|
|
SUBFC 011111 ..... ..... ..... . 000001000 . @XO
|
|
|
|
|
SUBFE 011111 ..... ..... ..... . 010001000 . @XO
|
|
|
|
|
|
|
|
|
|
SUBFME 011111 ..... ..... ----- . 011101000 . @XO_ta
|
|
|
|
|
SUBFZE 011111 ..... ..... ----- . 011001000 . @XO_ta
|
2021-06-01 22:35:27 +03:00
|
|
|
|
2024-04-23 09:32:27 +03:00
|
|
|
MULLI 000111 ..... ..... ................ @D
|
|
|
|
|
MULLW 011111 ..... ..... ..... 0 011101011 . @XO_tab_rc
|
|
|
|
|
MULLWO 011111 ..... ..... ..... 1 011101011 . @XO_tab_rc
|
|
|
|
|
MULHW 011111 ..... ..... ..... - 001001011 . @XO_tab_rc
|
|
|
|
|
MULHWU 011111 ..... ..... ..... - 000001011 . @XO_tab_rc
|
|
|
|
|
|
2024-04-23 09:32:29 +03:00
|
|
|
DIVW 011111 ..... ..... ..... . 111101011 . @XO
|
|
|
|
|
DIVWU 011111 ..... ..... ..... . 111001011 . @XO
|
|
|
|
|
DIVWE 011111 ..... ..... ..... . 110101011 . @XO
|
|
|
|
|
DIVWEU 011111 ..... ..... ..... . 110001011 . @XO
|
|
|
|
|
|
2024-04-23 09:32:30 +03:00
|
|
|
MODSW 011111 ..... ..... ..... 1100001011 - @X
|
|
|
|
|
MODUW 011111 ..... ..... ..... 0100001011 - @X
|
|
|
|
|
DARN 011111 ..... --- .. ----- 1011110011 - @X_tl
|
|
|
|
|
NEG 011111 ..... ..... ----- . 001101000 . @XO_ta
|
|
|
|
|
|
2024-04-23 09:32:31 +03:00
|
|
|
MULLD 011111 ..... ..... ..... 0 011101001 . @XO_tab_rc
|
|
|
|
|
MULLDO 011111 ..... ..... ..... 1 011101001 . @XO_tab_rc
|
|
|
|
|
MULHD 011111 ..... ..... ..... - 001001001 . @XO_tab_rc
|
|
|
|
|
MULHDU 011111 ..... ..... ..... - 000001001 . @XO_tab_rc
|
|
|
|
|
|
|
|
|
|
MADDLD 000100 ..... ..... ..... ..... 110011 @VA
|
|
|
|
|
MADDHD 000100 ..... ..... ..... ..... 110000 @VA
|
|
|
|
|
MADDHDU 000100 ..... ..... ..... ..... 110001 @VA
|
|
|
|
|
|
2024-04-23 09:32:32 +03:00
|
|
|
DIVD 011111 ..... ..... ..... . 111101001 . @XO
|
|
|
|
|
DIVDU 011111 ..... ..... ..... . 111001001 . @XO
|
|
|
|
|
DIVDE 011111 ..... ..... ..... . 110101001 . @XO
|
|
|
|
|
DIVDEU 011111 ..... ..... ..... . 110001001 . @XO
|
|
|
|
|
|
|
|
|
|
MODSD 011111 ..... ..... ..... 1100001001 - @X
|
|
|
|
|
MODUD 011111 ..... ..... ..... 0100001001 - @X
|
|
|
|
|
|
2021-06-01 22:35:25 +03:00
|
|
|
## Fixed-Point Logical Instructions
|
|
|
|
|
|
target/ppc: Move logical fixed-point instructions to decodetree.
Moving the below instructions to decodetree specification :
andi[s]., {ori, xori}[s] : D-form
{and, andc, nand, or, orc, nor, xor, eqv}[.],
exts{b, h, w}[.], cnt{l, t}z{w, d}[.],
popcnt{b, w, d}, prty{w, d}, cmp, bpermd : X-form
With this patch, all the fixed-point logical instructions have been
moved to decodetree.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
[np: 32-bit compile fix]
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-04-23 09:32:34 +03:00
|
|
|
ANDI_ 011100 ..... ..... ................ @D_ui
|
|
|
|
|
ANDIS_ 011101 ..... ..... ................ @D_ui
|
|
|
|
|
ORI 011000 ..... ..... ................ @D_ui
|
|
|
|
|
ORIS 011001 ..... ..... ................ @D_ui
|
|
|
|
|
XORI 011010 ..... ..... ................ @D_ui
|
|
|
|
|
XORIS 011011 ..... ..... ................ @D_ui
|
|
|
|
|
|
|
|
|
|
AND 011111 ..... ..... ..... 0000011100 . @X_rc
|
|
|
|
|
ANDC 011111 ..... ..... ..... 0000111100 . @X_rc
|
|
|
|
|
NAND 011111 ..... ..... ..... 0111011100 . @X_rc
|
|
|
|
|
OR 011111 ..... ..... ..... 0110111100 . @X_rc
|
|
|
|
|
ORC 011111 ..... ..... ..... 0110011100 . @X_rc
|
|
|
|
|
NOR 011111 ..... ..... ..... 0001111100 . @X_rc
|
|
|
|
|
XOR 011111 ..... ..... ..... 0100111100 . @X_rc
|
|
|
|
|
EQV 011111 ..... ..... ..... 0100011100 . @X_rc
|
|
|
|
|
CMPB 011111 ..... ..... ..... 0111111100 . @X_rc
|
|
|
|
|
|
|
|
|
|
EXTSB 011111 ..... ..... ----- 1110111010 . @X_sa_rc
|
|
|
|
|
EXTSH 011111 ..... ..... ----- 1110011010 . @X_sa_rc
|
|
|
|
|
EXTSW 011111 ..... ..... ----- 1111011010 . @X_sa_rc
|
|
|
|
|
CNTLZW 011111 ..... ..... ----- 0000011010 . @X_sa_rc
|
|
|
|
|
CNTTZW 011111 ..... ..... ----- 1000011010 . @X_sa_rc
|
|
|
|
|
CNTLZD 011111 ..... ..... ----- 0000111010 . @X_sa_rc
|
|
|
|
|
CNTTZD 011111 ..... ..... ----- 1000111010 . @X_sa_rc
|
|
|
|
|
POPCNTB 011111 ..... ..... ----- 0001111010 . @X_sa_rc
|
|
|
|
|
|
|
|
|
|
POPCNTW 011111 ..... ..... ----- 0101111010 - @X_sa
|
|
|
|
|
POPCNTD 011111 ..... ..... ----- 0111111010 - @X_sa
|
|
|
|
|
PRTYW 011111 ..... ..... ----- 0010011010 - @X_sa
|
|
|
|
|
PRTYD 011111 ..... ..... ----- 0010111010 - @X_sa
|
|
|
|
|
|
|
|
|
|
BPERMD 011111 ..... ..... ..... 0011111100 - @X
|
2021-06-01 22:35:25 +03:00
|
|
|
CFUGED 011111 ..... ..... ..... 0011011100 - @X
|
2021-10-29 23:23:57 +03:00
|
|
|
CNTLZDM 011111 ..... ..... ..... 0000111011 - @X
|
2021-10-29 23:23:58 +03:00
|
|
|
CNTTZDM 011111 ..... ..... ..... 1000111011 - @X
|
2021-10-29 23:23:59 +03:00
|
|
|
PDEPD 011111 ..... ..... ..... 0010011100 - @X
|
2021-10-29 23:24:00 +03:00
|
|
|
PEXTD 011111 ..... ..... ..... 0010111100 - @X
|
2021-06-01 22:35:25 +03:00
|
|
|
|
2022-07-15 23:54:38 +03:00
|
|
|
# Fixed-Point Hash Instructions
|
|
|
|
|
|
|
|
|
|
HASHST 011111 ..... ..... ..... 1011010010 . @X_DW
|
|
|
|
|
HASHCHK 011111 ..... ..... ..... 1011110010 . @X_DW
|
2022-07-15 23:54:39 +03:00
|
|
|
HASHSTP 011111 ..... ..... ..... 1010010010 . @X_DW
|
|
|
|
|
HASHCHKP 011111 ..... ..... ..... 1010110010 . @X_DW
|
2022-07-15 23:54:38 +03:00
|
|
|
|
2022-06-29 19:29:02 +03:00
|
|
|
## BCD Assist
|
|
|
|
|
|
|
|
|
|
ADDG6S 011111 ..... ..... ..... - 001001010 - @X
|
2022-06-29 19:29:04 +03:00
|
|
|
CDTBCD 011111 ..... ..... ----- 0100011010 - @X_sa
|
2022-06-29 19:29:03 +03:00
|
|
|
CBCDTD 011111 ..... ..... ----- 0100111010 - @X_sa
|
2022-06-29 19:29:02 +03:00
|
|
|
|
target/ppc: Move load and store floating point instructions to decodetree
Move load floating point instructions (lfs, lfsu, lfsx, lfsux, lfd, lfdu, lfdx, lfdux)
and store floating point instructions(stfs, stfsu, stfsx, stfsux, stfd, stfdu, stfdx,
stfdux) from legacy system to decodetree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fernando Eckhardt Valle <fernando.valle@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211029202424.175401-4-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-10-29 23:23:53 +03:00
|
|
|
### Float-Point Load Instructions
|
|
|
|
|
|
|
|
|
|
LFS 110000 ..... ..... ................ @D
|
|
|
|
|
LFSU 110001 ..... ..... ................ @D
|
|
|
|
|
LFSX 011111 ..... ..... ..... 1000010111 - @X
|
|
|
|
|
LFSUX 011111 ..... ..... ..... 1000110111 - @X
|
|
|
|
|
|
|
|
|
|
LFD 110010 ..... ..... ................ @D
|
|
|
|
|
LFDU 110011 ..... ..... ................ @D
|
|
|
|
|
LFDX 011111 ..... ..... ..... 1001010111 - @X
|
|
|
|
|
LFDUX 011111 ..... ..... ..... 1001110111 - @X
|
|
|
|
|
|
|
|
|
|
### Float-Point Store Instructions
|
|
|
|
|
|
|
|
|
|
STFS 110100 ..... ...... ............... @D
|
|
|
|
|
STFSU 110101 ..... ...... ............... @D
|
|
|
|
|
STFSX 011111 ..... ...... .... 1010010111 - @X
|
|
|
|
|
STFSUX 011111 ..... ...... .... 1010110111 - @X
|
|
|
|
|
|
|
|
|
|
STFD 110110 ..... ...... ............... @D
|
|
|
|
|
STFDU 110111 ..... ...... ............... @D
|
|
|
|
|
STFDX 011111 ..... ...... .... 1011010111 - @X
|
|
|
|
|
STFDUX 011111 ..... ...... .... 1011110111 - @X
|
|
|
|
|
|
2022-09-05 15:37:44 +03:00
|
|
|
### Floating-Point Arithmetic Instructions
|
|
|
|
|
|
target/ppc: Move floating-point arithmetic instructions to decodetree.
This patch moves the below instructions to decodetree specification :
f{add, sub, mul, div, re, rsqrte, madd, msub, nmadd, nmsub}[s][.] : A-form
ft{div, sqrt} : X-form
With this patch, all the floating-point arithmetic instructions have been
moved to decodetree.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-15 09:44:22 +03:00
|
|
|
FADD 111111 ..... ..... ..... ----- 10101 . @A_tab
|
|
|
|
|
FADDS 111011 ..... ..... ..... ----- 10101 . @A_tab
|
|
|
|
|
|
|
|
|
|
FSUB 111111 ..... ..... ..... ----- 10100 . @A_tab
|
|
|
|
|
FSUBS 111011 ..... ..... ..... ----- 10100 . @A_tab
|
|
|
|
|
|
|
|
|
|
FMUL 111111 ..... ..... ----- ..... 11001 . @A_tac
|
|
|
|
|
FMULS 111011 ..... ..... ----- ..... 11001 . @A_tac
|
|
|
|
|
|
|
|
|
|
FDIV 111111 ..... ..... ..... ----- 10010 . @A_tab
|
|
|
|
|
FDIVS 111011 ..... ..... ..... ----- 10010 . @A_tab
|
|
|
|
|
|
2022-09-05 15:37:44 +03:00
|
|
|
FSQRT 111111 ..... ----- ..... ----- 10110 . @A_tb
|
2022-09-05 15:37:45 +03:00
|
|
|
FSQRTS 111011 ..... ----- ..... ----- 10110 . @A_tb
|
2022-09-05 15:37:44 +03:00
|
|
|
|
target/ppc: Move floating-point arithmetic instructions to decodetree.
This patch moves the below instructions to decodetree specification :
f{add, sub, mul, div, re, rsqrte, madd, msub, nmadd, nmsub}[s][.] : A-form
ft{div, sqrt} : X-form
With this patch, all the floating-point arithmetic instructions have been
moved to decodetree.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-15 09:44:22 +03:00
|
|
|
FRE 111111 ..... ----- ..... ----- 11000 . @A_tb
|
|
|
|
|
FRES 111011 ..... ----- ..... ----- 11000 . @A_tb
|
|
|
|
|
|
|
|
|
|
FRSQRTE 111111 ..... ----- ..... ----- 11010 . @A_tb
|
|
|
|
|
FRSQRTES 111011 ..... ----- ..... ----- 11010 . @A_tb
|
|
|
|
|
|
|
|
|
|
FTDIV 111111 ... -- ..... ..... 0010000000 - @X_bf
|
|
|
|
|
FTSQRT 111111 ... -- ----- ..... 0010100000 - @X_bf_b
|
|
|
|
|
|
|
|
|
|
FMADD 111111 ..... ..... ..... ..... 11101 . @A
|
|
|
|
|
FMADDS 111011 ..... ..... ..... ..... 11101 . @A
|
|
|
|
|
|
|
|
|
|
FMSUB 111111 ..... ..... ..... ..... 11100 . @A
|
|
|
|
|
FMSUBS 111011 ..... ..... ..... ..... 11100 . @A
|
|
|
|
|
|
|
|
|
|
FNMADD 111111 ..... ..... ..... ..... 11111 . @A
|
|
|
|
|
FNMADDS 111011 ..... ..... ..... ..... 11111 . @A
|
|
|
|
|
|
|
|
|
|
FNMSUB 111111 ..... ..... ..... ..... 11110 . @A
|
|
|
|
|
FNMSUBS 111011 ..... ..... ..... ..... 11110 . @A
|
|
|
|
|
|
2022-05-17 15:39:22 +03:00
|
|
|
### Floating-Point Select Instruction
|
|
|
|
|
|
|
|
|
|
FSEL 111111 ..... ..... ..... ..... 10111 . @A
|
|
|
|
|
|
2021-06-01 22:35:24 +03:00
|
|
|
### Move To/From System Register Instructions
|
|
|
|
|
|
|
|
|
|
SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
|
|
|
|
|
SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
|
|
|
|
|
SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
|
|
|
|
|
SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
|
2021-06-01 22:35:26 +03:00
|
|
|
|
2022-06-29 19:28:55 +03:00
|
|
|
### Move To/From FPSCR
|
|
|
|
|
|
2023-05-10 14:19:13 +03:00
|
|
|
{
|
|
|
|
|
# Before Power ISA v3.0, MFFS bits 11~15 were reserved and should be ignored
|
|
|
|
|
MFFS_ISA207 111111 ..... ----- ----- 1001000111 . @X_t_rc
|
|
|
|
|
[
|
|
|
|
|
MFFS 111111 ..... 00000 ----- 1001000111 . @X_t_rc
|
|
|
|
|
MFFSCE 111111 ..... 00001 ----- 1001000111 - @X_t
|
|
|
|
|
MFFSCRN 111111 ..... 10110 ..... 1001000111 - @X_tb
|
|
|
|
|
MFFSCDRN 111111 ..... 10100 ..... 1001000111 - @X_tb
|
|
|
|
|
MFFSCRNI 111111 ..... 10111 ---.. 1001000111 - @X_imm2
|
|
|
|
|
MFFSCDRNI 111111 ..... 10101 --... 1001000111 - @X_imm3
|
|
|
|
|
MFFSL 111111 ..... 11000 ----- 1001000111 - @X_t
|
|
|
|
|
]
|
|
|
|
|
}
|
2022-06-29 19:28:55 +03:00
|
|
|
|
2021-10-29 22:24:12 +03:00
|
|
|
### Decimal Floating-Point Arithmetic Instructions
|
|
|
|
|
|
|
|
|
|
DADD 111011 ..... ..... ..... 0000000010 . @X_rc
|
|
|
|
|
DADDQ 111111 ..... ..... ..... 0000000010 . @X_tp_ap_bp_rc
|
|
|
|
|
|
|
|
|
|
DSUB 111011 ..... ..... ..... 1000000010 . @X_rc
|
|
|
|
|
DSUBQ 111111 ..... ..... ..... 1000000010 . @X_tp_ap_bp_rc
|
|
|
|
|
|
|
|
|
|
DMUL 111011 ..... ..... ..... 0000100010 . @X_rc
|
|
|
|
|
DMULQ 111111 ..... ..... ..... 0000100010 . @X_tp_ap_bp_rc
|
|
|
|
|
|
|
|
|
|
DDIV 111011 ..... ..... ..... 1000100010 . @X_rc
|
|
|
|
|
DDIVQ 111111 ..... ..... ..... 1000100010 . @X_tp_ap_bp_rc
|
|
|
|
|
|
2021-10-29 22:24:13 +03:00
|
|
|
### Decimal Floating-Point Compare Instructions
|
|
|
|
|
|
|
|
|
|
DCMPU 111011 ... -- ..... ..... 1010000010 - @X_bf
|
|
|
|
|
DCMPUQ 111111 ... -- ..... ..... 1010000010 - @X_bf_ap_bp
|
|
|
|
|
|
|
|
|
|
DCMPO 111011 ... -- ..... ..... 0010000010 - @X_bf
|
|
|
|
|
DCMPOQ 111111 ... -- ..... ..... 0010000010 - @X_bf_ap_bp
|
|
|
|
|
|
2021-10-29 22:24:11 +03:00
|
|
|
### Decimal Floating-Point Test Instructions
|
|
|
|
|
|
|
|
|
|
DTSTDC 111011 ... -- ..... ...... 011000010 - @Z22_bf_fra
|
|
|
|
|
DTSTDCQ 111111 ... -- ..... ...... 011000010 - @Z22_bf_frap
|
|
|
|
|
|
|
|
|
|
DTSTDG 111011 ... -- ..... ...... 011100010 - @Z22_bf_fra
|
|
|
|
|
DTSTDGQ 111111 ... -- ..... ...... 011100010 - @Z22_bf_frap
|
|
|
|
|
|
2021-10-29 22:24:13 +03:00
|
|
|
DTSTEX 111011 ... -- ..... ..... 0010100010 - @X_bf
|
|
|
|
|
DTSTEXQ 111111 ... -- ..... ..... 0010100010 - @X_bf_ap_bp
|
|
|
|
|
|
|
|
|
|
DTSTSF 111011 ... -- ..... ..... 1010100010 - @X_bf
|
|
|
|
|
DTSTSFQ 111111 ... -- ..... ..... 1010100010 - @X_bf_a_bp
|
|
|
|
|
|
|
|
|
|
DTSTSFI 111011 ... - ...... ..... 1010100011 - @X_bf_uim
|
|
|
|
|
DTSTSFIQ 111111 ... - ...... ..... 1010100011 - @X_bf_uim_bp
|
|
|
|
|
|
2021-10-29 22:24:14 +03:00
|
|
|
### Decimal Floating-Point Quantum Adjustment Instructions
|
|
|
|
|
|
|
|
|
|
DQUAI 111011 ..... ..... ..... .. 01000011 . @Z23_te_tb
|
|
|
|
|
DQUAIQ 111111 ..... ..... ..... .. 01000011 . @Z23_te_tbp
|
|
|
|
|
|
2021-10-29 22:24:15 +03:00
|
|
|
DQUA 111011 ..... ..... ..... .. 00000011 . @Z23_tab
|
|
|
|
|
DQUAQ 111111 ..... ..... ..... .. 00000011 . @Z23_tabp
|
|
|
|
|
|
|
|
|
|
DRRND 111011 ..... ..... ..... .. 00100011 . @Z23_tab
|
|
|
|
|
DRRNDQ 111111 ..... ..... ..... .. 00100011 . @Z23_tp_a_bp
|
|
|
|
|
|
2021-10-29 22:24:14 +03:00
|
|
|
DRINTX 111011 ..... ---- . ..... .. 01100011 . @Z23_tb
|
|
|
|
|
DRINTXQ 111111 ..... ---- . ..... .. 01100011 . @Z23_tbp
|
|
|
|
|
|
|
|
|
|
DRINTN 111011 ..... ---- . ..... .. 11100011 . @Z23_tb
|
|
|
|
|
DRINTNQ 111111 ..... ---- . ..... .. 11100011 . @Z23_tbp
|
|
|
|
|
|
2021-10-29 22:24:06 +03:00
|
|
|
### Decimal Floating-Point Conversion Instructions
|
|
|
|
|
|
2021-10-29 22:24:16 +03:00
|
|
|
DCTDP 111011 ..... ----- ..... 0100000010 . @X_tb_rc
|
|
|
|
|
DCTQPQ 111111 ..... ----- ..... 0100000010 . @X_tp_b_rc
|
|
|
|
|
|
|
|
|
|
DRSP 111011 ..... ----- ..... 1100000010 . @X_tb_rc
|
|
|
|
|
DRDPQ 111111 ..... ----- ..... 1100000010 . @X_tbp_rc
|
|
|
|
|
|
|
|
|
|
DCFFIX 111011 ..... ----- ..... 1100100010 . @X_tb_rc
|
|
|
|
|
DCFFIXQ 111111 ..... ----- ..... 1100100010 . @X_tp_b_rc
|
2021-10-29 22:24:06 +03:00
|
|
|
DCFFIXQQ 111111 ..... 00000 ..... 1111100010 - @X_frtp_vrb
|
2021-10-29 22:24:16 +03:00
|
|
|
|
|
|
|
|
DCTFIX 111011 ..... ----- ..... 0100100010 . @X_tb_rc
|
|
|
|
|
DCTFIXQ 111111 ..... ----- ..... 0100100010 . @X_t_bp_rc
|
2021-10-29 22:24:09 +03:00
|
|
|
DCTFIXQQ 111111 ..... 00001 ..... 1111100010 - @X_vrt_frbp
|
2021-10-29 22:24:06 +03:00
|
|
|
|
2021-10-29 22:24:12 +03:00
|
|
|
### Decimal Floating-Point Format Instructions
|
|
|
|
|
|
2021-10-29 22:24:17 +03:00
|
|
|
DDEDPD 111011 ..... .. --- ..... 0101000010 . @X_tb_sp_rc
|
|
|
|
|
DDEDPDQ 111111 ..... .. --- ..... 0101000010 . @X_tbp_sp_rc
|
|
|
|
|
|
|
|
|
|
DENBCD 111011 ..... . ---- ..... 1101000010 . @X_tb_s_rc
|
|
|
|
|
DENBCDQ 111111 ..... . ---- ..... 1101000010 . @X_tbp_s_rc
|
|
|
|
|
|
2021-10-29 22:24:16 +03:00
|
|
|
DXEX 111011 ..... ----- ..... 0101100010 . @X_tb_rc
|
|
|
|
|
DXEXQ 111111 ..... ----- ..... 0101100010 . @X_t_bp_rc
|
|
|
|
|
|
2021-10-29 22:24:12 +03:00
|
|
|
DIEX 111011 ..... ..... ..... 1101100010 . @X_rc
|
|
|
|
|
DIEXQ 111111 ..... ..... ..... 1101100010 . @X_tp_a_bp_rc
|
|
|
|
|
|
2021-10-29 22:24:17 +03:00
|
|
|
DSCLI 111011 ..... ..... ...... 001000010 . @Z22_ta_sh_rc
|
|
|
|
|
DSCLIQ 111111 ..... ..... ...... 001000010 . @Z22_tap_sh_rc
|
|
|
|
|
|
|
|
|
|
DSCRI 111011 ..... ..... ...... 001100010 . @Z22_ta_sh_rc
|
|
|
|
|
DSCRIQ 111111 ..... ..... ...... 001100010 . @Z22_tap_sh_rc
|
|
|
|
|
|
2022-06-06 18:00:31 +03:00
|
|
|
## Vector Exclusive-OR-based Instructions
|
|
|
|
|
|
|
|
|
|
VPMSUMD 000100 ..... ..... ..... 10011001000 @VX
|
|
|
|
|
|
target/ppc: Move VMX storage access instructions to decodetree
Moving the following instructions to decodetree specification :
{l,st}ve{b,h,w}x,
{l,st}v{x,xl},
lvs{l,r} : X-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured using the '-d in_asm,op' flag.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-04-29 08:13:15 +03:00
|
|
|
## Vector Load/Store Instructions
|
|
|
|
|
|
|
|
|
|
LVEBX 011111 ..... ..... ..... 0000000111 - @X
|
|
|
|
|
LVEHX 011111 ..... ..... ..... 0000100111 - @X
|
|
|
|
|
LVEWX 011111 ..... ..... ..... 0001000111 - @X
|
|
|
|
|
LVX 011111 ..... ..... ..... 0001100111 - @X
|
|
|
|
|
LVXL 011111 ..... ..... ..... 0101100111 - @X
|
|
|
|
|
|
|
|
|
|
STVEBX 011111 ..... ..... ..... 0010000111 - @X
|
|
|
|
|
STVEHX 011111 ..... ..... ..... 0010100111 - @X
|
|
|
|
|
STVEWX 011111 ..... ..... ..... 0011000111 - @X
|
|
|
|
|
STVX 011111 ..... ..... ..... 0011100111 - @X
|
|
|
|
|
STVXL 011111 ..... ..... ..... 0111100111 - @X
|
|
|
|
|
|
|
|
|
|
LVSL 011111 ..... ..... ..... 0000000110 - @X
|
|
|
|
|
LVSR 011111 ..... ..... ..... 0000100110 - @X
|
|
|
|
|
|
2022-03-02 08:51:37 +03:00
|
|
|
## Vector Integer Instructions
|
|
|
|
|
|
|
|
|
|
VCMPEQUB 000100 ..... ..... ..... . 0000000110 @VC
|
|
|
|
|
VCMPEQUH 000100 ..... ..... ..... . 0001000110 @VC
|
|
|
|
|
VCMPEQUW 000100 ..... ..... ..... . 0010000110 @VC
|
|
|
|
|
VCMPEQUD 000100 ..... ..... ..... . 0011000111 @VC
|
2022-03-02 08:51:37 +03:00
|
|
|
VCMPEQUQ 000100 ..... ..... ..... . 0111000111 @VC
|
2022-03-02 08:51:37 +03:00
|
|
|
|
|
|
|
|
VCMPGTSB 000100 ..... ..... ..... . 1100000110 @VC
|
|
|
|
|
VCMPGTSH 000100 ..... ..... ..... . 1101000110 @VC
|
|
|
|
|
VCMPGTSW 000100 ..... ..... ..... . 1110000110 @VC
|
|
|
|
|
VCMPGTSD 000100 ..... ..... ..... . 1111000111 @VC
|
2022-03-02 08:51:37 +03:00
|
|
|
VCMPGTSQ 000100 ..... ..... ..... . 1110000111 @VC
|
2022-03-02 08:51:37 +03:00
|
|
|
|
|
|
|
|
VCMPGTUB 000100 ..... ..... ..... . 1000000110 @VC
|
|
|
|
|
VCMPGTUH 000100 ..... ..... ..... . 1001000110 @VC
|
|
|
|
|
VCMPGTUW 000100 ..... ..... ..... . 1010000110 @VC
|
|
|
|
|
VCMPGTUD 000100 ..... ..... ..... . 1011000111 @VC
|
2022-03-02 08:51:37 +03:00
|
|
|
VCMPGTUQ 000100 ..... ..... ..... . 1010000111 @VC
|
2022-03-02 08:51:37 +03:00
|
|
|
|
|
|
|
|
VCMPNEB 000100 ..... ..... ..... . 0000000111 @VC
|
|
|
|
|
VCMPNEH 000100 ..... ..... ..... . 0001000111 @VC
|
|
|
|
|
VCMPNEW 000100 ..... ..... ..... . 0010000111 @VC
|
|
|
|
|
|
2022-03-02 08:51:37 +03:00
|
|
|
VCMPNEZB 000100 ..... ..... ..... . 0100000111 @VC
|
|
|
|
|
VCMPNEZH 000100 ..... ..... ..... . 0101000111 @VC
|
|
|
|
|
VCMPNEZW 000100 ..... ..... ..... . 0110000111 @VC
|
|
|
|
|
|
2022-03-02 08:51:37 +03:00
|
|
|
VCMPSQ 000100 ... -- ..... ..... 00101000001 @VX_bf
|
|
|
|
|
VCMPUQ 000100 ... -- ..... ..... 00100000001 @VX_bf
|
|
|
|
|
|
2024-04-29 08:13:16 +03:00
|
|
|
## Vector Integer Logical Instructions
|
|
|
|
|
|
|
|
|
|
VAND 000100 ..... ..... ..... 10000000100 @VX
|
|
|
|
|
VANDC 000100 ..... ..... ..... 10001000100 @VX
|
|
|
|
|
VNAND 000100 ..... ..... ..... 10110000100 @VX
|
|
|
|
|
VOR 000100 ..... ..... ..... 10010000100 @VX
|
|
|
|
|
VORC 000100 ..... ..... ..... 10101000100 @VX
|
|
|
|
|
VNOR 000100 ..... ..... ..... 10100000100 @VX
|
|
|
|
|
VXOR 000100 ..... ..... ..... 10011000100 @VX
|
|
|
|
|
VEQV 000100 ..... ..... ..... 11010000100 @VX
|
|
|
|
|
|
target/ppc: Move VAVG[SU][BHW] to decodetree and use gvec
Moved the instructions VAVGUB, VAVGUH, VAVGUW, VAVGSB, VAVGSH, VAVGSW,
to decodetree and use gvec with them. For these one the right shift
had to be made before the sum as to avoid an overflow, so add 1 at the
end if any of the entries had 1 in its LSB as to replicate the "+ 1"
before the shift described by the ISA.
vavgub:
rept loop master patch
8 12500 0,02616600 0,00754200 (-71.2%)
25 4000 0,02530000 0,00637700 (-74.8%)
100 1000 0,02604600 0,00790100 (-69.7%)
500 200 0,03189300 0,01838400 (-42.4%)
2500 40 0,06006900 0,06851000 (+14.1%)
8000 12 0,13941000 0,20548500 (+47.4%)
vavguh:
rept loop master patch
8 12500 0,01818200 0,00780600 (-57.1%)
25 4000 0,01789300 0,00641600 (-64.1%)
100 1000 0,01899100 0,00787200 (-58.5%)
500 200 0,02527200 0,01828400 (-27.7%)
2500 40 0,05361800 0,06773000 (+26.3%)
8000 12 0,12886600 0,20291400 (+57.5%)
vavguw:
rept loop master patch
8 12500 0,01423100 0,00776600 (-45.4%)
25 4000 0,01780800 0,00638600 (-64.1%)
100 1000 0,02085500 0,00787000 (-62.3%)
500 200 0,02737100 0,01828800 (-33.2%)
2500 40 0,05572600 0,06774200 (+21.6%)
8000 12 0,13101700 0,20311600 (+55.0%)
vavgsb:
rept loop master patch
8 12500 0,03006000 0,00788600 (-73.8%)
25 4000 0,02882200 0,00637800 (-77.9%)
100 1000 0,02958000 0,00791400 (-73.2%)
500 200 0,03548800 0,01860400 (-47.6%)
2500 40 0,06360000 0,06850800 (+7.7%)
8000 12 0,13816500 0,20550300 (+48.7%)
vavgsh:
rept loop master patch
8 12500 0,01965900 0,00776600 (-60.5%)
25 4000 0,01875400 0,00638700 (-65.9%)
100 1000 0,01952200 0,00786900 (-59.7%)
500 200 0,02562000 0,01760300 (-31.3%)
2500 40 0,05384300 0,06742800 (+25.2%)
8000 12 0,13240800 0,20330000 (+53.5%)
vavgsw:
rept loop master patch
8 12500 0,01407700 0,00775600 (-44.9%)
25 4000 0,01762300 0,00640000 (-63.7%)
100 1000 0,02046500 0,00788500 (-61.5%)
500 200 0,02745600 0,01843000 (-32.9%)
2500 40 0,05375500 0,06820500 (+26.9%)
8000 12 0,13068300 0,20304900 (+55.4%)
These results to me seems to indicate that with gvec the results have a
slower translation but faster execution.
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-7-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-19 15:50:34 +03:00
|
|
|
## Vector Integer Average Instructions
|
|
|
|
|
|
|
|
|
|
VAVGSB 000100 ..... ..... ..... 10100000010 @VX
|
|
|
|
|
VAVGSH 000100 ..... ..... ..... 10101000010 @VX
|
|
|
|
|
VAVGSW 000100 ..... ..... ..... 10110000010 @VX
|
|
|
|
|
VAVGUB 000100 ..... ..... ..... 10000000010 @VX
|
|
|
|
|
VAVGUH 000100 ..... ..... ..... 10001000010 @VX
|
|
|
|
|
VAVGUW 000100 ..... ..... ..... 10010000010 @VX
|
|
|
|
|
|
target/ppc: Move VABSDU[BHW] to decodetree and use gvec
Moved VABSDUB, VABSDUH and VABSDUW to decodetree and use gvec to
translate them.
vabsdub:
rept loop master patch
8 12500 0,03601600 0,00688500 (-80.9%)
25 4000 0,03651000 0,00532100 (-85.4%)
100 1000 0,03666900 0,00595300 (-83.8%)
500 200 0,04305800 0,01244600 (-71.1%)
2500 40 0,06893300 0,04273700 (-38.0%)
8000 12 0,14633200 0,12660300 (-13.5%)
vabsduh:
rept loop master patch
8 12500 0,02172400 0,00687500 (-68.4%)
25 4000 0,02154100 0,00531500 (-75.3%)
100 1000 0,02235400 0,00596300 (-73.3%)
500 200 0,02827500 0,01245100 (-56.0%)
2500 40 0,05638400 0,04285500 (-24.0%)
8000 12 0,13166000 0,12641400 (-4.0%)
vabsduw:
rept loop master patch
8 12500 0,01646400 0,00688300 (-58.2%)
25 4000 0,01454500 0,00475500 (-67.3%)
100 1000 0,01545800 0,00511800 (-66.9%)
500 200 0,02168200 0,01114300 (-48.6%)
2500 40 0,04571300 0,04138800 (-9.5%)
8000 12 0,12209500 0,12178500 (-0.3%)
Same as VADDCUW and VSUBCUW, overall performance gain but it uses more
TCGop (4 before the patch, 6 after).
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-8-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-19 15:50:35 +03:00
|
|
|
## Vector Integer Absolute Difference Instructions
|
|
|
|
|
|
|
|
|
|
VABSDUB 000100 ..... ..... ..... 10000000011 @VX
|
|
|
|
|
VABSDUH 000100 ..... ..... ..... 10001000011 @VX
|
|
|
|
|
VABSDUW 000100 ..... ..... ..... 10010000011 @VX
|
|
|
|
|
|
2021-06-01 22:35:26 +03:00
|
|
|
## Vector Bit Manipulation Instruction
|
|
|
|
|
|
2022-03-02 08:51:37 +03:00
|
|
|
VGNB 000100 ..... -- ... ..... 10011001100 @VX_n
|
|
|
|
|
|
2021-06-01 22:35:26 +03:00
|
|
|
VCFUGED 000100 ..... ..... ..... 10101001101 @VX
|
2021-11-04 15:36:56 +03:00
|
|
|
VCLZDM 000100 ..... ..... ..... 11110000100 @VX
|
|
|
|
|
VCTZDM 000100 ..... ..... ..... 11111000100 @VX
|
2021-11-04 15:36:57 +03:00
|
|
|
VPDEPD 000100 ..... ..... ..... 10111001101 @VX
|
|
|
|
|
VPEXTD 000100 ..... ..... ..... 10110001101 @VX
|
2021-11-04 15:36:58 +03:00
|
|
|
|
target/ppc: Move VPRTYB[WDQ] to decodetree and use gvec
Moved VPRTYBW and VPRTYBD to use gvec and both of them and VPRTYBQ to
decodetree. VPRTYBW and VPRTYBD now also use .fni4 and .fni8,
respectively.
vprtybw:
rept loop master patch
8 12500 0,01198900 0,00703100 (-41.4%)
25 4000 0,01070100 0,00571400 (-46.6%)
100 1000 0,01123300 0,00678200 (-39.6%)
500 200 0,01601500 0,01535600 (-4.1%)
2500 40 0,03872900 0,05562100 (43.6%)
8000 12 0,10047000 0,16643000 (65.7%)
vprtybd:
rept loop master patch
8 12500 0,00757700 0,00788100 (4.0%)
25 4000 0,00652500 0,00669600 (2.6%)
100 1000 0,00714400 0,00825400 (15.5%)
500 200 0,01211000 0,01903700 (57.2%)
2500 40 0,03483800 0,07021200 (101.5%)
8000 12 0,09591800 0,21036200 (119.3%)
vprtybq:
rept loop master patch
8 12500 0,00675600 0,00667200 (-1.2%)
25 4000 0,00619400 0,00643200 (3.8%)
100 1000 0,00707100 0,00751100 (6.2%)
500 200 0,01199300 0,01342000 (11.9%)
2500 40 0,03490900 0,04092900 (17.2%)
8000 12 0,09588200 0,11465100 (19.6%)
I wasn't expecting such a performance lost in both VPRTYBD and VPRTYBQ,
I'm not sure if it's worth to move those instructions. Comparing the
assembly of the helper with the TCGop they are pretty similar, so
I'm not sure why vprtybd took so much more time.
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-6-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-19 15:50:33 +03:00
|
|
|
VPRTYBD 000100 ..... 01001 ..... 11000000010 @VX_tb
|
|
|
|
|
VPRTYBQ 000100 ..... 01010 ..... 11000000010 @VX_tb
|
|
|
|
|
VPRTYBW 000100 ..... 01000 ..... 11000000010 @VX_tb
|
|
|
|
|
|
2021-11-04 15:36:58 +03:00
|
|
|
## Vector Permute and Formatting Instruction
|
|
|
|
|
|
2021-11-04 15:37:03 +03:00
|
|
|
VEXTDUBVLX 000100 ..... ..... ..... ..... 011000 @VA
|
|
|
|
|
VEXTDUBVRX 000100 ..... ..... ..... ..... 011001 @VA
|
|
|
|
|
VEXTDUHVLX 000100 ..... ..... ..... ..... 011010 @VA
|
|
|
|
|
VEXTDUHVRX 000100 ..... ..... ..... ..... 011011 @VA
|
|
|
|
|
VEXTDUWVLX 000100 ..... ..... ..... ..... 011100 @VA
|
|
|
|
|
VEXTDUWVRX 000100 ..... ..... ..... ..... 011101 @VA
|
|
|
|
|
VEXTDDVLX 000100 ..... ..... ..... ..... 011110 @VA
|
|
|
|
|
VEXTDDVRX 000100 ..... ..... ..... ..... 011111 @VA
|
|
|
|
|
|
2021-11-04 15:37:02 +03:00
|
|
|
VINSERTB 000100 ..... - .... ..... 01100001101 @VX_uim4
|
|
|
|
|
VINSERTH 000100 ..... - .... ..... 01101001101 @VX_uim4
|
|
|
|
|
VINSERTW 000100 ..... - .... ..... 01110001101 @VX_uim4
|
|
|
|
|
VINSERTD 000100 ..... - .... ..... 01111001101 @VX_uim4
|
|
|
|
|
|
2021-11-04 15:36:59 +03:00
|
|
|
VINSBLX 000100 ..... ..... ..... 01000001111 @VX
|
|
|
|
|
VINSBRX 000100 ..... ..... ..... 01100001111 @VX
|
|
|
|
|
VINSHLX 000100 ..... ..... ..... 01001001111 @VX
|
|
|
|
|
VINSHRX 000100 ..... ..... ..... 01101001111 @VX
|
|
|
|
|
VINSWLX 000100 ..... ..... ..... 01010001111 @VX
|
|
|
|
|
VINSWRX 000100 ..... ..... ..... 01110001111 @VX
|
|
|
|
|
VINSDLX 000100 ..... ..... ..... 01011001111 @VX
|
|
|
|
|
VINSDRX 000100 ..... ..... ..... 01111001111 @VX
|
|
|
|
|
|
2021-11-04 15:37:00 +03:00
|
|
|
VINSW 000100 ..... - .... ..... 00011001111 @VX_uim4
|
|
|
|
|
VINSD 000100 ..... - .... ..... 00111001111 @VX_uim4
|
|
|
|
|
|
2021-11-04 15:37:01 +03:00
|
|
|
VINSBVLX 000100 ..... ..... ..... 00000001111 @VX
|
|
|
|
|
VINSBVRX 000100 ..... ..... ..... 00100001111 @VX
|
|
|
|
|
VINSHVLX 000100 ..... ..... ..... 00001001111 @VX
|
|
|
|
|
VINSHVRX 000100 ..... ..... ..... 00101001111 @VX
|
|
|
|
|
VINSWVLX 000100 ..... ..... ..... 00010001111 @VX
|
|
|
|
|
VINSWVRX 000100 ..... ..... ..... 00110001111 @VX
|
|
|
|
|
|
2021-11-04 15:36:58 +03:00
|
|
|
VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
|
|
|
|
|
VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
|
2021-11-04 15:37:06 +03:00
|
|
|
|
2022-03-02 08:51:37 +03:00
|
|
|
VPERM 000100 ..... ..... ..... ..... 101011 @VA
|
|
|
|
|
VPERMR 000100 ..... ..... ..... ..... 111011 @VA
|
|
|
|
|
|
|
|
|
|
VSEL 000100 ..... ..... ..... ..... 101010 @VA
|
|
|
|
|
|
2022-03-02 08:51:37 +03:00
|
|
|
## Vector Integer Shift Instruction
|
|
|
|
|
|
|
|
|
|
VSLB 000100 ..... ..... ..... 00100000100 @VX
|
|
|
|
|
VSLH 000100 ..... ..... ..... 00101000100 @VX
|
|
|
|
|
VSLW 000100 ..... ..... ..... 00110000100 @VX
|
|
|
|
|
VSLD 000100 ..... ..... ..... 10111000100 @VX
|
2022-03-02 08:51:37 +03:00
|
|
|
VSLQ 000100 ..... ..... ..... 00100000101 @VX
|
2022-03-02 08:51:37 +03:00
|
|
|
|
|
|
|
|
VSRB 000100 ..... ..... ..... 01000000100 @VX
|
|
|
|
|
VSRH 000100 ..... ..... ..... 01001000100 @VX
|
|
|
|
|
VSRW 000100 ..... ..... ..... 01010000100 @VX
|
|
|
|
|
VSRD 000100 ..... ..... ..... 11011000100 @VX
|
2022-03-02 08:51:37 +03:00
|
|
|
VSRQ 000100 ..... ..... ..... 01000000101 @VX
|
2022-03-02 08:51:37 +03:00
|
|
|
|
|
|
|
|
VSRAB 000100 ..... ..... ..... 01100000100 @VX
|
|
|
|
|
VSRAH 000100 ..... ..... ..... 01101000100 @VX
|
|
|
|
|
VSRAW 000100 ..... ..... ..... 01110000100 @VX
|
|
|
|
|
VSRAD 000100 ..... ..... ..... 01111000100 @VX
|
2022-03-02 08:51:37 +03:00
|
|
|
VSRAQ 000100 ..... ..... ..... 01100000101 @VX
|
2022-03-02 08:51:37 +03:00
|
|
|
|
2022-03-02 08:51:37 +03:00
|
|
|
VRLB 000100 ..... ..... ..... 00000000100 @VX
|
|
|
|
|
VRLH 000100 ..... ..... ..... 00001000100 @VX
|
|
|
|
|
VRLW 000100 ..... ..... ..... 00010000100 @VX
|
|
|
|
|
VRLD 000100 ..... ..... ..... 00011000100 @VX
|
2022-03-02 08:51:37 +03:00
|
|
|
VRLQ 000100 ..... ..... ..... 00000000101 @VX
|
2022-03-02 08:51:37 +03:00
|
|
|
|
2022-03-02 08:51:37 +03:00
|
|
|
VRLWMI 000100 ..... ..... ..... 00010000101 @VX
|
|
|
|
|
VRLDMI 000100 ..... ..... ..... 00011000101 @VX
|
2022-03-02 08:51:37 +03:00
|
|
|
VRLQMI 000100 ..... ..... ..... 00001000101 @VX
|
2022-03-02 08:51:37 +03:00
|
|
|
|
|
|
|
|
VRLWNM 000100 ..... ..... ..... 00110000101 @VX
|
|
|
|
|
VRLDNM 000100 ..... ..... ..... 00111000101 @VX
|
2022-03-02 08:51:37 +03:00
|
|
|
VRLQNM 000100 ..... ..... ..... 00101000101 @VX
|
2022-03-02 08:51:37 +03:00
|
|
|
|
2022-03-02 08:51:37 +03:00
|
|
|
## Vector Integer Arithmetic Instructions
|
|
|
|
|
|
target/ppc: Move V(ADD|SUB)CUW to decodetree and use gvec
This patch moves VADDCUW and VSUBCUW to decodtree with gvec using an
implementation based on the helper, with the main difference being
changing the -1 (aka all bits set to 1) result returned by cmp when
true to +1. It also implemented a .fni4 version of those instructions
and dropped the helper.
vaddcuw:
rept loop master patch
8 12500 0,01008200 0,00612400 (-39.3%)
25 4000 0,01091500 0,00471600 (-56.8%)
100 1000 0,01332500 0,00593700 (-55.4%)
500 200 0,01998500 0,01275700 (-36.2%)
2500 40 0,04704300 0,04364300 (-7.2%)
8000 12 0,10748200 0,11241000 (+4.6%)
vsubcuw:
rept loop master patch
8 12500 0,01226200 0,00571600 (-53.4%)
25 4000 0,01493500 0,00462100 (-69.1%)
100 1000 0,01522700 0,00455100 (-70.1%)
500 200 0,02384600 0,01133500 (-52.5%)
2500 40 0,04935200 0,03178100 (-35.6%)
8000 12 0,09039900 0,09440600 (+4.4%)
Overall there was a gain in performance, but the TCGop code was still
slightly bigger in the new version (it went from 4 to 5).
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-4-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-19 15:50:31 +03:00
|
|
|
VADDCUW 000100 ..... ..... ..... 00110000000 @VX
|
2022-06-06 18:00:34 +03:00
|
|
|
VADDCUQ 000100 ..... ..... ..... 00101000000 @VX
|
2022-06-06 18:00:32 +03:00
|
|
|
VADDUQM 000100 ..... ..... ..... 00100000000 @VX
|
|
|
|
|
|
2024-05-23 12:44:53 +03:00
|
|
|
VADDSBS 000100 ..... ..... ..... 01100000000 @VX
|
|
|
|
|
VADDSHS 000100 ..... ..... ..... 01101000000 @VX
|
|
|
|
|
VADDSWS 000100 ..... ..... ..... 01110000000 @VX
|
|
|
|
|
|
|
|
|
|
VADDUBS 000100 ..... ..... ..... 01000000000 @VX
|
|
|
|
|
VADDUHS 000100 ..... ..... ..... 01001000000 @VX
|
|
|
|
|
VADDUWS 000100 ..... ..... ..... 01010000000 @VX
|
|
|
|
|
|
2022-06-06 18:00:33 +03:00
|
|
|
VADDEUQM 000100 ..... ..... ..... ..... 111100 @VA
|
|
|
|
|
VADDECUQ 000100 ..... ..... ..... ..... 111101 @VA
|
|
|
|
|
|
target/ppc: Move V(ADD|SUB)CUW to decodetree and use gvec
This patch moves VADDCUW and VSUBCUW to decodtree with gvec using an
implementation based on the helper, with the main difference being
changing the -1 (aka all bits set to 1) result returned by cmp when
true to +1. It also implemented a .fni4 version of those instructions
and dropped the helper.
vaddcuw:
rept loop master patch
8 12500 0,01008200 0,00612400 (-39.3%)
25 4000 0,01091500 0,00471600 (-56.8%)
100 1000 0,01332500 0,00593700 (-55.4%)
500 200 0,01998500 0,01275700 (-36.2%)
2500 40 0,04704300 0,04364300 (-7.2%)
8000 12 0,10748200 0,11241000 (+4.6%)
vsubcuw:
rept loop master patch
8 12500 0,01226200 0,00571600 (-53.4%)
25 4000 0,01493500 0,00462100 (-69.1%)
100 1000 0,01522700 0,00455100 (-70.1%)
500 200 0,02384600 0,01133500 (-52.5%)
2500 40 0,04935200 0,03178100 (-35.6%)
8000 12 0,09039900 0,09440600 (+4.4%)
Overall there was a gain in performance, but the TCGop code was still
slightly bigger in the new version (it went from 4 to 5).
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-4-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-19 15:50:31 +03:00
|
|
|
VSUBCUW 000100 ..... ..... ..... 10110000000 @VX
|
2022-06-06 18:00:37 +03:00
|
|
|
VSUBCUQ 000100 ..... ..... ..... 10101000000 @VX
|
2022-06-06 18:00:35 +03:00
|
|
|
VSUBUQM 000100 ..... ..... ..... 10100000000 @VX
|
|
|
|
|
|
2024-05-23 12:44:53 +03:00
|
|
|
VSUBSBS 000100 ..... ..... ..... 11100000000 @VX
|
|
|
|
|
VSUBSHS 000100 ..... ..... ..... 11101000000 @VX
|
|
|
|
|
VSUBSWS 000100 ..... ..... ..... 11110000000 @VX
|
|
|
|
|
|
|
|
|
|
VSUBUBS 000100 ..... ..... ..... 11000000000 @VX
|
|
|
|
|
VSUBUHS 000100 ..... ..... ..... 11001000000 @VX
|
|
|
|
|
VSUBUWS 000100 ..... ..... ..... 11010000000 @VX
|
|
|
|
|
|
2022-06-06 18:00:36 +03:00
|
|
|
VSUBECUQ 000100 ..... ..... ..... ..... 111111 @VA
|
|
|
|
|
VSUBEUQM 000100 ..... ..... ..... ..... 111110 @VA
|
|
|
|
|
|
2022-03-02 08:51:37 +03:00
|
|
|
VEXTSB2W 000100 ..... 10000 ..... 11000000010 @VX_tb
|
|
|
|
|
VEXTSH2W 000100 ..... 10001 ..... 11000000010 @VX_tb
|
|
|
|
|
VEXTSB2D 000100 ..... 11000 ..... 11000000010 @VX_tb
|
|
|
|
|
VEXTSH2D 000100 ..... 11001 ..... 11000000010 @VX_tb
|
|
|
|
|
VEXTSW2D 000100 ..... 11010 ..... 11000000010 @VX_tb
|
2022-03-02 08:51:37 +03:00
|
|
|
VEXTSD2Q 000100 ..... 11011 ..... 11000000010 @VX_tb
|
2022-03-02 08:51:37 +03:00
|
|
|
|
target/ppc: Move VNEG[WD] to decodtree and use gvec
Moved the instructions VNEGW and VNEGD to decodetree and used gvec to
decode it.
vnegw:
rept loop master patch
8 12500 0,01053200 0,00548400 (-47.9%)
25 4000 0,01030500 0,00390000 (-62.2%)
100 1000 0,01096300 0,00395400 (-63.9%)
500 200 0,01472000 0,00712300 (-51.6%)
2500 40 0,03809000 0,02147700 (-43.6%)
8000 12 0,09957100 0,06202100 (-37.7%)
vnegd:
rept loop master patch
8 12500 0,00594600 0,00543800 (-8.5%)
25 4000 0,00575200 0,00396400 (-31.1%)
100 1000 0,00676100 0,00394800 (-41.6%)
500 200 0,01149300 0,00709400 (-38.3%)
2500 40 0,03441500 0,02169600 (-37.0%)
8000 12 0,09516900 0,06337000 (-33.4%)
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-5-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-19 15:50:32 +03:00
|
|
|
VNEGD 000100 ..... 00111 ..... 11000000010 @VX_tb
|
|
|
|
|
VNEGW 000100 ..... 00110 ..... 11000000010 @VX_tb
|
|
|
|
|
|
2024-04-29 08:13:17 +03:00
|
|
|
## Vector Integer Maximum/Minimum Instructions
|
|
|
|
|
|
|
|
|
|
VMAXUB 000100 ..... ..... ..... 00000000010 @VX
|
|
|
|
|
VMAXUH 000100 ..... ..... ..... 00001000010 @VX
|
|
|
|
|
VMAXUW 000100 ..... ..... ..... 00010000010 @VX
|
|
|
|
|
VMAXUD 000100 ..... ..... ..... 00011000010 @VX
|
|
|
|
|
|
|
|
|
|
VMAXSB 000100 ..... ..... ..... 00100000010 @VX
|
|
|
|
|
VMAXSH 000100 ..... ..... ..... 00101000010 @VX
|
|
|
|
|
VMAXSW 000100 ..... ..... ..... 00110000010 @VX
|
|
|
|
|
VMAXSD 000100 ..... ..... ..... 00111000010 @VX
|
|
|
|
|
|
|
|
|
|
VMINUB 000100 ..... ..... ..... 01000000010 @VX
|
|
|
|
|
VMINUH 000100 ..... ..... ..... 01001000010 @VX
|
|
|
|
|
VMINUW 000100 ..... ..... ..... 01010000010 @VX
|
|
|
|
|
VMINUD 000100 ..... ..... ..... 01011000010 @VX
|
|
|
|
|
|
|
|
|
|
VMINSB 000100 ..... ..... ..... 01100000010 @VX
|
|
|
|
|
VMINSH 000100 ..... ..... ..... 01101000010 @VX
|
|
|
|
|
VMINSW 000100 ..... ..... ..... 01110000010 @VX
|
|
|
|
|
VMINSD 000100 ..... ..... ..... 01111000010 @VX
|
|
|
|
|
|
2021-12-17 19:57:13 +03:00
|
|
|
## Vector Mask Manipulation Instructions
|
|
|
|
|
|
2021-12-17 19:57:13 +03:00
|
|
|
MTVSRBM 000100 ..... 10000 ..... 11001000010 @VX_tb
|
|
|
|
|
MTVSRHM 000100 ..... 10001 ..... 11001000010 @VX_tb
|
|
|
|
|
MTVSRWM 000100 ..... 10010 ..... 11001000010 @VX_tb
|
|
|
|
|
MTVSRDM 000100 ..... 10011 ..... 11001000010 @VX_tb
|
|
|
|
|
MTVSRQM 000100 ..... 10100 ..... 11001000010 @VX_tb
|
|
|
|
|
MTVSRBMI 000100 ..... ..... .......... 01010 . @DX_b
|
|
|
|
|
|
2021-12-17 19:57:13 +03:00
|
|
|
VEXPANDBM 000100 ..... 00000 ..... 11001000010 @VX_tb
|
|
|
|
|
VEXPANDHM 000100 ..... 00001 ..... 11001000010 @VX_tb
|
|
|
|
|
VEXPANDWM 000100 ..... 00010 ..... 11001000010 @VX_tb
|
|
|
|
|
VEXPANDDM 000100 ..... 00011 ..... 11001000010 @VX_tb
|
|
|
|
|
VEXPANDQM 000100 ..... 00100 ..... 11001000010 @VX_tb
|
|
|
|
|
|
2021-12-17 19:57:13 +03:00
|
|
|
VEXTRACTBM 000100 ..... 01000 ..... 11001000010 @VX_tb
|
|
|
|
|
VEXTRACTHM 000100 ..... 01001 ..... 11001000010 @VX_tb
|
|
|
|
|
VEXTRACTWM 000100 ..... 01010 ..... 11001000010 @VX_tb
|
|
|
|
|
VEXTRACTDM 000100 ..... 01011 ..... 11001000010 @VX_tb
|
|
|
|
|
VEXTRACTQM 000100 ..... 01100 ..... 11001000010 @VX_tb
|
|
|
|
|
|
2022-03-02 08:51:37 +03:00
|
|
|
VCNTMBB 000100 ..... 1100 . ..... 11001000010 @VX_mp
|
|
|
|
|
VCNTMBH 000100 ..... 1101 . ..... 11001000010 @VX_mp
|
|
|
|
|
VCNTMBW 000100 ..... 1110 . ..... 11001000010 @VX_mp
|
|
|
|
|
VCNTMBD 000100 ..... 1111 . ..... 11001000010 @VX_mp
|
|
|
|
|
|
target/ppc: moved vector even and odd multiplication to decodetree
Moved the instructions vmulesb, vmulosb, vmuleub, vmuloub,
vmulesh, vmulosh, vmuleuh, vmulouh, vmulesw, vmulosw,
muleuw and vmulouw from legacy to decodetree. Implemented
the instructions vmulesd, vmulosd, vmuleud, vmuloud.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-3-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02 08:51:36 +03:00
|
|
|
## Vector Multiply Instruction
|
|
|
|
|
|
|
|
|
|
VMULESB 000100 ..... ..... ..... 01100001000 @VX
|
|
|
|
|
VMULOSB 000100 ..... ..... ..... 00100001000 @VX
|
|
|
|
|
VMULEUB 000100 ..... ..... ..... 01000001000 @VX
|
|
|
|
|
VMULOUB 000100 ..... ..... ..... 00000001000 @VX
|
|
|
|
|
|
|
|
|
|
VMULESH 000100 ..... ..... ..... 01101001000 @VX
|
|
|
|
|
VMULOSH 000100 ..... ..... ..... 00101001000 @VX
|
|
|
|
|
VMULEUH 000100 ..... ..... ..... 01001001000 @VX
|
|
|
|
|
VMULOUH 000100 ..... ..... ..... 00001001000 @VX
|
|
|
|
|
|
|
|
|
|
VMULESW 000100 ..... ..... ..... 01110001000 @VX
|
|
|
|
|
VMULOSW 000100 ..... ..... ..... 00110001000 @VX
|
|
|
|
|
VMULEUW 000100 ..... ..... ..... 01010001000 @VX
|
|
|
|
|
VMULOUW 000100 ..... ..... ..... 00010001000 @VX
|
|
|
|
|
|
|
|
|
|
VMULESD 000100 ..... ..... ..... 01111001000 @VX
|
|
|
|
|
VMULOSD 000100 ..... ..... ..... 00111001000 @VX
|
|
|
|
|
VMULEUD 000100 ..... ..... ..... 01011001000 @VX
|
|
|
|
|
VMULOUD 000100 ..... ..... ..... 00011001000 @VX
|
|
|
|
|
|
2022-03-02 08:51:36 +03:00
|
|
|
VMULHSW 000100 ..... ..... ..... 01110001001 @VX
|
|
|
|
|
VMULHUW 000100 ..... ..... ..... 01010001001 @VX
|
|
|
|
|
VMULHSD 000100 ..... ..... ..... 01111001001 @VX
|
|
|
|
|
VMULHUD 000100 ..... ..... ..... 01011001001 @VX
|
|
|
|
|
VMULLD 000100 ..... ..... ..... 00111001001 @VX
|
|
|
|
|
|
2022-03-02 08:51:37 +03:00
|
|
|
## Vector Multiply-Sum Instructions
|
|
|
|
|
|
2022-05-17 15:39:27 +03:00
|
|
|
VMSUMUBM 000100 ..... ..... ..... ..... 100100 @VA
|
|
|
|
|
VMSUMMBM 000100 ..... ..... ..... ..... 100101 @VA
|
2022-05-17 15:39:29 +03:00
|
|
|
VMSUMSHM 000100 ..... ..... ..... ..... 101000 @VA
|
|
|
|
|
VMSUMSHS 000100 ..... ..... ..... ..... 101001 @VA
|
2022-05-17 15:39:28 +03:00
|
|
|
VMSUMUHM 000100 ..... ..... ..... ..... 100110 @VA
|
|
|
|
|
VMSUMUHS 000100 ..... ..... ..... ..... 100111 @VA
|
2022-05-17 15:39:27 +03:00
|
|
|
|
2022-03-02 08:51:37 +03:00
|
|
|
VMSUMCUD 000100 ..... ..... ..... ..... 010111 @VA
|
2022-03-02 08:51:37 +03:00
|
|
|
VMSUMUDM 000100 ..... ..... ..... ..... 100011 @VA
|
2022-03-02 08:51:37 +03:00
|
|
|
|
target/ppc: Moved VMLADDUHM to decodetree and use gvec
This patch moves VMLADDUHM to decodetree a creates a gvec implementation
using mul_vec and add_vec.
rept loop master patch
8 12500 0,01810500 0,00903100 (-50.1%)
25 4000 0,01739400 0,00747700 (-57.0%)
100 1000 0,01843600 0,00901400 (-51.1%)
500 200 0,02574600 0,01971000 (-23.4%)
2500 40 0,05921600 0,07121800 (+20.3%)
8000 12 0,15326700 0,21725200 (+41.7%)
The significant difference in performance when REPT is low and LOOP is
high I think is due to the fact that the new implementation has a higher
translation time, as when using a helper only 5 TCGop are used but with
the patch a total of 10 TCGop are needed (Power lacks a direct mul_vec
equivalent so this instruction is implemented with the help of 5 others,
vmuleu, vmulou, vmrgh, vmrgl and vpkum).
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-2-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-19 15:50:29 +03:00
|
|
|
VMLADDUHM 000100 ..... ..... ..... ..... 100010 @VA
|
target/ppc: Move VMH[R]ADDSHS instruction to decodetree
This patch moves VMHADDSHS and VMHRADDSHS to decodetree I couldn't find
a satisfactory implementation with TCG inline.
vmhaddshs:
rept loop master patch
8 12500 0,02983400 0,02648500 (-11.2%)
25 4000 0,02946000 0,02518000 (-14.5%)
100 1000 0,03104300 0,02638000 (-15.0%)
500 200 0,04002000 0,03502500 (-12.5%)
2500 40 0,08090100 0,07562200 (-6.5%)
8000 12 0,19242600 0,18626800 (-3.2%)
vmhraddshs:
rept loop master patch
8 12500 0,03078600 0,02851000 (-7.4%)
25 4000 0,02793200 0,02746900 (-1.7%)
100 1000 0,02886000 0,02839900 (-1.6%)
500 200 0,03714700 0,03799200 (+2.3%)
2500 40 0,07948000 0,07852200 (-1.2%)
8000 12 0,19049800 0,18813900 (-1.2%)
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-3-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-19 15:50:30 +03:00
|
|
|
VMHADDSHS 000100 ..... ..... ..... ..... 100000 @VA
|
|
|
|
|
VMHRADDSHS 000100 ..... ..... ..... ..... 100001 @VA
|
target/ppc: Moved VMLADDUHM to decodetree and use gvec
This patch moves VMLADDUHM to decodetree a creates a gvec implementation
using mul_vec and add_vec.
rept loop master patch
8 12500 0,01810500 0,00903100 (-50.1%)
25 4000 0,01739400 0,00747700 (-57.0%)
100 1000 0,01843600 0,00901400 (-51.1%)
500 200 0,02574600 0,01971000 (-23.4%)
2500 40 0,05921600 0,07121800 (+20.3%)
8000 12 0,15326700 0,21725200 (+41.7%)
The significant difference in performance when REPT is low and LOOP is
high I think is due to the fact that the new implementation has a higher
translation time, as when using a helper only 5 TCGop are used but with
the patch a total of 10 TCGop are needed (Power lacks a direct mul_vec
equivalent so this instruction is implemented with the help of 5 others,
vmuleu, vmulou, vmrgh, vmrgl and vpkum).
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-2-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-19 15:50:29 +03:00
|
|
|
|
2022-03-02 08:51:37 +03:00
|
|
|
## Vector String Instructions
|
|
|
|
|
|
|
|
|
|
VSTRIBL 000100 ..... 00000 ..... . 0000001101 @VX_tb_rc
|
|
|
|
|
VSTRIBR 000100 ..... 00001 ..... . 0000001101 @VX_tb_rc
|
|
|
|
|
VSTRIHL 000100 ..... 00010 ..... . 0000001101 @VX_tb_rc
|
|
|
|
|
VSTRIHR 000100 ..... 00011 ..... . 0000001101 @VX_tb_rc
|
|
|
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|
2022-03-02 08:51:37 +03:00
|
|
|
VCLRLB 000100 ..... ..... ..... 00110001101 @VX
|
2022-03-02 08:51:37 +03:00
|
|
|
VCLRRB 000100 ..... ..... ..... 00111001101 @VX
|
2022-03-02 08:51:37 +03:00
|
|
|
|
2021-11-04 15:37:06 +03:00
|
|
|
# VSX Load/Store Instructions
|
|
|
|
|
|
2022-03-02 08:51:38 +03:00
|
|
|
LXSD 111001 ..... ..... .............. 10 @DS
|
|
|
|
|
STXSD 111101 ..... ..... .............. 10 @DS
|
2022-03-02 08:51:38 +03:00
|
|
|
LXSSP 111001 ..... ..... .............. 11 @DS
|
|
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|
STXSSP 111101 ..... ..... .............. 11 @DS
|
2021-11-04 15:37:06 +03:00
|
|
|
LXV 111101 ..... ..... ............ . 001 @DQ_TSX
|
|
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|
STXV 111101 ..... ..... ............ . 101 @DQ_TSX
|
2021-11-04 15:37:08 +03:00
|
|
|
LXVP 000110 ..... ..... ............ 0000 @DQ_TSXP
|
|
|
|
|
STXVP 000110 ..... ..... ............ 0001 @DQ_TSXP
|
2021-11-04 15:37:07 +03:00
|
|
|
LXVX 011111 ..... ..... ..... 0100 - 01100 . @X_TSX
|
|
|
|
|
STXVX 011111 ..... ..... ..... 0110001100 . @X_TSX
|
2021-11-04 15:37:09 +03:00
|
|
|
LXVPX 011111 ..... ..... ..... 0101001101 - @X_TSXP
|
|
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|
|
STXVPX 011111 ..... ..... ..... 0111001101 - @X_TSXP
|
2022-03-02 08:51:38 +03:00
|
|
|
LXVRBX 011111 ..... ..... ..... 0000001101 . @X_TSX
|
|
|
|
|
LXVRHX 011111 ..... ..... ..... 0000101101 . @X_TSX
|
|
|
|
|
LXVRWX 011111 ..... ..... ..... 0001001101 . @X_TSX
|
|
|
|
|
LXVRDX 011111 ..... ..... ..... 0001101101 . @X_TSX
|
|
|
|
|
STXVRBX 011111 ..... ..... ..... 0010001101 . @X_TSX
|
|
|
|
|
STXVRHX 011111 ..... ..... ..... 0010101101 . @X_TSX
|
|
|
|
|
STXVRWX 011111 ..... ..... ..... 0011001101 . @X_TSX
|
|
|
|
|
STXVRDX 011111 ..... ..... ..... 0011101101 . @X_TSX
|
2021-11-04 15:37:12 +03:00
|
|
|
|
target/ppc: Moving VSX scalar storage access insns to decodetree.
Moving the following instructions to decodetree specification :
lxs{d, iwa, ibz, ihz, iwz, sp}x : X-form
stxs{d, ib, ih, iw, sp}x : X-form
The changes were verified by validating that the tcg-ops generated by those
instructions remain the same, which were captured using the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-06-18 11:58:28 +03:00
|
|
|
LXSDX 011111 ..... ..... ..... 1001001100 . @X_TSX
|
|
|
|
|
LXSIWAX 011111 ..... ..... ..... 0001001100 . @X_TSX
|
|
|
|
|
LXSIBZX 011111 ..... ..... ..... 1100001101 . @X_TSX
|
|
|
|
|
LXSIHZX 011111 ..... ..... ..... 1100101101 . @X_TSX
|
|
|
|
|
LXSIWZX 011111 ..... ..... ..... 0000001100 . @X_TSX
|
|
|
|
|
LXSSPX 011111 ..... ..... ..... 1000001100 . @X_TSX
|
|
|
|
|
|
|
|
|
|
STXSDX 011111 ..... ..... ..... 1011001100 . @X_TSX
|
|
|
|
|
STXSIBX 011111 ..... ..... ..... 1110001101 . @X_TSX
|
|
|
|
|
STXSIHX 011111 ..... ..... ..... 1110101101 . @X_TSX
|
|
|
|
|
STXSIWX 011111 ..... ..... ..... 0010001100 . @X_TSX
|
|
|
|
|
STXSSPX 011111 ..... ..... ..... 1010001100 . @X_TSX
|
|
|
|
|
|
target/ppc: Move VSX vector storage access insns to decodetree.
Moving the following instructions to decodetree specification:
lxv{b16, d2, h8, w4, ds, ws}x : X-form
stxv{b16, d2, h8, w4}x : X-form
The changes were verified by validating that the tcg-ops generated for those
instructions remain the same, which were captured using the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-06-18 11:58:30 +03:00
|
|
|
LXVB16X 011111 ..... ..... ..... 1101101100 . @X_TSX
|
|
|
|
|
LXVD2X 011111 ..... ..... ..... 1101001100 . @X_TSX
|
|
|
|
|
LXVH8X 011111 ..... ..... ..... 1100101100 . @X_TSX
|
|
|
|
|
LXVW4X 011111 ..... ..... ..... 1100001100 . @X_TSX
|
|
|
|
|
LXVDSX 011111 ..... ..... ..... 0101001100 . @X_TSX
|
|
|
|
|
LXVWSX 011111 ..... ..... ..... 0101101100 . @X_TSX
|
2024-06-18 11:58:29 +03:00
|
|
|
LXVL 011111 ..... ..... ..... 0100001101 . @X_TSX
|
|
|
|
|
LXVLL 011111 ..... ..... ..... 0100101101 . @X_TSX
|
|
|
|
|
|
target/ppc: Move VSX vector storage access insns to decodetree.
Moving the following instructions to decodetree specification:
lxv{b16, d2, h8, w4, ds, ws}x : X-form
stxv{b16, d2, h8, w4}x : X-form
The changes were verified by validating that the tcg-ops generated for those
instructions remain the same, which were captured using the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-06-18 11:58:30 +03:00
|
|
|
STXVB16X 011111 ..... ..... ..... 1111101100 . @X_TSX
|
|
|
|
|
STXVD2X 011111 ..... ..... ..... 1111001100 . @X_TSX
|
|
|
|
|
STXVH8X 011111 ..... ..... ..... 1110101100 . @X_TSX
|
|
|
|
|
STXVW4X 011111 ..... ..... ..... 1110001100 . @X_TSX
|
2024-06-18 11:58:29 +03:00
|
|
|
STXVL 011111 ..... ..... ..... 0110001101 . @X_TSX
|
|
|
|
|
STXVLL 011111 ..... ..... ..... 0110101101 . @X_TSX
|
|
|
|
|
|
target/ppc: Use gvec to decode XV[N]ABS[DS]P/XVNEG[DS]P
Moved XVABSSP, XVABSDP, XVNABSSP,XVNABSDP, XVNEGSP and XVNEGDP to
decodetree and used gvec to translate them.
xvabssp:
rept loop master patch
8 12500 0,00477900 0,00476000 (-0.4%)
25 4000 0,00442800 0,00353300 (-20.2%)
100 1000 0,00478700 0,00366100 (-23.5%)
500 200 0,00973200 0,00649400 (-33.3%)
2500 40 0,03165200 0,02226700 (-29.7%)
8000 12 0,09315900 0,06674900 (-28.3%)
xvabsdp:
rept loop master patch
8 12500 0,00475000 0,00474400 (-0.1%)
25 4000 0,00355600 0,00367500 (+3.3%)
100 1000 0,00444200 0,00366000 (-17.6%)
500 200 0,00942700 0,00732400 (-22.3%)
2500 40 0,02990000 0,02308500 (-22.8%)
8000 12 0,08770300 0,06683800 (-23.8%)
xvnabssp:
rept loop master patch
8 12500 0,00494500 0,00492900 (-0.3%)
25 4000 0,00397700 0,00338600 (-14.9%)
100 1000 0,00421400 0,00353500 (-16.1%)
500 200 0,01048000 0,00707100 (-32.5%)
2500 40 0,03251500 0,02238300 (-31.2%)
8000 12 0,08889100 0,06469800 (-27.2%)
xvnabsdp:
rept loop master patch
8 12500 0,00511000 0,00492700 (-3.6%)
25 4000 0,00398800 0,00381500 (-4.3%)
100 1000 0,00390500 0,00365900 (-6.3%)
500 200 0,00924800 0,00784600 (-15.2%)
2500 40 0,03138900 0,02391600 (-23.8%)
8000 12 0,09654200 0,05684600 (-41.1%)
xvnegsp:
rept loop master patch
8 12500 0,00493900 0,00452800 (-8.3%)
25 4000 0,00369100 0,00366800 (-0.6%)
100 1000 0,00371100 0,00380000 (+2.4%)
500 200 0,00991100 0,00652300 (-34.2%)
2500 40 0,03025800 0,02422300 (-19.9%)
8000 12 0,09251100 0,06457600 (-30.2%)
xvnegdp:
rept loop master patch
8 12500 0,00474900 0,00454400 (-4.3%)
25 4000 0,00353100 0,00325600 (-7.8%)
100 1000 0,00398600 0,00366800 (-8.0%)
500 200 0,01032300 0,00702400 (-32.0%)
2500 40 0,03125000 0,02422400 (-22.5%)
8000 12 0,09475100 0,06173000 (-34.9%)
This one to me seemed the opposite of the previous instructions, as it
looks like there was an improvement in the translation time (itself not
a surprise as operations were done twice before so there was the need to
translate twice as many TCGop)
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-9-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-19 15:50:36 +03:00
|
|
|
## VSX Vector Binary Floating-Point Sign Manipulation Instructions
|
|
|
|
|
|
|
|
|
|
XVABSDP 111100 ..... 00000 ..... 111011001 .. @XX2
|
|
|
|
|
XVABSSP 111100 ..... 00000 ..... 110011001 .. @XX2
|
|
|
|
|
XVNABSDP 111100 ..... 00000 ..... 111101001 .. @XX2
|
|
|
|
|
XVNABSSP 111100 ..... 00000 ..... 110101001 .. @XX2
|
|
|
|
|
XVNEGDP 111100 ..... 00000 ..... 111111001 .. @XX2
|
|
|
|
|
XVNEGSP 111100 ..... 00000 ..... 110111001 .. @XX2
|
target/ppc: Use gvec to decode XVCPSGN[SD]P
Moved XVCPSGNSP and XVCPSGNDP to decodetree and used gvec to translate
them.
xvcpsgnsp:
rept loop master patch
8 12500 0,00561400 0,00537900 (-4.2%)
25 4000 0,00562100 0,00400000 (-28.8%)
100 1000 0,00696900 0,00416300 (-40.3%)
500 200 0,02211900 0,00840700 (-62.0%)
2500 40 0,09328600 0,02728300 (-70.8%)
8000 12 0,27295300 0,06867800 (-74.8%)
xvcpsgndp:
rept loop master patch
8 12500 0,00556300 0,00584200 (+5.0%)
25 4000 0,00482700 0,00431700 (-10.6%)
100 1000 0,00585800 0,00464400 (-20.7%)
500 200 0,01565300 0,00839700 (-46.4%)
2500 40 0,05766500 0,02430600 (-57.8%)
8000 12 0,19875300 0,07947100 (-60.0%)
Like the previous instructions there seemed to be a improvement on
translation time.
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-10-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-19 15:50:37 +03:00
|
|
|
XVCPSGNDP 111100 ..... ..... ..... 11110000 ... @XX3
|
|
|
|
|
XVCPSGNSP 111100 ..... ..... ..... 11010000 ... @XX3
|
target/ppc: Use gvec to decode XV[N]ABS[DS]P/XVNEG[DS]P
Moved XVABSSP, XVABSDP, XVNABSSP,XVNABSDP, XVNEGSP and XVNEGDP to
decodetree and used gvec to translate them.
xvabssp:
rept loop master patch
8 12500 0,00477900 0,00476000 (-0.4%)
25 4000 0,00442800 0,00353300 (-20.2%)
100 1000 0,00478700 0,00366100 (-23.5%)
500 200 0,00973200 0,00649400 (-33.3%)
2500 40 0,03165200 0,02226700 (-29.7%)
8000 12 0,09315900 0,06674900 (-28.3%)
xvabsdp:
rept loop master patch
8 12500 0,00475000 0,00474400 (-0.1%)
25 4000 0,00355600 0,00367500 (+3.3%)
100 1000 0,00444200 0,00366000 (-17.6%)
500 200 0,00942700 0,00732400 (-22.3%)
2500 40 0,02990000 0,02308500 (-22.8%)
8000 12 0,08770300 0,06683800 (-23.8%)
xvnabssp:
rept loop master patch
8 12500 0,00494500 0,00492900 (-0.3%)
25 4000 0,00397700 0,00338600 (-14.9%)
100 1000 0,00421400 0,00353500 (-16.1%)
500 200 0,01048000 0,00707100 (-32.5%)
2500 40 0,03251500 0,02238300 (-31.2%)
8000 12 0,08889100 0,06469800 (-27.2%)
xvnabsdp:
rept loop master patch
8 12500 0,00511000 0,00492700 (-3.6%)
25 4000 0,00398800 0,00381500 (-4.3%)
100 1000 0,00390500 0,00365900 (-6.3%)
500 200 0,00924800 0,00784600 (-15.2%)
2500 40 0,03138900 0,02391600 (-23.8%)
8000 12 0,09654200 0,05684600 (-41.1%)
xvnegsp:
rept loop master patch
8 12500 0,00493900 0,00452800 (-8.3%)
25 4000 0,00369100 0,00366800 (-0.6%)
100 1000 0,00371100 0,00380000 (+2.4%)
500 200 0,00991100 0,00652300 (-34.2%)
2500 40 0,03025800 0,02422300 (-19.9%)
8000 12 0,09251100 0,06457600 (-30.2%)
xvnegdp:
rept loop master patch
8 12500 0,00474900 0,00454400 (-4.3%)
25 4000 0,00353100 0,00325600 (-7.8%)
100 1000 0,00398600 0,00366800 (-8.0%)
500 200 0,01032300 0,00702400 (-32.0%)
2500 40 0,03125000 0,02422400 (-22.5%)
8000 12 0,09475100 0,06173000 (-34.9%)
This one to me seemed the opposite of the previous instructions, as it
looks like there was an improvement in the translation time (itself not
a surprise as operations were done twice before so there was the need to
translate twice as many TCGop)
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-9-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-19 15:50:36 +03:00
|
|
|
|
target/ppc: Move VSX arithmetic and max/min insns to decodetree.
Moving the following instructions to decodetree specification:
x{s, v}{add, sub, mul, div}{s, d}p : XX3-form
xs{max, min}dp, xv{max, min}{s, d}p : XX3-form
The changes were verfied by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-05-23 12:48:20 +03:00
|
|
|
## VSX Binary Floating-Point Arithmetic Instructions
|
|
|
|
|
|
|
|
|
|
XSADDSP 111100 ..... ..... ..... 00000000 ... @XX3
|
|
|
|
|
XSSUBSP 111100 ..... ..... ..... 00001000 ... @XX3
|
|
|
|
|
XSMULSP 111100 ..... ..... ..... 00010000 ... @XX3
|
|
|
|
|
XSDIVSP 111100 ..... ..... ..... 00011000 ... @XX3
|
|
|
|
|
|
|
|
|
|
XSADDDP 111100 ..... ..... ..... 00100000 ... @XX3
|
|
|
|
|
XSSUBDP 111100 ..... ..... ..... 00101000 ... @XX3
|
|
|
|
|
XSMULDP 111100 ..... ..... ..... 00110000 ... @XX3
|
|
|
|
|
XSDIVDP 111100 ..... ..... ..... 00111000 ... @XX3
|
|
|
|
|
|
|
|
|
|
XVADDSP 111100 ..... ..... ..... 01000000 ... @XX3
|
|
|
|
|
XVSUBSP 111100 ..... ..... ..... 01001000 ... @XX3
|
|
|
|
|
XVMULSP 111100 ..... ..... ..... 01010000 ... @XX3
|
|
|
|
|
XVDIVSP 111100 ..... ..... ..... 01011000 ... @XX3
|
|
|
|
|
|
|
|
|
|
XVADDDP 111100 ..... ..... ..... 01100000 ... @XX3
|
|
|
|
|
XVSUBDP 111100 ..... ..... ..... 01101000 ... @XX3
|
|
|
|
|
XVMULDP 111100 ..... ..... ..... 01110000 ... @XX3
|
|
|
|
|
XVDIVDP 111100 ..... ..... ..... 01111000 ... @XX3
|
|
|
|
|
|
2022-03-02 08:51:38 +03:00
|
|
|
## VSX Scalar Multiply-Add Instructions
|
|
|
|
|
|
|
|
|
|
XSMADDADP 111100 ..... ..... ..... 00100001 . . . @XX3
|
|
|
|
|
XSMADDMDP 111100 ..... ..... ..... 00101001 . . . @XX3
|
|
|
|
|
XSMADDASP 111100 ..... ..... ..... 00000001 . . . @XX3
|
|
|
|
|
XSMADDMSP 111100 ..... ..... ..... 00001001 . . . @XX3
|
2022-03-02 08:51:38 +03:00
|
|
|
XSMADDQP 111111 ..... ..... ..... 0110000100 . @X_rc
|
2022-03-02 08:51:38 +03:00
|
|
|
|
|
|
|
|
XSMSUBADP 111100 ..... ..... ..... 00110001 . . . @XX3
|
|
|
|
|
XSMSUBMDP 111100 ..... ..... ..... 00111001 . . . @XX3
|
|
|
|
|
XSMSUBASP 111100 ..... ..... ..... 00010001 . . . @XX3
|
|
|
|
|
XSMSUBMSP 111100 ..... ..... ..... 00011001 . . . @XX3
|
2022-03-02 08:51:38 +03:00
|
|
|
XSMSUBQP 111111 ..... ..... ..... 0110100100 . @X_rc
|
2022-03-02 08:51:38 +03:00
|
|
|
|
|
|
|
|
XSNMADDASP 111100 ..... ..... ..... 10000001 . . . @XX3
|
|
|
|
|
XSNMADDMSP 111100 ..... ..... ..... 10001001 . . . @XX3
|
|
|
|
|
XSNMADDADP 111100 ..... ..... ..... 10100001 . . . @XX3
|
|
|
|
|
XSNMADDMDP 111100 ..... ..... ..... 10101001 . . . @XX3
|
2022-03-02 08:51:38 +03:00
|
|
|
XSNMADDQP 111111 ..... ..... ..... 0111000100 . @X_rc
|
2022-03-02 08:51:38 +03:00
|
|
|
|
|
|
|
|
XSNMSUBASP 111100 ..... ..... ..... 10010001 . . . @XX3
|
|
|
|
|
XSNMSUBMSP 111100 ..... ..... ..... 10011001 . . . @XX3
|
|
|
|
|
XSNMSUBADP 111100 ..... ..... ..... 10110001 . . . @XX3
|
|
|
|
|
XSNMSUBMDP 111100 ..... ..... ..... 10111001 . . . @XX3
|
2022-03-02 08:51:38 +03:00
|
|
|
XSNMSUBQP 111111 ..... ..... ..... 0111100100 . @X_rc
|
2022-03-02 08:51:38 +03:00
|
|
|
|
2021-11-04 15:37:12 +03:00
|
|
|
## VSX splat instruction
|
|
|
|
|
|
2021-11-04 15:37:13 +03:00
|
|
|
XXSPLTIB 111100 ..... 00 ........ 0101101000 . @X_imm8
|
2022-03-02 08:51:38 +03:00
|
|
|
XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2_uim2
|
2021-11-04 15:37:18 +03:00
|
|
|
|
2022-03-02 08:51:38 +03:00
|
|
|
## VSX Permute Instructions
|
|
|
|
|
|
2022-05-17 15:39:25 +03:00
|
|
|
XXEXTRACTUW 111100 ..... - .... ..... 010100101 .. @XX2_uim4
|
|
|
|
|
XXINSERTW 111100 ..... - .... ..... 010110101 .. @XX2_uim4
|
|
|
|
|
|
2022-03-02 08:51:38 +03:00
|
|
|
XXPERM 111100 ..... ..... ..... 00011010 ... @XX3
|
|
|
|
|
XXPERMR 111100 ..... ..... ..... 00111010 ... @XX3
|
2022-03-02 08:51:38 +03:00
|
|
|
XXPERMDI 111100 ..... ..... ..... 0 .. 01010 ... @XX3_dm
|
2022-03-02 08:51:38 +03:00
|
|
|
|
2022-03-02 08:51:37 +03:00
|
|
|
XXSEL 111100 ..... ..... ..... ..... 11 .... @XX4
|
|
|
|
|
|
2022-03-02 08:51:38 +03:00
|
|
|
## VSX Vector Generate PCV
|
|
|
|
|
|
|
|
|
|
XXGENPCVBM 111100 ..... ..... ..... 1110010100 . @X_imm5
|
|
|
|
|
XXGENPCVHM 111100 ..... ..... ..... 1110010101 . @X_imm5
|
|
|
|
|
XXGENPCVWM 111100 ..... ..... ..... 1110110100 . @X_imm5
|
|
|
|
|
XXGENPCVDM 111100 ..... ..... ..... 1110110101 . @X_imm5
|
|
|
|
|
|
2021-11-04 15:37:18 +03:00
|
|
|
## VSX Vector Load Special Value Instruction
|
|
|
|
|
|
|
|
|
|
LXVKQ 111100 ..... 11111 ..... 0101101000 . @X_uim5
|
2021-12-17 19:57:18 +03:00
|
|
|
|
|
|
|
|
## VSX Comparison Instructions
|
|
|
|
|
|
|
|
|
|
XSMAXCDP 111100 ..... ..... ..... 10000000 ... @XX3
|
|
|
|
|
XSMINCDP 111100 ..... ..... ..... 10001000 ... @XX3
|
|
|
|
|
XSMAXJDP 111100 ..... ..... ..... 10010000 ... @XX3
|
|
|
|
|
XSMINJDP 111100 ..... ..... ..... 10011000 ... @XX3
|
2022-03-02 08:51:38 +03:00
|
|
|
XSMAXCQP 111111 ..... ..... ..... 1010100100 - @X
|
|
|
|
|
XSMINCQP 111111 ..... ..... ..... 1011100100 - @X
|
|
|
|
|
|
2022-03-02 08:51:38 +03:00
|
|
|
XSCMPEQDP 111100 ..... ..... ..... 00000011 ... @XX3
|
|
|
|
|
XSCMPGEDP 111100 ..... ..... ..... 00010011 ... @XX3
|
|
|
|
|
XSCMPGTDP 111100 ..... ..... ..... 00001011 ... @XX3
|
2022-03-02 08:51:38 +03:00
|
|
|
XSCMPEQQP 111111 ..... ..... ..... 0001000100 - @X
|
|
|
|
|
XSCMPGEQP 111111 ..... ..... ..... 0011000100 - @X
|
|
|
|
|
XSCMPGTQP 111111 ..... ..... ..... 0011100100 - @X
|
2021-12-17 19:57:18 +03:00
|
|
|
|
2024-06-18 11:58:31 +03:00
|
|
|
XVCMPEQSP 111100 ..... ..... ..... . 1000011 ... @XX3_rc
|
|
|
|
|
XVCMPGTSP 111100 ..... ..... ..... . 1001011 ... @XX3_rc
|
|
|
|
|
XVCMPGESP 111100 ..... ..... ..... . 1010011 ... @XX3_rc
|
|
|
|
|
XVCMPNESP 111100 ..... ..... ..... . 1011011 ... @XX3_rc
|
|
|
|
|
XVCMPEQDP 111100 ..... ..... ..... . 1100011 ... @XX3_rc
|
|
|
|
|
XVCMPGTDP 111100 ..... ..... ..... . 1101011 ... @XX3_rc
|
|
|
|
|
XVCMPGEDP 111100 ..... ..... ..... . 1110011 ... @XX3_rc
|
|
|
|
|
XVCMPNEDP 111100 ..... ..... ..... . 1111011 ... @XX3_rc
|
|
|
|
|
|
target/ppc: Move VSX arithmetic and max/min insns to decodetree.
Moving the following instructions to decodetree specification:
x{s, v}{add, sub, mul, div}{s, d}p : XX3-form
xs{max, min}dp, xv{max, min}{s, d}p : XX3-form
The changes were verfied by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-05-23 12:48:20 +03:00
|
|
|
XSMAXDP 111100 ..... ..... ..... 10100000 ... @XX3
|
|
|
|
|
XSMINDP 111100 ..... ..... ..... 10101000 ... @XX3
|
|
|
|
|
|
|
|
|
|
XVMAXSP 111100 ..... ..... ..... 11000000 ... @XX3
|
|
|
|
|
XVMINSP 111100 ..... ..... ..... 11001000 ... @XX3
|
|
|
|
|
XVMAXDP 111100 ..... ..... ..... 11100000 ... @XX3
|
|
|
|
|
XVMINDP 111100 ..... ..... ..... 11101000 ... @XX3
|
|
|
|
|
|
2021-12-17 19:57:18 +03:00
|
|
|
## VSX Binary Floating-Point Convert Instructions
|
|
|
|
|
|
|
|
|
|
XSCVQPDP 111111 ..... 10100 ..... 1101000100 . @X_tb_rc
|
2022-03-30 20:59:32 +03:00
|
|
|
XSCVQPUQZ 111111 ..... 00000 ..... 1101000100 - @X_tb
|
|
|
|
|
XSCVQPSQZ 111111 ..... 01000 ..... 1101000100 - @X_tb
|
2022-03-30 20:59:31 +03:00
|
|
|
XSCVUQQP 111111 ..... 00011 ..... 1101000100 - @X_tb
|
|
|
|
|
XSCVSQQP 111111 ..... 01011 ..... 1101000100 - @X_tb
|
2022-03-02 08:51:38 +03:00
|
|
|
XVCVBF16SPN 111100 ..... 10000 ..... 111011011 .. @XX2
|
|
|
|
|
XVCVSPBF16 111100 ..... 10001 ..... 111011011 .. @XX2
|
2022-05-17 15:39:23 +03:00
|
|
|
XSCVSPDPN 111100 ..... ----- ..... 101001011 .. @XX2
|
2021-12-17 19:57:19 +03:00
|
|
|
|
2022-05-17 15:39:24 +03:00
|
|
|
## VSX Binary Floating-Point Math Support Instructions
|
|
|
|
|
|
|
|
|
|
XVXSIGSP 111100 ..... 01001 ..... 111011011 .. @XX2
|
target/ppc: Moved XVTSTDC[DS]P to decodetree
Moved XVTSTDCSP and XVTSTDCDP to decodetree an restructured the helper
to be simpler and do all decoding in the decodetree (so XB, XT and DCMX
are all calculated outside the helper).
Obs: The tests in this one are slightly different, these are the sum of
these instructions with all possible immediate and those instructions
are repeated 10 times.
xvtstdcsp:
rept loop master patch
8 12500 2,76402100 2,70699100 (-2.1%)
25 4000 2,64867100 2,67884100 (+1.1%)
100 1000 2,73806300 2,78701000 (+1.8%)
500 200 3,44666500 3,61027600 (+4.7%)
2500 40 5,85790200 6,47475500 (+10.5%)
8000 12 15,22102100 17,46062900 (+14.7%)
xvtstdcdp:
rept loop master patch
8 12500 2,11818000 1,61065300 (-24.0%)
25 4000 2,04573400 1,60132200 (-21.7%)
100 1000 2,13834100 1,69988100 (-20.5%)
500 200 2,73977000 2,48631700 (-9.3%)
2500 40 5,05067000 5,25914100 (+4.1%)
8000 12 14,60507800 15,93704900 (+9.1%)
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-11-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-19 15:50:38 +03:00
|
|
|
XVTSTDCDP 111100 ..... ..... ..... 1111 . 101 ... @XX2_uim7
|
|
|
|
|
XVTSTDCSP 111100 ..... ..... ..... 1101 . 101 ... @XX2_uim7
|
target/ppc: Moved XSTSTDC[QDS]P to decodetree
Moved XSTSTDCSP, XSTSTDCDP and XSTSTDCQP to decodetree and moved some of
its decoding away from the helper as previously the DCMX, XB and BF were
calculated in the helper with the help of cpu_env, now that part was
moved to the decodetree with the rest.
xvtstdcsp:
rept loop master patch
8 12500 1,85393600 1,94683600 (+5.0%)
25 4000 1,78779800 1,92479000 (+7.7%)
100 1000 2,12775000 2,28895500 (+7.6%)
500 200 2,99655300 3,23102900 (+7.8%)
2500 40 6,89082200 7,44827500 (+8.1%)
8000 12 17,50585500 18,95152100 (+8.3%)
xvtstdcdp:
rept loop master patch
8 12500 1,39043100 1,33539800 (-4.0%)
25 4000 1,35731800 1,37347800 (+1.2%)
100 1000 1,51514800 1,56053000 (+3.0%)
500 200 2,21014400 2,47906000 (+12.2%)
2500 40 5,39488200 6,68766700 (+24.0%)
8000 12 13,98623900 18,17661900 (+30.0%)
xvtstdcdp:
rept loop master patch
8 12500 1,35123800 1,34455800 (-0.5%)
25 4000 1,36441200 1,36759600 (+0.2%)
100 1000 1,49763500 1,54138400 (+2.9%)
500 200 2,19020200 2,46196400 (+12.4%)
2500 40 5,39265700 6,68147900 (+23.9%)
8000 12 14,04163600 18,19669600 (+29.6%)
As some values are now decoded outside the helper and passed to it as an
argument the number of arguments of the helper increased, the number
of TCGop needed to load the arguments increased. I suspect that's why
the slow-down in the tests with a high REPT but low LOOP.
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-12-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-10-19 15:50:39 +03:00
|
|
|
XSTSTDCSP 111100 ... ....... ..... 100101010 . - @XX2_bf_uim xb=%xx_xb
|
|
|
|
|
XSTSTDCDP 111100 ... ....... ..... 101101010 . - @XX2_bf_uim xb=%xx_xb
|
|
|
|
|
XSTSTDCQP 111111 ... ....... xb:5 1011000100 - @XX2_bf_uim
|
2022-05-17 15:39:24 +03:00
|
|
|
|
2022-03-02 08:51:38 +03:00
|
|
|
## VSX Vector Test Least-Significant Bit by Byte Instruction
|
|
|
|
|
|
|
|
|
|
XVTLSBB 111100 ... -- 00010 ..... 111011011 . - @XX2_bf_xb
|
|
|
|
|
|
2021-12-17 19:57:19 +03:00
|
|
|
### rfebb
|
|
|
|
|
&XL_s s:uint8_t
|
|
|
|
|
@XL_s ......-------------- s:1 .......... - &XL_s
|
|
|
|
|
RFEBB 010011-------------- . 0010010010 - @XL_s
|
2022-05-24 17:05:30 +03:00
|
|
|
|
|
|
|
|
## Accumulator Instructions
|
|
|
|
|
|
|
|
|
|
XXMFACC 011111 ... -- 00000 ----- 0010110001 - @X_a
|
|
|
|
|
XXMTACC 011111 ... -- 00001 ----- 0010110001 - @X_a
|
|
|
|
|
XXSETACCZ 011111 ... -- 00011 ----- 0010110001 - @X_a
|
2022-05-24 17:05:31 +03:00
|
|
|
|
2024-05-23 12:48:21 +03:00
|
|
|
## VSX Vector Logical instructions
|
|
|
|
|
|
|
|
|
|
XXLAND 111100 ..... ..... ..... 10000010 ... @XX3
|
|
|
|
|
XXLANDC 111100 ..... ..... ..... 10001010 ... @XX3
|
|
|
|
|
XXLOR 111100 ..... ..... ..... 10010010 ... @XX3
|
|
|
|
|
XXLXOR 111100 ..... ..... ..... 10011010 ... @XX3
|
|
|
|
|
XXLNOR 111100 ..... ..... ..... 10100010 ... @XX3
|
|
|
|
|
XXLEQV 111100 ..... ..... ..... 10111010 ... @XX3
|
|
|
|
|
XXLNAND 111100 ..... ..... ..... 10110010 ... @XX3
|
|
|
|
|
XXLORC 111100 ..... ..... ..... 10101010 ... @XX3
|
|
|
|
|
|
2022-05-24 17:05:31 +03:00
|
|
|
## VSX GER instruction
|
|
|
|
|
|
|
|
|
|
XVI4GER8 111011 ... -- ..... ..... 00100011 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
XVI4GER8PP 111011 ... -- ..... ..... 00100010 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
XVI8GER4 111011 ... -- ..... ..... 00000011 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
XVI8GER4PP 111011 ... -- ..... ..... 00000010 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
XVI16GER2 111011 ... -- ..... ..... 01001011 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
XVI16GER2PP 111011 ... -- ..... ..... 01101011 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
XVI8GER4SPP 111011 ... -- ..... ..... 01100011 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
XVI16GER2S 111011 ... -- ..... ..... 00101011 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
XVI16GER2SPP 111011 ... -- ..... ..... 00101010 ..- @XX3_at xa=%xx_xa
|
2022-05-24 17:05:33 +03:00
|
|
|
|
2022-05-24 17:05:36 +03:00
|
|
|
XVBF16GER2 111011 ... -- ..... ..... 00110011 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
XVBF16GER2PP 111011 ... -- ..... ..... 00110010 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
XVBF16GER2PN 111011 ... -- ..... ..... 10110010 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
XVBF16GER2NP 111011 ... -- ..... ..... 01110010 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
XVBF16GER2NN 111011 ... -- ..... ..... 11110010 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
|
2022-05-24 17:05:34 +03:00
|
|
|
XVF16GER2 111011 ... -- ..... ..... 00010011 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
XVF16GER2PP 111011 ... -- ..... ..... 00010010 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
XVF16GER2PN 111011 ... -- ..... ..... 10010010 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
XVF16GER2NP 111011 ... -- ..... ..... 01010010 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
XVF16GER2NN 111011 ... -- ..... ..... 11010010 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
|
2022-05-24 17:05:33 +03:00
|
|
|
XVF32GER 111011 ... -- ..... ..... 00011011 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
XVF32GERPP 111011 ... -- ..... ..... 00011010 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
XVF32GERPN 111011 ... -- ..... ..... 10011010 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
XVF32GERNP 111011 ... -- ..... ..... 01011010 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
XVF32GERNN 111011 ... -- ..... ..... 11011010 ..- @XX3_at xa=%xx_xa
|
|
|
|
|
|
|
|
|
|
XVF64GER 111011 ... -- .... 0 ..... 00111011 ..- @XX3_at xa=%xx_xa_pair
|
|
|
|
|
XVF64GERPP 111011 ... -- .... 0 ..... 00111010 ..- @XX3_at xa=%xx_xa_pair
|
|
|
|
|
XVF64GERPN 111011 ... -- .... 0 ..... 10111010 ..- @XX3_at xa=%xx_xa_pair
|
|
|
|
|
XVF64GERNP 111011 ... -- .... 0 ..... 01111010 ..- @XX3_at xa=%xx_xa_pair
|
|
|
|
|
XVF64GERNN 111011 ... -- .... 0 ..... 11111010 ..- @XX3_at xa=%xx_xa_pair
|
2022-05-25 16:49:47 +03:00
|
|
|
|
|
|
|
|
## Vector Division Instructions
|
|
|
|
|
|
|
|
|
|
VDIVSW 000100 ..... ..... ..... 00110001011 @VX
|
|
|
|
|
VDIVUW 000100 ..... ..... ..... 00010001011 @VX
|
|
|
|
|
VDIVSD 000100 ..... ..... ..... 00111001011 @VX
|
|
|
|
|
VDIVUD 000100 ..... ..... ..... 00011001011 @VX
|
2022-05-25 16:49:48 +03:00
|
|
|
VDIVSQ 000100 ..... ..... ..... 00100001011 @VX
|
|
|
|
|
VDIVUQ 000100 ..... ..... ..... 00000001011 @VX
|
2022-05-25 16:49:49 +03:00
|
|
|
|
|
|
|
|
VDIVESW 000100 ..... ..... ..... 01110001011 @VX
|
|
|
|
|
VDIVEUW 000100 ..... ..... ..... 01010001011 @VX
|
2022-05-25 16:49:52 +03:00
|
|
|
VDIVESD 000100 ..... ..... ..... 01111001011 @VX
|
|
|
|
|
VDIVEUD 000100 ..... ..... ..... 01011001011 @VX
|
|
|
|
|
VDIVESQ 000100 ..... ..... ..... 01100001011 @VX
|
|
|
|
|
VDIVEUQ 000100 ..... ..... ..... 01000001011 @VX
|
2022-05-25 16:49:53 +03:00
|
|
|
|
|
|
|
|
VMODSW 000100 ..... ..... ..... 11110001011 @VX
|
|
|
|
|
VMODUW 000100 ..... ..... ..... 11010001011 @VX
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VMODSD 000100 ..... ..... ..... 11111001011 @VX
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VMODUD 000100 ..... ..... ..... 11011001011 @VX
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2022-05-25 16:49:54 +03:00
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VMODSQ 000100 ..... ..... ..... 11100001011 @VX
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VMODUQ 000100 ..... ..... ..... 11000001011 @VX
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2022-07-12 22:37:40 +03:00
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2022-07-01 16:34:59 +03:00
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## SLB Management Instructions
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SLBIE 011111 ----- ----- ..... 0110110010 - @X_rb
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2022-07-01 16:35:00 +03:00
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SLBIEG 011111 ..... ----- ..... 0111010010 - @X_tb
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2022-07-01 16:34:59 +03:00
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2022-07-01 16:35:01 +03:00
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SLBIA 011111 --... ----- ----- 0111110010 - @X_ih
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2022-07-01 16:35:07 +03:00
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SLBIAG 011111 ..... ----. ----- 1101010010 - @X_rs_l
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2022-07-01 16:35:01 +03:00
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2022-07-01 16:35:02 +03:00
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SLBMTE 011111 ..... ----- ..... 0110010010 - @X_tb
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2022-07-01 16:35:03 +03:00
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SLBMFEV 011111 ..... ----- ..... 1101010011 - @X_tb
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2022-07-01 16:35:04 +03:00
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SLBMFEE 011111 ..... ----- ..... 1110010011 - @X_tb
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2022-07-01 16:35:03 +03:00
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2022-07-01 16:35:05 +03:00
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SLBFEE 011111 ..... ----- ..... 1111010011 1 @X_tb
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2022-07-01 16:35:06 +03:00
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SLBSYNC 011111 ----- ----- ----- 0101010010 -
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2022-07-12 22:37:40 +03:00
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## TLB Management Instructions
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&X_tlbie rb rs ric prs:bool r:bool
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@X_tlbie ...... rs:5 - ric:2 prs:1 r:1 rb:5 .......... - &X_tlbie
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TLBIE 011111 ..... - .. . . ..... 0100110010 - @X_tlbie
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TLBIEL 011111 ..... - .. . . ..... 0100010010 - @X_tlbie
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2022-10-06 23:06:52 +03:00
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# Processor Control Instructions
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MSGCLR 011111 ----- ----- ..... 0011101110 - @X_rb
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MSGSND 011111 ----- ----- ..... 0011001110 - @X_rb
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2022-10-06 23:06:53 +03:00
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MSGCLRP 011111 ----- ----- ..... 0010101110 - @X_rb
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MSGSNDP 011111 ----- ----- ..... 0010001110 - @X_rb
|
2022-10-06 23:06:54 +03:00
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MSGSYNC 011111 ----- ----- ----- 1101110110 -
|
2024-05-01 16:04:32 +03:00
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# Memory Barrier Instructions
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|
2024-05-01 16:04:34 +03:00
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&X_sync l sc
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@X_sync ...... .. l:3 ... sc:2 ..... .......... . &X_sync
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SYNC 011111 -- ... --- .. ----- 1001010110 - @X_sync
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2024-05-01 16:04:32 +03:00
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EIEIO 011111 ----- ----- ----- 1101010110 -
|
2024-03-28 13:41:35 +03:00
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# Branch History Rolling Buffer (BHRB) Instructions
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&XFX_bhrbe rt bhrbe
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@XFX_bhrbe ...... rt:5 bhrbe:10 .......... - &XFX_bhrbe
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MFBHRBE 011111 ..... ..... ..... 0100101110 - @XFX_bhrbe
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CLRBHRB 011111 ----- ----- ----- 0110101110 -
|
2023-06-18 12:39:13 +03:00
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## Misc POWER instructions
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ATTN 000000 00000 00000 00000 0100000000 0
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