target/ppc: Move mul{li, lw, lwo, hw, hwu} instructions to decodetree.
Moving the following instructions to decodetree specification :
mulli : D-form
mul{lw, lwo, hw, hwu}[.] : XO-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Also cleaned up code for mullw[o][.] as per review comments while
keeping the logic of the tcg ops generated semantically same.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Chinmay Rath
Nicholas Piggin
parent
177fcc06dc
commit
a1faff873a
@ -202,6 +202,9 @@
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&XO_ta rt ra oe:bool rc:bool
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@XO_ta ...... rt:5 ra:5 ..... oe:1 ......... rc:1 &XO_ta
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&XO_tab_rc rt ra rb rc:bool
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@XO_tab_rc ...... rt:5 ra:5 rb:5 . ......... rc:1 &XO_tab_rc
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%xx_xt 0:1 21:5
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%xx_xb 1:1 11:5
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%xx_xa 2:1 16:5
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@ -362,6 +365,12 @@ SUBFE 011111 ..... ..... ..... . 010001000 . @XO
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SUBFME 011111 ..... ..... ----- . 011101000 . @XO_ta
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SUBFZE 011111 ..... ..... ----- . 011001000 . @XO_ta
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MULLI 000111 ..... ..... ................ @D
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MULLW 011111 ..... ..... ..... 0 011101011 . @XO_tab_rc
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MULLWO 011111 ..... ..... ..... 1 011101011 . @XO_tab_rc
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MULHW 011111 ..... ..... ..... - 001001011 . @XO_tab_rc
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MULHWU 011111 ..... ..... ..... - 000001011 . @XO_tab_rc
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## Fixed-Point Logical Instructions
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CFUGED 011111 ..... ..... ..... 0011011100 - @X
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@ -1947,90 +1947,6 @@ GEN_INT_ARITH_MODD(modud, 0x08, 0);
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GEN_INT_ARITH_MODD(modsd, 0x18, 1);
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#endif
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/* mulhw mulhw. */
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static void gen_mulhw(DisasContext *ctx)
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{
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TCGv_i32 t0 = tcg_temp_new_i32();
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TCGv_i32 t1 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
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tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
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tcg_gen_muls2_i32(t0, t1, t0, t1);
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tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
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if (unlikely(Rc(ctx->opcode) != 0)) {
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gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
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}
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}
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/* mulhwu mulhwu. */
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static void gen_mulhwu(DisasContext *ctx)
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{
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TCGv_i32 t0 = tcg_temp_new_i32();
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TCGv_i32 t1 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
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tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
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tcg_gen_mulu2_i32(t0, t1, t0, t1);
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tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
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if (unlikely(Rc(ctx->opcode) != 0)) {
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gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
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}
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}
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/* mullw mullw. */
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static void gen_mullw(DisasContext *ctx)
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{
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#if defined(TARGET_PPC64)
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TCGv_i64 t0, t1;
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t0 = tcg_temp_new_i64();
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t1 = tcg_temp_new_i64();
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tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
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tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
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tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
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#else
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tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
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cpu_gpr[rB(ctx->opcode)]);
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#endif
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if (unlikely(Rc(ctx->opcode) != 0)) {
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gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
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}
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}
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/* mullwo mullwo. */
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static void gen_mullwo(DisasContext *ctx)
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{
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TCGv_i32 t0 = tcg_temp_new_i32();
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TCGv_i32 t1 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
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tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
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tcg_gen_muls2_i32(t0, t1, t0, t1);
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#if defined(TARGET_PPC64)
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tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
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#else
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tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
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#endif
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tcg_gen_sari_i32(t0, t0, 31);
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tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
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tcg_gen_extu_i32_tl(cpu_ov, t0);
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if (is_isa300(ctx)) {
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tcg_gen_mov_tl(cpu_ov32, cpu_ov);
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}
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tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
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if (unlikely(Rc(ctx->opcode) != 0)) {
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gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
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}
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}
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/* mulli */
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static void gen_mulli(DisasContext *ctx)
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{
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tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
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SIMM(ctx->opcode));
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}
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#if defined(TARGET_PPC64)
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/* mulhd mulhd. */
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static void gen_mulhd(DisasContext *ctx)
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@ -6343,11 +6259,6 @@ GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
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GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
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GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
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GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
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GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
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GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
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GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
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GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
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GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
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#if defined(TARGET_PPC64)
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GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
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#endif
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@ -395,6 +395,72 @@ TRANS(SUBFE, do_subf_XO, true, true)
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TRANS(SUBFME, do_subf_const_XO, tcg_constant_tl(-1LL), true, true)
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TRANS(SUBFZE, do_subf_const_XO, tcg_constant_tl(0), true, true)
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static bool trans_MULLI(DisasContext *ctx, arg_MULLI *a)
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{
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tcg_gen_muli_tl(cpu_gpr[a->rt], cpu_gpr[a->ra], a->si);
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return true;
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}
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static bool trans_MULLW(DisasContext *ctx, arg_MULLW *a)
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{
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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tcg_gen_ext32s_tl(t0, cpu_gpr[a->ra]);
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tcg_gen_ext32s_tl(t1, cpu_gpr[a->rb]);
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tcg_gen_mul_tl(cpu_gpr[a->rt], t0, t1);
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if (unlikely(a->rc)) {
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gen_set_Rc0(ctx, cpu_gpr[a->rt]);
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}
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return true;
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}
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static bool trans_MULLWO(DisasContext *ctx, arg_MULLWO *a)
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{
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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#if defined(TARGET_PPC64)
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tcg_gen_ext32s_i64(t0, cpu_gpr[a->ra]);
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tcg_gen_ext32s_i64(t1, cpu_gpr[a->rb]);
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tcg_gen_mul_i64(cpu_gpr[a->rt], t0, t1);
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tcg_gen_sextract_i64(t0, cpu_gpr[a->rt], 31, 1);
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tcg_gen_sari_i64(t1, cpu_gpr[a->rt], 32);
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#else
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tcg_gen_muls2_i32(cpu_gpr[a->rt], t1, cpu_gpr[a->ra], cpu_gpr[a->rb]);
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tcg_gen_sari_i32(t0, cpu_gpr[a->rt], 31);
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#endif
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tcg_gen_setcond_tl(TCG_COND_NE, cpu_ov, t0, t1);
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if (is_isa300(ctx)) {
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tcg_gen_mov_tl(cpu_ov32, cpu_ov);
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}
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tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
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if (unlikely(a->rc)) {
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gen_set_Rc0(ctx, cpu_gpr[a->rt]);
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}
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return true;
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}
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static bool do_mulhw(DisasContext *ctx, arg_XO_tab_rc *a,
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void (*helper)(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1,
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TCGv_i32 arg2))
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{
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TCGv_i32 t0 = tcg_temp_new_i32();
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TCGv_i32 t1 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(t0, cpu_gpr[a->ra]);
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tcg_gen_trunc_tl_i32(t1, cpu_gpr[a->rb]);
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helper(t0, t1, t0, t1);
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tcg_gen_extu_i32_tl(cpu_gpr[a->rt], t1);
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if (unlikely(a->rc)) {
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gen_set_Rc0(ctx, cpu_gpr[a->rt]);
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}
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return true;
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}
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TRANS(MULHW, do_mulhw, tcg_gen_muls2_i32)
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TRANS(MULHWU, do_mulhw, tcg_gen_mulu2_i32)
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static bool trans_INVALID(DisasContext *ctx, arg_INVALID *a)
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{
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gen_invalid(ctx);
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