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target/ppc: Move neg, darn, mod{sw, uw} to decodetree.

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Moving the below instructions to decodetree specification :

	neg[o][.]       	: XO-form
	mod{sw, uw}, darn	: X-form

The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
[np: 32-bit compile fix]
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Chinmay Rath 2024-04-23 12:02:30 +05:30 committed by Nicholas Piggin
parent 2871921d85
commit a81b5c1867
5 changed files with 60 additions and 60 deletions
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4
target/ppc/helper.h
View File

@ -71,8 +71,8 @@ DEF_HELPER_FLAGS_2(cmpeqb, TCG_CALL_NO_RWG_SE, i32, tl, tl)
DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_3(srad, tl, env, tl, tl)
DEF_HELPER_FLAGS_0(darn32, TCG_CALL_NO_RWG, tl)
DEF_HELPER_FLAGS_0(darn64, TCG_CALL_NO_RWG, tl)
DEF_HELPER_FLAGS_0(DARN32, TCG_CALL_NO_RWG, tl)
DEF_HELPER_FLAGS_0(DARN64, TCG_CALL_NO_RWG, tl)
#endif
DEF_HELPER_FLAGS_1(cntlsw32, TCG_CALL_NO_RWG_SE, i32, i32)

8
target/ppc/insn32.decode
View File

@ -196,6 +196,9 @@
&X_a ra
@X_a ...... ra:3 .. ..... ..... .......... . &X_a
&X_tl rt l
@X_tl ...... rt:5 ... l:2 ..... .......... . &X_tl
&XO rt ra rb oe:bool rc:bool
@XO ...... rt:5 ra:5 rb:5 oe:1 ......... rc:1 &XO
@ -376,6 +379,11 @@ DIVWU 011111 ..... ..... ..... . 111001011 . @XO
DIVWE 011111 ..... ..... ..... . 110101011 . @XO
DIVWEU 011111 ..... ..... ..... . 110001011 . @XO
MODSW 011111 ..... ..... ..... 1100001011 - @X
MODUW 011111 ..... ..... ..... 0100001011 - @X
DARN 011111 ..... --- .. ----- 1011110011 - @X_tl
NEG 011111 ..... ..... ----- . 001101000 . @XO_ta
## Fixed-Point Logical Instructions
CFUGED 011111 ..... ..... ..... 0011011100 - @X

4
target/ppc/int_helper.c
View File

@ -171,7 +171,7 @@ uint32_t helper_cmpeqb(target_ulong ra, target_ulong rb)
/*
* Return a random number.
*/
uint64_t helper_darn32(void)
uint64_t helper_DARN32(void)
{
Error *err = NULL;
uint32_t ret;
@ -186,7 +186,7 @@ uint64_t helper_darn32(void)
return ret;
}
uint64_t helper_darn64(void)
uint64_t helper_DARN64(void)
{
Error *err = NULL;
uint64_t ret;

56
target/ppc/translate.c
View File

@ -1877,17 +1877,6 @@ static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
}
}
#define GEN_INT_ARITH_MODW(name, opc3, sign) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
sign); \
}
GEN_INT_ARITH_MODW(moduw, 0x08, 0);
GEN_INT_ARITH_MODW(modsw, 0x18, 1);
#if defined(TARGET_PPC64)
static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
TCGv arg2, int sign)
@ -2054,27 +2043,6 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
}
}
/* neg neg. nego nego. */
static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
{
TCGv zero = tcg_constant_tl(0);
gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
zero, 0, 0, compute_ov, Rc(ctx->opcode));
}
static void gen_neg(DisasContext *ctx)
{
tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
if (unlikely(Rc(ctx->opcode))) {
gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
}
}
static void gen_nego(DisasContext *ctx)
{
gen_op_arith_neg(ctx, 1);
}
/*** Integer logical ***/
#define GEN_LOGICAL2(name, tcg_op, opc, type) \
static void glue(gen_, name)(DisasContext *ctx) \
@ -2400,24 +2368,6 @@ static void gen_cnttzd(DisasContext *ctx)
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
}
/* darn */
static void gen_darn(DisasContext *ctx)
{
int l = L(ctx->opcode);
if (l > 2) {
tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
} else {
translator_io_start(&ctx->base);
if (l == 0) {
gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
} else {
/* Return 64-bit random for both CRN and RRN */
gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
}
}
}
#endif
/*** Integer rotate ***/
@ -6243,8 +6193,6 @@ GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
#if defined(TARGET_PPC64)
GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
#endif
GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
@ -6265,7 +6213,6 @@ GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
#endif
@ -6450,9 +6397,6 @@ GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
#endif
GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
#if defined(TARGET_PPC64)
#undef GEN_INT_ARITH_DIVD
#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \

48
target/ppc/translate/fixedpoint-impl.c.inc
View File

@ -485,6 +485,54 @@ TRANS(DIVWU, do_divw, 0);
TRANS(DIVWE, do_divwe, gen_helper_DIVWE);
TRANS(DIVWEU, do_divwe, gen_helper_DIVWEU);
static bool do_modw(DisasContext *ctx, arg_X *a, bool sign)
{
REQUIRE_INSNS_FLAGS2(ctx, ISA300);
gen_op_arith_modw(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], cpu_gpr[a->rb],
sign);
return true;
}
TRANS(MODUW, do_modw, false);
TRANS(MODSW, do_modw, true);
static bool trans_NEG(DisasContext *ctx, arg_NEG *a)
{
if (a->oe) {
TCGv zero = tcg_constant_tl(0);
gen_op_arith_subf(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], zero,
false, false, true, a->rc);
} else {
tcg_gen_neg_tl(cpu_gpr[a->rt], cpu_gpr[a->ra]);
if (unlikely(a->rc)) {
gen_set_Rc0(ctx, cpu_gpr[a->rt]);
}
}
return true;
}
static bool trans_DARN(DisasContext *ctx, arg_DARN *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_INSNS_FLAGS2(ctx, ISA300);
#if defined(TARGET_PPC64)
if (a->l > 2) {
tcg_gen_movi_i64(cpu_gpr[a->rt], -1);
} else {
translator_io_start(&ctx->base);
if (a->l == 0) {
gen_helper_DARN32(cpu_gpr[a->rt]);
} else {
/* Return 64-bit random for both CRN and RRN */
gen_helper_DARN64(cpu_gpr[a->rt]);
}
}
#else
qemu_build_not_reached();
#endif
return true;
}
static bool trans_INVALID(DisasContext *ctx, arg_INVALID *a)
{
gen_invalid(ctx);