target/ppc: Add ISA v3.1 variants of sync instruction
POWER10 adds a new field to sync for store-store syncs, and some new variants of the existing syncs that include persistent memory. Implement the store-store syncs and plwsync/phwsync. Reviewed-by: Chinmay Rath <rathc@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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@ -1001,7 +1001,7 @@ MSGSYNC 011111 ----- ----- ----- 1101110110 -
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# Memory Barrier Instructions
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&X_sync l
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@X_sync ...... ... l:2 ..... ..... .......... . &X_sync
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SYNC 011111 --- .. ----- ----- 1001010110 - @X_sync
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&X_sync l sc
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@X_sync ...... .. l:3 ... sc:2 ..... .......... . &X_sync
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SYNC 011111 -- ... --- .. ----- 1001010110 - @X_sync
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EIEIO 011111 ----- ----- ----- 1101010110 -
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@ -25,6 +25,7 @@ static bool trans_SYNC(DisasContext *ctx, arg_X_sync *a)
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{
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TCGBar bar = TCG_MO_ALL;
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uint32_t l = a->l;
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uint32_t sc = a->sc;
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/*
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* BookE uses the msync mnemonic. This means hwsync, except in the
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@ -41,20 +42,36 @@ static bool trans_SYNC(DisasContext *ctx, arg_X_sync *a)
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return false;
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}
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if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) {
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bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST;
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/*
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* In ISA v3.1, the L field grew one bit. Mask that out to ignore it in
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* older processors. It also added the SC field, zero this to ignore
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* it too.
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*/
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if (!(ctx->insns_flags2 & PPC2_ISA310)) {
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l &= 0x3;
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sc = 0;
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}
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/*
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* We may need to check for a pending TLB flush.
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*
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* We do this on ptesync (l == 2) on ppc64 and any sync on ppc32.
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*
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* Additionally, this can only happen in kernel mode however so
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* check MSR_PR as well.
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*/
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if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
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gen_check_tlb_flush(ctx, true);
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if (sc) {
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/* Store syncs [stsync, stcisync, stncisync]. These ignore L. */
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bar = TCG_MO_ST_ST;
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} else {
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if (((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) || (l == 5)) {
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/* lwsync, or plwsync on POWER10 and later */
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bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST;
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}
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/*
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* We may need to check for a pending TLB flush.
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*
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* We do this on ptesync (l == 2) on ppc64 and any sync on ppc32.
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*
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* Additionally, this can only happen in kernel mode however so
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* check MSR_PR as well.
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*/
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if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
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gen_check_tlb_flush(ctx, true);
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}
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}
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tcg_gen_mb(bar | TCG_BAR_SC);
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