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target/ppc: Implemented xvi*ger* instructions

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Implement the following PowerISA v3.1 instructions:
xvi4ger8:     VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update)
xvi4ger8pp:   VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update)
Positive multiply, Positive accumulate
xvi8ger4:     VSX Vector 4-bit Signed Integer GER (rank-8 update)
xvi8ger4pp:   VSX Vector 4-bit Signed Integer GER (rank-8 update)
Positive multiply, Positive accumulate
xvi8ger4spp:  VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update)
with Saturate Positive multiply, Positive accumulate
xvi16ger2:    VSX Vector 16-bit Signed Integer GER (rank-2 update)
xvi16ger2pp:  VSX Vector 16-bit Signed Integer GER (rank-2 update)
Positive multiply, Positive accumulate
xvi16ger2s:   VSX Vector 16-bit Signed Integer GER (rank-2 update)
with Saturation
xvi16ger2spp: VSX Vector 16-bit Signed Integer GER (rank-2 update)
with Saturation Positive multiply, Positive accumulate

Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220524140537.27451-3-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Lucas Mateus Castro (alqotel) 2022-05-24 11:05:31 -03:00 committed by Daniel Henrique Barboza
parent a702c5339e
commit 345531533f
6 changed files with 218 additions and 0 deletions
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1
target/ppc/cpu.h
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@ -238,6 +238,7 @@ typedef union _ppc_vsr_t {
typedef ppc_vsr_t ppc_avr_t;
typedef ppc_vsr_t ppc_fprp_t;
typedef ppc_vsr_t ppc_acc_t;
#if !defined(CONFIG_USER_ONLY)
/* Software TLB cache */

13
target/ppc/helper.h
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@ -133,6 +133,10 @@ DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i64)
#define dh_ctype_vsr ppc_vsr_t *
#define dh_typecode_vsr dh_typecode_ptr
#define dh_alias_acc ptr
#define dh_ctype_acc ppc_acc_t *
#define dh_typecode_acc dh_typecode_ptr
DEF_HELPER_FLAGS_3(vavgub, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(vavguh, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(vavguw, TCG_CALL_NO_RWG, void, avr, avr, avr)
@ -537,6 +541,15 @@ DEF_HELPER_FLAGS_5(XXBLENDVB, TCG_CALL_NO_RWG, void, vsr, vsr, vsr, vsr, i32)
DEF_HELPER_FLAGS_5(XXBLENDVH, TCG_CALL_NO_RWG, void, vsr, vsr, vsr, vsr, i32)
DEF_HELPER_FLAGS_5(XXBLENDVW, TCG_CALL_NO_RWG, void, vsr, vsr, vsr, vsr, i32)
DEF_HELPER_FLAGS_5(XXBLENDVD, TCG_CALL_NO_RWG, void, vsr, vsr, vsr, vsr, i32)
DEF_HELPER_5(XVI4GER8, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVI4GER8PP, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVI8GER4, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVI8GER4PP, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVI8GER4SPP, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVI16GER2, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVI16GER2S, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVI16GER2PP, void, env, vsr, vsr, acc, i32)
DEF_HELPER_5(XVI16GER2SPP, void, env, vsr, vsr, acc, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)

18
target/ppc/insn32.decode
View File

@ -175,6 +175,12 @@
&XX3 xt xa xb
@XX3 ...... ..... ..... ..... ........ ... &XX3 xt=%xx_xt xa=%xx_xa xb=%xx_xb
# 32 bit GER instructions have all mask bits considered 1
&MMIRR_XX3 xa xb xt pmsk xmsk ymsk
%xx_at 23:3
@XX3_at ...... ... .. ..... ..... ........ ... &MMIRR_XX3 xt=%xx_at xb=%xx_xb \
pmsk=255 xmsk=15 ymsk=15
&XX3_dm xt xa xb dm
@XX3_dm ...... ..... ..... ..... . dm:2 ..... ... &XX3_dm xt=%xx_xt xa=%xx_xa xb=%xx_xb
@ -743,3 +749,15 @@ RFEBB 010011-------------- . 0010010010 - @XL_s
XXMFACC 011111 ... -- 00000 ----- 0010110001 - @X_a
XXMTACC 011111 ... -- 00001 ----- 0010110001 - @X_a
XXSETACCZ 011111 ... -- 00011 ----- 0010110001 - @X_a
## VSX GER instruction
XVI4GER8 111011 ... -- ..... ..... 00100011 ..- @XX3_at xa=%xx_xa
XVI4GER8PP 111011 ... -- ..... ..... 00100010 ..- @XX3_at xa=%xx_xa
XVI8GER4 111011 ... -- ..... ..... 00000011 ..- @XX3_at xa=%xx_xa
XVI8GER4PP 111011 ... -- ..... ..... 00000010 ..- @XX3_at xa=%xx_xa
XVI16GER2 111011 ... -- ..... ..... 01001011 ..- @XX3_at xa=%xx_xa
XVI16GER2PP 111011 ... -- ..... ..... 01101011 ..- @XX3_at xa=%xx_xa
XVI8GER4SPP 111011 ... -- ..... ..... 01100011 ..- @XX3_at xa=%xx_xa
XVI16GER2S 111011 ... -- ..... ..... 00101011 ..- @XX3_at xa=%xx_xa
XVI16GER2SPP 111011 ... -- ..... ..... 00101010 ..- @XX3_at xa=%xx_xa

130
target/ppc/int_helper.c
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@ -782,6 +782,136 @@ VCT(uxs, cvtsduw, u32)
VCT(sxs, cvtsdsw, s32)
#undef VCT
typedef int64_t do_ger(uint32_t, uint32_t, uint32_t);
static int64_t ger_rank8(uint32_t a, uint32_t b, uint32_t mask)
{
int64_t psum = 0;
for (int i = 0; i < 8; i++, mask >>= 1) {
if (mask & 1) {
psum += sextract32(a, 4 * i, 4) * sextract32(b, 4 * i, 4);
}
}
return psum;
}
static int64_t ger_rank4(uint32_t a, uint32_t b, uint32_t mask)
{
int64_t psum = 0;
for (int i = 0; i < 4; i++, mask >>= 1) {
if (mask & 1) {
psum += sextract32(a, 8 * i, 8) * (int64_t)extract32(b, 8 * i, 8);
}
}
return psum;
}
static int64_t ger_rank2(uint32_t a, uint32_t b, uint32_t mask)
{
int64_t psum = 0;
for (int i = 0; i < 2; i++, mask >>= 1) {
if (mask & 1) {
psum += sextract32(a, 16 * i, 16) * sextract32(b, 16 * i, 16);
}
}
return psum;
}
static void xviger(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b, ppc_acc_t *at,
uint32_t mask, bool sat, bool acc, do_ger ger)
{
uint8_t pmsk = FIELD_EX32(mask, GER_MSK, PMSK),
xmsk = FIELD_EX32(mask, GER_MSK, XMSK),
ymsk = FIELD_EX32(mask, GER_MSK, YMSK);
uint8_t xmsk_bit, ymsk_bit;
int64_t psum;
int i, j;
for (i = 0, xmsk_bit = 1 << 3; i < 4; i++, xmsk_bit >>= 1) {
for (j = 0, ymsk_bit = 1 << 3; j < 4; j++, ymsk_bit >>= 1) {
if ((xmsk_bit & xmsk) && (ymsk_bit & ymsk)) {
psum = ger(a->VsrW(i), b->VsrW(j), pmsk);
if (acc) {
psum += at[i].VsrSW(j);
}
if (sat && psum > INT32_MAX) {
set_vscr_sat(env);
at[i].VsrSW(j) = INT32_MAX;
} else if (sat && psum < INT32_MIN) {
set_vscr_sat(env);
at[i].VsrSW(j) = INT32_MIN;
} else {
at[i].VsrSW(j) = (int32_t) psum;
}
} else {
at[i].VsrSW(j) = 0;
}
}
}
}
QEMU_FLATTEN
void helper_XVI4GER8(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
ppc_acc_t *at, uint32_t mask)
{
xviger(env, a, b, at, mask, false, false, ger_rank8);
}
QEMU_FLATTEN
void helper_XVI4GER8PP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
ppc_acc_t *at, uint32_t mask)
{
xviger(env, a, b, at, mask, false, true, ger_rank8);
}
QEMU_FLATTEN
void helper_XVI8GER4(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
ppc_acc_t *at, uint32_t mask)
{
xviger(env, a, b, at, mask, false, false, ger_rank4);
}
QEMU_FLATTEN
void helper_XVI8GER4PP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
ppc_acc_t *at, uint32_t mask)
{
xviger(env, a, b, at, mask, false, true, ger_rank4);
}
QEMU_FLATTEN
void helper_XVI8GER4SPP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
ppc_acc_t *at, uint32_t mask)
{
xviger(env, a, b, at, mask, true, true, ger_rank4);
}
QEMU_FLATTEN
void helper_XVI16GER2(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
ppc_acc_t *at, uint32_t mask)
{
xviger(env, a, b, at, mask, false, false, ger_rank2);
}
QEMU_FLATTEN
void helper_XVI16GER2S(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
ppc_acc_t *at, uint32_t mask)
{
xviger(env, a, b, at, mask, true, false, ger_rank2);
}
QEMU_FLATTEN
void helper_XVI16GER2PP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
ppc_acc_t *at, uint32_t mask)
{
xviger(env, a, b, at, mask, false, true, ger_rank2);
}
QEMU_FLATTEN
void helper_XVI16GER2SPP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
ppc_acc_t *at, uint32_t mask)
{
xviger(env, a, b, at, mask, true, true, ger_rank2);
}
target_ulong helper_vclzlsbb(ppc_avr_t *r)
{
target_ulong count = 0;

15
target/ppc/internal.h
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@ -18,6 +18,8 @@
#ifndef PPC_INTERNAL_H
#define PPC_INTERNAL_H
#include "hw/registerfields.h"
#define FUNC_MASK(name, ret_type, size, max_val) \
static inline ret_type name(uint##size##_t start, \
uint##size##_t end) \
@ -291,4 +293,17 @@ G_NORETURN void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
uintptr_t retaddr);
#endif
FIELD(GER_MSK, XMSK, 0, 4)
FIELD(GER_MSK, YMSK, 4, 4)
FIELD(GER_MSK, PMSK, 8, 8)
static inline int ger_pack_masks(int pmsk, int ymsk, int xmsk)
{
int msk = 0;
msk = FIELD_DP32(msk, GER_MSK, XMSK, xmsk);
msk = FIELD_DP32(msk, GER_MSK, YMSK, ymsk);
msk = FIELD_DP32(msk, GER_MSK, PMSK, pmsk);
return msk;
}
#endif /* PPC_INTERNAL_H */

41
target/ppc/translate/vsx-impl.c.inc
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@ -17,6 +17,13 @@ static inline TCGv_ptr gen_vsr_ptr(int reg)
return r;
}
static inline TCGv_ptr gen_acc_ptr(int reg)
{
TCGv_ptr r = tcg_temp_new_ptr();
tcg_gen_addi_ptr(r, cpu_env, acc_full_offset(reg));
return r;
}
#define VSX_LOAD_SCALAR(name, operation) \
static void gen_##name(DisasContext *ctx) \
{ \
@ -2847,6 +2854,40 @@ static bool trans_XXSETACCZ(DisasContext *ctx, arg_X_a *a)
return true;
}
static bool do_ger(DisasContext *ctx, arg_MMIRR_XX3 *a,
void (*helper)(TCGv_env, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32))
{
uint32_t mask;
TCGv_ptr xt, xa, xb;
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
REQUIRE_VSX(ctx);
if (unlikely((a->xa / 4 == a->xt) || (a->xb / 4 == a->xt))) {
gen_invalid(ctx);
return true;
}
xt = gen_acc_ptr(a->xt);
xa = gen_vsr_ptr(a->xa);
xb = gen_vsr_ptr(a->xb);
mask = ger_pack_masks(a->pmsk, a->ymsk, a->xmsk);
helper(cpu_env, xa, xb, xt, tcg_constant_i32(mask));
tcg_temp_free_ptr(xt);
tcg_temp_free_ptr(xa);
tcg_temp_free_ptr(xb);
return true;
}
TRANS(XVI4GER8, do_ger, gen_helper_XVI4GER8)
TRANS(XVI4GER8PP, do_ger, gen_helper_XVI4GER8PP)
TRANS(XVI8GER4, do_ger, gen_helper_XVI8GER4)
TRANS(XVI8GER4PP, do_ger, gen_helper_XVI8GER4PP)
TRANS(XVI8GER4SPP, do_ger, gen_helper_XVI8GER4SPP)
TRANS(XVI16GER2, do_ger, gen_helper_XVI16GER2)
TRANS(XVI16GER2PP, do_ger, gen_helper_XVI16GER2PP)
TRANS(XVI16GER2S, do_ger, gen_helper_XVI16GER2S)
TRANS(XVI16GER2SPP, do_ger, gen_helper_XVI16GER2SPP)
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM