target/ppc: Implement Vector Insert Word from GPR using Immediate insns
Implements the following PowerISA v3.1 instructions: vinsw: Vector Insert Word from GPR using immediate-specified index vinsd: Vector Insert Doubleword from GPR using immediate-specified index Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211104123719.323713-7-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -44,6 +44,9 @@
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&VX vrt vra vrb
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@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
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&VX_uim4 vrt uim vrb
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@VX_uim4 ...... vrt:5 . uim:4 vrb:5 ........... &VX_uim4
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&X rt ra rb
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@X ...... rt:5 ra:5 rb:5 .......... . &X
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@ -353,5 +356,8 @@ VINSWRX 000100 ..... ..... ..... 01110001111 @VX
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VINSDLX 000100 ..... ..... ..... 01011001111 @VX
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VINSDRX 000100 ..... ..... ..... 01111001111 @VX
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VINSW 000100 ..... - .... ..... 00011001111 @VX_uim4
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VINSD 000100 ..... - .... ..... 00111001111 @VX_uim4
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VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
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VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
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@ -1278,6 +1278,40 @@ static bool do_vinsx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
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return ok;
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}
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static bool do_vins_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
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void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
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{
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bool ok;
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TCGv_i64 val;
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REQUIRE_INSNS_FLAGS2(ctx, ISA310);
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REQUIRE_VECTOR(ctx);
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if (a->uim > (16 - size)) {
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/*
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* PowerISA v3.1 says that the resulting value is undefined in this
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* case, so just log a guest error and leave VRT unchanged. The
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* real hardware would do a partial insert, e.g. if VRT is zeroed and
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* RB is 0x12345678, executing "vinsw VRT,RB,14" results in
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* VRT = 0x0000...00001234, but we don't bother to reproduce this
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* behavior as software shouldn't rely on it.
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*/
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VINS* at"
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" 0x" TARGET_FMT_lx ", UIM = %d > %d\n", ctx->cia, a->uim,
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16 - size);
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return true;
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}
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val = tcg_temp_new_i64();
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tcg_gen_extu_tl_i64(val, cpu_gpr[a->vrb]);
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ok = do_vinsx(ctx, a->vrt, size, false, tcg_constant_tl(a->uim), val,
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gen_helper);
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tcg_temp_free_i64(val);
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return ok;
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}
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TRANS(VINSBLX, do_vinsx_VX, 1, false, gen_helper_VINSBLX)
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TRANS(VINSHLX, do_vinsx_VX, 2, false, gen_helper_VINSHLX)
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TRANS(VINSWLX, do_vinsx_VX, 4, false, gen_helper_VINSWLX)
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@ -1288,6 +1322,9 @@ TRANS(VINSHRX, do_vinsx_VX, 2, true, gen_helper_VINSHLX)
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TRANS(VINSWRX, do_vinsx_VX, 4, true, gen_helper_VINSWLX)
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TRANS(VINSDRX, do_vinsx_VX, 8, true, gen_helper_VINSDLX)
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TRANS(VINSW, do_vins_VX_uim4, 4, gen_helper_VINSWLX)
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TRANS(VINSD, do_vins_VX_uim4, 8, gen_helper_VINSDLX)
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static void gen_vsldoi(DisasContext *ctx)
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{
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TCGv_ptr ra, rb, rd;
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