target/ppc: Implement Vector Mask Move insns
Implement the following PowerISA v3.1 instructions: mtvsrbm: Move to VSR Byte Mask mtvsrhm: Move to VSR Halfword Mask mtvsrwm: Move to VSR Word Mask mtvsrdm: Move to VSR Doubleword Mask mtvsrqm: Move to VSR Quadword Mask mtvsrbmi: Move to VSR Byte Mask Immediate Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211203194229.746275-4-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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@ -40,6 +40,10 @@
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%ds_rtp 22:4 !function=times_2
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@DS_rtp ...... ....0 ra:5 .............. .. &D rt=%ds_rtp si=%ds_si
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&DX_b vrt b
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%dx_b 6:10 16:5 0:1
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@DX_b ...... vrt:5 ..... .......... ..... . &DX_b b=%dx_b
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&DX rt d
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%dx_d 6:s10 16:5 0:1
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@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
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@ -413,6 +417,13 @@ VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
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## Vector Mask Manipulation Instructions
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MTVSRBM 000100 ..... 10000 ..... 11001000010 @VX_tb
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MTVSRHM 000100 ..... 10001 ..... 11001000010 @VX_tb
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MTVSRWM 000100 ..... 10010 ..... 11001000010 @VX_tb
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MTVSRDM 000100 ..... 10011 ..... 11001000010 @VX_tb
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MTVSRQM 000100 ..... 10100 ..... 11001000010 @VX_tb
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MTVSRBMI 000100 ..... ..... .......... 01010 . @DX_b
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VEXPANDBM 000100 ..... 00000 ..... 11001000010 @VX_tb
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VEXPANDHM 000100 ..... 00001 ..... 11001000010 @VX_tb
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VEXPANDWM 000100 ..... 00010 ..... 11001000010 @VX_tb
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@ -1607,6 +1607,121 @@ static bool trans_VEXTRACTQM(DisasContext *ctx, arg_VX_tb *a)
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return true;
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}
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static bool do_mtvsrm(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
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{
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const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece;
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uint64_t c;
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int i, j;
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TCGv_i64 hi, lo, t0, t1;
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REQUIRE_INSNS_FLAGS2(ctx, ISA310);
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REQUIRE_VECTOR(ctx);
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hi = tcg_temp_new_i64();
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lo = tcg_temp_new_i64();
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t0 = tcg_temp_new_i64();
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t1 = tcg_temp_new_i64();
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tcg_gen_extu_tl_i64(t0, cpu_gpr[a->vrb]);
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tcg_gen_extract_i64(hi, t0, elem_count_half, elem_count_half);
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tcg_gen_extract_i64(lo, t0, 0, elem_count_half);
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/*
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* Spread the bits into their respective elements.
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* E.g. for bytes:
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* 00000000000000000000000000000000000000000000000000000000abcdefgh
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* << 32 - 4
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* 0000000000000000000000000000abcdefgh0000000000000000000000000000
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* |
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* 0000000000000000000000000000abcdefgh00000000000000000000abcdefgh
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* << 16 - 2
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* 00000000000000abcdefgh00000000000000000000abcdefgh00000000000000
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* |
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* 00000000000000abcdefgh000000abcdefgh000000abcdefgh000000abcdefgh
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* << 8 - 1
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* 0000000abcdefgh000000abcdefgh000000abcdefgh000000abcdefgh0000000
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* |
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* 0000000abcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgh
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* & dup(1)
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* 0000000a0000000b0000000c0000000d0000000e0000000f0000000g0000000h
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* * 0xff
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* aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh
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*/
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for (i = elem_count_half / 2, j = 32; i > 0; i >>= 1, j >>= 1) {
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tcg_gen_shli_i64(t0, hi, j - i);
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tcg_gen_shli_i64(t1, lo, j - i);
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tcg_gen_or_i64(hi, hi, t0);
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tcg_gen_or_i64(lo, lo, t1);
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}
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c = dup_const(vece, 1);
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tcg_gen_andi_i64(hi, hi, c);
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tcg_gen_andi_i64(lo, lo, c);
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c = MAKE_64BIT_MASK(0, elem_width);
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tcg_gen_muli_i64(hi, hi, c);
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tcg_gen_muli_i64(lo, lo, c);
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set_avr64(a->vrt, lo, false);
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set_avr64(a->vrt, hi, true);
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tcg_temp_free_i64(hi);
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tcg_temp_free_i64(lo);
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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return true;
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}
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TRANS(MTVSRBM, do_mtvsrm, MO_8)
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TRANS(MTVSRHM, do_mtvsrm, MO_16)
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TRANS(MTVSRWM, do_mtvsrm, MO_32)
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TRANS(MTVSRDM, do_mtvsrm, MO_64)
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static bool trans_MTVSRQM(DisasContext *ctx, arg_VX_tb *a)
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{
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TCGv_i64 tmp;
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REQUIRE_INSNS_FLAGS2(ctx, ISA310);
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REQUIRE_VECTOR(ctx);
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tmp = tcg_temp_new_i64();
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tcg_gen_ext_tl_i64(tmp, cpu_gpr[a->vrb]);
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tcg_gen_sextract_i64(tmp, tmp, 0, 1);
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set_avr64(a->vrt, tmp, false);
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set_avr64(a->vrt, tmp, true);
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tcg_temp_free_i64(tmp);
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return true;
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}
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static bool trans_MTVSRBMI(DisasContext *ctx, arg_DX_b *a)
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{
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const uint64_t mask = dup_const(MO_8, 1);
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uint64_t hi, lo;
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REQUIRE_INSNS_FLAGS2(ctx, ISA310);
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REQUIRE_VECTOR(ctx);
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hi = extract16(a->b, 8, 8);
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lo = extract16(a->b, 0, 8);
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for (int i = 4, j = 32; i > 0; i >>= 1, j >>= 1) {
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hi |= hi << (j - i);
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lo |= lo << (j - i);
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}
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hi = (hi & mask) * 0xFF;
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lo = (lo & mask) * 0xFF;
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set_avr64(a->vrt, tcg_constant_i64(hi), true);
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set_avr64(a->vrt, tcg_constant_i64(lo), false);
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return true;
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}
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#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
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static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
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{ \
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