the arguments are changed so the address is first and the ASI second so we
can have the address in %o0:%o1 and not worry about unused registers.
Also a bit of copyright cleanup.
non-cached. XXX clean this up by looking at the "non-cacheable" bit of
the full physical address.
avoid having 'nbuf' change between calls to `mdallocsys()' by setting it
in mdallocsys() like the MI allocsys() does. XXX fix this too!
fix some printf lossage.
update for probeget() changes -- though bus_space_probe() appears to be
unused on the sparc64.
device declaration, we don't want it). pull in psycho, pci,
ata and pciide code. clock, eeprom and power attach at sbus
*and* ebus now (clock as `eeprom' works). add `lpt at ebus',
wd major number, and other misc. commented devices.
(`SUNW,sabre') for now, and it doesn't really quite work there yet anyway.
the bus space/dma code is cloned from the sbus driver. the IOMMU code also
is cloned from the sbus code, but separated out into iommu.c so that we can
share it with the sbus driver. hopefully, much of the bus space/dma code
can also be re-shared with the sbus driver and the ebus driver but for now
these copies will do.
support for the real UltraSPARC PCI (`SUNW,psycho') is unwritten, though
most of this code is shared with it.
we can probe PCI config space and try to configue devices, but interrupts
don't work yet...
the bus space/dma code is cloned from the PCI code to do the same thing
which itself was cloned from the sbus bus space/dma code. the bus dma
code is non-functional at this point.
bytes/sector correctly.
Submitted by Detlev Würkner in PR 7653.
Non-trivial merge with the 1.30 change (handle old AmigaDOS fs partitions
with simulated sectorsperblock > 1) by myself, so don't blame Detlev if it
doesn't work (but I checked!).
XXX We still need changes to the file systems to handle this fully.
at levels 5 (sound) and 6 (via1) on the Q700.
Raise splhigh when reading and writing registers. It's ugly, but it's
possible that we could get an interrupt from a higher-level source,
causing a re-read of a memory location.
This is not good when, e.g., we are reading the interrupt register.
Ideally, we would just raise splhigh() in ncr53c9x_readregs(), but
that's m.i. code, and it may be expensive on other architectures.
I've fixed most (not all) m68k FPE bugs that give bogus
calculation results, esp. fsqrt instruction. Also, the internal FP
representation has been reduced from 115-bit mantissa to 67-bit
mantissa which reduced the required mantissa operation roughly by one
fourth. I've done an extensive (though not exhaustive - it's
impossible!) test on the internal routines by feeding them randomly
generated FP numbers, and found that the new code is more precise than
MC68040 FPU (it seems to have a rounding bug).
[ Only change was to keep fpu_calcea.c's name instead of renaming to
fpu_ea.c in Ken's patch. --akb ]
instead of ldstub, but since we aren't doing n-way locking it makes little
difference. N.B. Need to decide what to do with sparc64/sparc64/asm.h which
has name conflicts with sparc64/include/asm.h. So far most of
sparc64/sparc64/asm.h has been moved to ctlreg.h.
TLBUpdate() routine is used for dual purposes. In TLBmod case, just ok
to call 'tlbwi' (as designed). Result in saving of extraneous execution
path. MIPS1 only this moment.
has PAGEABLE and INTRSAFE flags. PAGEABLE now really means "pageable",
not "allocate vm_map_entry's from non-static pool", so update all map
creations to reflect that. INTRSAFE maps are maps that are used in
interrupt context (e.g. kmem_map, mb_map), and thus use the static
map entry pool (XXX as does kernel_map, for now). This will eventually
change now these maps are locked, as well.
managed pages, into KVA space. Since the pages are managed, we should
use pmap_enter(), not pmap_kenter_pa().
Also, when entering the mappings, enter with an access_type of
VM_PROT_READ | VM_PROT_WRITE. We do this for a couple of reasons:
(1) On systems that have H/W mod/ref attributes, the hardware
may not be able to track mod/ref done by a bus master.
(2) On systems that have to do mod/ref emulation, this prevents
a mod/ref page fault from potentially happening while in an
interrupt context, which can be problematic.
This latter change is fairly important if we ever want to be able to
transfer DMA-safe memory pages to anonymous memory objects; we will need
to know that the pages are modified, or else data could be lost!
Note that while the pages are unowned (i.e. "just DMA-safe memory pages"),
they won't consume any swap resources, as the mappings are wired, and
the pages aren't on the active or inactive queues.
routines now reside in locore.S. No functional difference is expected.
- Replace abused splx() abuse with _splset() to change MIPS processor
interrupt mask bit. 'mips/trap.c' side will be fixed soon.
context, so we must block interrupts which may cause memory allocation
before asserting the kernel pmap's lock. Put this all in PMAP_LOCK()
and PMAP_UNLOCK() macros to make it easier.
- Make it compile again, with BPF.
- Don't subtract the Ethernet header length from the total packet length.
- Copy the alignment fix from sys/dev/ic/i82586.c (though the m68k shouldn't
really be affected).
(correct name, vax?) replacing mips1_TLBFlushAddr and mips1_TLBUpdate,
respectively. New codes always use current ASID holded in EntryHi
register. In most occations, the register already contains a necessary
value before (re-)written, ugh. 'sva | asid' ops for their arguments are
now verbose, to be removed when MIPS3 side changes are done.
end of the mappable kernel virtual address space. Previously, it would
get called more often than necessary, because the caller only new what
was requested.
Also, export uvm_maxkaddr so that uvm_pageboot_alloc() can grow the
kernel pmap if necessary, as well. Note that pmap_growkernel() must
now be able to handle being called before pmap_init().
'pm_asid' member of 'pmap' structure is assigned a new value after
uvmspace_alloc() provides afresh pmap.
- ASID generation number 0 is not a reserved value anymore.
processor is one of processors with no 'referenced bit' nor 'modified bit'
processor machinary. Those functions are implemented combining two
hardware bits, 'dirty bit' and 'valid bit', with TLBmod exception handler.
per process user spaces, replacing mips1_TBLFlush(). This reserves
kernel space TLB entries when TLBPID generation number about to wrap.
- Correct comments a bit, nuke unused routines.
directly, call the function pointer (*if_input)(ifp, m). The input routine
expects the packet header to be at the head of the packet, and will adjust
as necessary. Privatize the layer 2 input and output routines, allowing
*_ifattach() to set them up as appropriate.
initialization code.
- Abandon mips_init_proc0() and do the 4 lines straightly in MD mach_init().
- Restore a block of code accidentally lost in prevous commit.
- Change the term 'tlbpid' to a MIPS3 nomenclature 'asid'.
- Hide PTE size exposures by symbolic names in locore.S
interface border, so that other serial interfaces can be attached to the
ms/kbd. zero functional changes and mostly involves moving code around
a bit. tested on the SS2.
this is necessary to attach the PCI ultrasparc keyboard/mouse drivers.
firmware sets the "stdin" property of /chosen to be a pseudo-hid (yes, they
even spell it incorrectly) that merges all keyboard input into one stream,
so we can't find the USB controller we're attached to. Instead, just give
it to the first USB keyboard found during autoconfiguration. So that we
have SOMETHING available early on, use OpenFirmware i/o to do keyboard
input to the console wsdisplay until the USB code attaches the keyboard.
From Jason Thorpe <thorpej@nas.nasa.gov>
the child inherits the stack pointer from the parent (traditional
behavior). Like the signal stack, the stack area is secified as
a low address and a size; machine-dependent code accounts for stack
direction.
This is required for clone(2).
netbooting on machines that can't netboot a fullsize kernel.
This is only a stop-gap solution until the pmax gets a working two stage
netboot, and is not enabled by default.
which set the LDT and share VM space (e.g. new versions of WINE) expect
the LDT to be logically coupled to the address space. Use the new pmap_fork()
interface to copy non-shared user-set LDTs when the address space is forked.
unaligned access handler and clean it up some. Add support for emulating
the BWX instructions (ld{b,w}u, st{b,w}, sext{b,w}), which user software
can expect to be emulated. (Thanks, Alpha Architecture!)
register names was confusing, and could not _be_ correct in some cases.
Also, add a couple of 'generic' instruction formats which should be used
when decoding instructions before the specific format is known.
so that devices which must allocate DMA memory in this range (e.g.
PixelStamp graphics boards) have a better chance of doing so, without
an awful hack.
_splraise, _spllower, _splset, _splget, _setsoftintr, _clrsoftintr, _splnone.
They manipulate MIPS processor's 8 interrupt sources and are used
as building blocks for NetBSD spl(9) kernel interface. Note that
MIPS processor doesn't enforce inclusive 'interrupt levels' found
in other processors, then the hierarchal nature of IPL must be
implemented by composing MIPS processor interrupt masks appropriately.
With the simplest target port in which small number of devices are
independently assigned with 6 external interrupt signal lines,
spl(9) kernel interface will be implemented with #define's of
processor interrupt controls mentioned above. In more general
cases, in which target computers have many devices and 'system
registers' indicating pending interrupt sources at any moment,
spl(9) will be implemented with more complex machinary manipulating
processor interrupts and system registers in target port dependent
ways.
- Nuke unused code and reorder locore definitions. XXX Following
routines will be replaced with C language version; setrunqueue,
remrunqueue, switchfpregs, savefpregs, MachFPInterrupt.
the console. New algorithm:
* if stdin == keyboard, and parent of keyboard == adb, use ADB.
* else, must be a USB keyboard. Search backwards though the parents
until the USB controller is located. Determine its location in the PCI
domain, and which type of controller it is, and tell that controller that
it has the console input device. The USB code will then attach the first
USB keyboard as the console input device during autoconfiguration.
The iMac and Blue and White G3 consoles are fully functional now!
