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PCI driver for the UltraSPARC. this only works on the Ultra5/10 machines 

(`SUNW,sabre') for now, and it doesn't really quite work there yet anyway.
the bus space/dma code is cloned from the sbus driver.  the IOMMU code also
is cloned from the sbus code, but separated out into iommu.c so that we can
share it with the sbus driver.  hopefully, much of the bus space/dma code
can also be re-shared with the sbus driver and the ebus driver but for now
these copies will do.

support for the real UltraSPARC PCI (`SUNW,psycho') is unwritten, though
most of this code is shared with it.

we can probe PCI config space and try to configue devices, but interrupts
don't work yet...
This commit is contained in:
mrg 1999-06-04 13:42:14 +00:00
parent 36237341af
commit 03adf4aad1
8 changed files with 2694 additions and 0 deletions
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417
sys/arch/sparc64/dev/pci_machdep.c Normal file
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/* $NetBSD: pci_machdep.c,v 1.1 1999/06/04 13:42:15 mrg Exp $ */
/*
* Copyright (c) 1999 Matthew R. Green
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* functions expected by the MI PCI code.
*/
#undef DEBUG
#define DEBUG
#ifdef DEBUG
#define SPDB_CONF 0x01
#define SPDB_INTR 0x04
#define SPDB_INTMAP 0x08
#define SPDB_INTFIX 0x10
int sparc_pci_debug = 0x4;
#define DPRINTF(l, s) do { if (sparc_pci_debug & l) printf s; } while (0)
#else
#define DPRINTF(l, s)
#endif
#include <sys/types.h>
#include <sys/param.h>
#include <sys/time.h>
#include <sys/systm.h>
#include <sys/errno.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <vm/vm.h>
#include <vm/vm_kern.h>
#define _SPARC_BUS_DMA_PRIVATE
#include <machine/bus.h>
#include <machine/autoconf.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <sparc64/dev/iommureg.h>
#include <sparc64/dev/iommuvar.h>
#include <sparc64/dev/psychoreg.h>
#include <sparc64/dev/psychovar.h>
/* this is a base to be copied */
struct sparc_pci_chipset _sparc_pci_chipset = {
NULL,
};
/*
* functions provided to the MI code.
*/
void
pci_attach_hook(parent, self, pba)
struct device *parent;
struct device *self;
struct pcibus_attach_args *pba;
{
pci_chipset_tag_t pc = pba->pba_pc;
struct psycho_pbm *pp = pc->cookie;
struct psycho_registers *pr;
pcitag_t tag;
char *name, *devtype;
u_int32_t hi, mid, lo, intr;
int node, i, n, *ip, *ap;
u_int bus, dev, fn;
DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\npci_attach_hook:"));
/*
* ok, here we look in the OFW for each PCI device and fix it's
* "interrupt line" register to be useful.
*/
for (node = firstchild(pc->node); node; node = nextsibling(node)) {
pr = NULL;
ip = ap = NULL;
/*
* ok, for each child we get the "interrupts" property,
* which contains a value to match against later.
* XXX deal with multiple "interrupts" values XXX.
* then we get the "assigned-addresses" property which
* contains, in the first entry, the PCI bus, device and
* function associated with this node, which we use to
* generate a pcitag_t to use pci_conf_read() and
* pci_conf_write(). next, we get the 'reg" property
* which is structured like the following:
* u_int32_t phys_hi;
* u_int32_t phys_mid;
* u_int32_t phys_lo;
* u_int32_t size_hi;
* u_int32_t size_lo;
* we mask these values with the "interrupt-map-mask"
* property of our parent and them compare with each
* entry in the "interrupt-map" property (also of our
* parent) which is structred like the following:
* u_int32_t phys_hi;
* u_int32_t phys_mid;
* u_int32_t phys_lo;
* u_int32_t intr;
* int32_t child_node;
* u_int32_t child_intr;
* if there is an exact match with phys_hi, phys_mid,
* phys_lo and the interrupt, we have a match and we
* know that this interrupt's value is really the
* child_intr of the interrupt map entry. we put this
* into the PCI interrupt line register so that when
* the driver for this node wants to attach, we know
* it's INO already.
*/
name = getpropstring(node, "name");
DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\n\tnode %x name `%s'", node, name));
devtype = getpropstring(node, "device_type");
DPRINTF((SPDB_INTFIX|SPDB_INTMAP), (" devtype `%s':", devtype));
/* ignore PCI bridges, we'll get them later */
if (strcmp(devtype, "pci") == 0)
continue;
/* if there isn't any "interrupts" then we don't care to fix it */
ip = NULL;
if (getprop(node, "interrupts", sizeof(int), &n, (void **)&ip))
continue;
DPRINTF(SPDB_INTFIX, (" got interrupts"));
/* and if there isn't an "assigned-addresses" we can't find b/d/f */
if (getprop(node, "assigned-addresses", sizeof(int), &n,
(void **)&ap))
goto clean1;
DPRINTF(SPDB_INTFIX, (" got assigned-addresses"));
/* ok, and now the "reg" property, so we know what we're talking about. */
if (getprop(node, "reg", sizeof(*pr), &n,
(void **)&pr))
goto clean2;
DPRINTF(SPDB_INTFIX, (" got reg"));
bus = (ap[0] >> 16) & 0xff;
dev = (ap[0] >> 11) & 0x1f;
fn = (ap[0] >> 8) & 0x7;
DPRINTF(SPDB_INTFIX, ("; bus %u dev %u fn %u", bus, dev, fn));
tag = pci_make_tag(pc, bus, dev, fn);
DPRINTF(SPDB_INTFIX, ("; tag %08x\n\t; reg: hi %x mid %x lo %x intr %x", tag, pr->phys_hi, pr->phys_mid, pr->phys_lo, *ip));
DPRINTF(SPDB_INTFIX, ("\n\t; intmapmask: hi %x mid %x lo %x intr %x", pp->pp_intmapmask.phys_hi, pp->pp_intmapmask.phys_mid,
pp->pp_intmapmask.phys_lo, pp->pp_intmapmask.intr));
hi = pr->phys_hi & pp->pp_intmapmask.phys_hi;
mid = pr->phys_mid & pp->pp_intmapmask.phys_mid;
lo = pr->phys_lo & pp->pp_intmapmask.phys_lo;
intr = *ip & pp->pp_intmapmask.intr;
DPRINTF(SPDB_INTFIX, ("\n\t; after: hi %x mid %x lo %x intr %x", hi, mid, lo, intr));
for (i = 0; i < pp->pp_nintmap; i++) {
DPRINTF(SPDB_INTFIX, ("\n\t\tmatching for: hi %x mid %x lo %x intr %x", pp->pp_intmap[i].phys_hi, pp->pp_intmap[i].phys_mid,
pp->pp_intmap[i].phys_lo, pp->pp_intmap[i].intr));
if (pp->pp_intmap[i].phys_hi != hi ||
pp->pp_intmap[i].phys_mid != mid ||
pp->pp_intmap[i].phys_lo != lo ||
pp->pp_intmap[i].intr != intr)
continue;
DPRINTF(SPDB_INTFIX, ("... BINGO! ..."));
/*
* OK! we found match. pull out the old interrupt
* register, patch in the new value, and put it back.
*/
intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
DPRINTF(SPDB_INTFIX, ("\n\t ; read %x from intreg", intr));
intr = (intr & ~PCI_INTERRUPT_LINE_MASK) |
(pp->pp_intmap[i].child_intr & PCI_INTERRUPT_LINE_MASK);
DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\n\t ; gonna write %x to intreg", intr));
pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr);
DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\n\t ; reread %x from intreg", intr));
break;
}
/* clean up */
if (pr)
free(pr, M_DEVBUF);
clean2:
if (ap)
free(ap, M_DEVBUF);
clean1:
if (ip)
free(ip, M_DEVBUF);
}
DPRINTF(SPDB_INTFIX, ("\n"));
}
int
pci_bus_maxdevs(pc, busno)
pci_chipset_tag_t pc;
int busno;
{
return 32;
}
pcitag_t
pci_make_tag(pc, b, d, f)
pci_chipset_tag_t pc;
int b;
int d;
int f;
{
return (b << 16) | (d << 11) | (f << 8);
}
static int confaddr_ok __P((struct psycho_softc *, pcitag_t));
/*
* this function is a large hack. ideally, we should also trap accesses
* properly, but we have to avoid letting anything read various parts
* of bus 0 dev 0 fn 0 space or the machine may hang. so, even if we
* do properly implement PCI config access trap handling, this function
* should remain in place Just In Case.
*/
static int
confaddr_ok(sc, tag)
struct psycho_softc *sc;
pcitag_t tag;
{
int bus, dev, fn;
bus = (tag >> 16) & 0xff;
dev = (tag >> 11) & 0x1f;
fn = (tag >> 8) & 0x7;
if (sc->sc_mode == PSYCHO_MODE_SABRE) {
/*
* bus 0 is only ok for dev 0 fn 0, dev 1 fn 0 and dev fn 1.
*/
if (bus == 0 &&
((dev == 0 && fn > 0) ||
(dev == 1 && fn > 1) ||
(dev > 1))) {
DPRINTF(SPDB_CONF, (" confaddr_ok: rejecting bus %d dev %d fn %d -", bus, dev, fn));
return (0);
}
} else if (sc->sc_mode == PSYCHO_MODE_PSYCHO_A ||
sc->sc_mode == PSYCHO_MODE_PSYCHO_B) {
/*
* make sure we are reading our own bus
*/
/* XXX??? */
}
return (1);
}
/* assume we are mapped little-endian/side-effect */
pcireg_t
pci_conf_read(pc, tag, reg)
pci_chipset_tag_t pc;
pcitag_t tag;
int reg;
{
struct psycho_pbm *pp = pc->cookie;
struct psycho_softc *sc = pp->pp_sc;
pcireg_t val;
DPRINTF(SPDB_CONF, ("pci_conf_read: tag %lx; reg %x; ", (long)tag, reg));
DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x) ...",
bus_type_asi[sc->sc_configtag->type],
sc->sc_configaddr + tag + reg, (int)tag + reg));
if (confaddr_ok(sc, tag) == 0) {
val = (pcireg_t)~0;
} else {
membar_sync();
val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr,
tag + reg);
membar_sync();
}
DPRINTF(SPDB_CONF, (" returning %08x\n", (u_int)val));
return (val);
}
void
pci_conf_write(pc, tag, reg, data)
pci_chipset_tag_t pc;
pcitag_t tag;
int reg;
pcireg_t data;
{
struct psycho_pbm *pp = pc->cookie;
struct psycho_softc *sc = pp->pp_sc;
DPRINTF(SPDB_CONF, ("pci_conf_write: tag %ld; reg %d; data %d; ", (long)tag, reg, (int)data));
DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n",
bus_type_asi[sc->sc_configtag->type],
sc->sc_configaddr + tag + reg, (int)tag + reg));
if (confaddr_ok(sc, tag) == 0)
panic("pci_conf_write: bad addr");
membar_sync();
bus_space_write_4(sc->sc_configtag, sc->sc_configaddr, tag + reg, data);
membar_sync();
}
/*
* interrupt mapping foo.
*/
int
pci_intr_map(pc, tag, pin, line, ihp)
pci_chipset_tag_t pc;
pcitag_t tag;
int pin;
int line;
pci_intr_handle_t *ihp;
{
struct psycho_pbm *pp = pc->cookie;
int rv;
DPRINTF(SPDB_INTR, ("pci_intr_map: tag %x; pin %d; line %d", (u_int)tag, pin, line));
if (line == 255 || pin == 0) {
*ihp = -1;
rv = 1;
goto out;
}
if (pin > 4)
panic("pci_intr_map: pin > 4");
rv = psycho_intr_map(tag, pin, line, ihp);
out:
DPRINTF(SPDB_INTR, ("; handle = %d; returning %d\n", (int)*ihp, rv));
return (rv);
}
const char *
pci_intr_string(pc, ih)
pci_chipset_tag_t pc;
pci_intr_handle_t ih;
{
static char str[16];
DPRINTF(SPDB_INTR, ("pci_intr_string: ih %u", ih));
if (ih < 0 || ih > 0x32) {
printf("\n"); /* i'm *so* beautiful */
panic("pci_intr_string: bogus handle\n");
}
sprintf(str, "vector %u", ih);
DPRINTF(SPDB_INTR, ("; returning %s\n", str));
return (str);
}
void *
pci_intr_establish(pc, ih, level, func, arg)
pci_chipset_tag_t pc;
pci_intr_handle_t ih;
int level;
int (*func) __P((void *));
void *arg;
{
void *cookie;
struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie;
DPRINTF(SPDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level));
cookie = bus_intr_establish(pp->pp_memt, ih, 0, func, arg);
DPRINTF(SPDB_INTR, ("; returning handle %p\n", cookie));
return (cookie);
}
void
pci_intr_disestablish(pc, cookie)
pci_chipset_tag_t pc;
void *cookie;
{
DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie));
/* XXX */
panic("can't disestablish PCI interrupts yet");
}

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sys/arch/sparc64/dev/psycho.c Normal file
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/* $NetBSD: psycho.c,v 1.1 1999/06/04 13:42:14 mrg Exp $ */
/*
* Copyright (c) 1999 Matthew R. Green
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* PCI support for UltraSPARC `psycho'
*/
#undef DEBUG
#define DEBUG
#ifdef DEBUG
#define PDB_PROM 0x1
#define PDB_IOMMU 0x2
int psycho_debug = 0;
#define DPRINTF(l, s) do { if (psycho_debug & l) printf s; } while (0)
#else
#define DPRINTF(l, s)
#endif
#include <sys/param.h>
#include <sys/extent.h>
#include <sys/time.h>
#include <sys/systm.h>
#include <sys/errno.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <vm/vm.h>
#include <vm/vm_kern.h>
#define _SPARC_BUS_DMA_PRIVATE
#include <machine/bus.h>
#include <machine/autoconf.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <sparc64/dev/iommureg.h>
#include <sparc64/dev/iommuvar.h>
#include <sparc64/dev/psychoreg.h>
#include <sparc64/dev/psychovar.h>
static pci_chipset_tag_t psycho_alloc_chipset __P((struct psycho_pbm *, int,
pci_chipset_tag_t));
static void psycho_get_bus_range __P((int, int *));
static void psycho_get_ranges __P((int, struct psycho_ranges **, int *));
static void psycho_get_registers __P((int, struct psycho_registers **, int *));
static void psycho_get_intmap __P((int, struct psycho_interrupt_map **, int *));
static void psycho_get_intmapmask __P((int, struct psycho_interrupt_map_mask *));
/* IOMMU support */
static void psycho_iommu_init __P((struct psycho_softc *));
extern struct sparc_pci_chipset _sparc_pci_chipset;
/*
* autoconfiguration
*/
static int psycho_match __P((struct device *, struct cfdata *, void *));
static void psycho_attach __P((struct device *, struct device *, void *));
static int psycho_print __P((void *aux, const char *p));
static void sabre_init __P((struct psycho_softc *, struct pcibus_attach_args *));
static void psycho_init __P((struct psycho_softc *, struct pcibus_attach_args *));
struct cfattach psycho_ca = {
sizeof(struct psycho_softc), psycho_match, psycho_attach
};
/*
* "sabre" is the UltraSPARC IIi onboard PCI interface, normally connected to
* an APB (advanced PCI bridge), which was designed specifically for the IIi.
* the APB appears as two "simba"'s underneath the sabre. real devices
* typically appear on the "simba"'s only.
*
* a pair of "psycho"s sit on the mainbus and have real devices attached to
* them. they implemented in the U2P (UPA to PCI). these two devices share
* register space and as such need to be configured together, even though the
* autoconfiguration will attach them separately.
*
* each of these appears as two usable PCI busses, though the sabre itself
* takes pci0 in this case, leaving real devices on pci1 and pci2. there can
* be multiple pairs of psycho's, however, in multi-board machines.
*/
#define ROM_PCI_NAME "pci"
#define ROM_SABRE_MODEL "SUNW,sabre"
#define ROM_SIMBA_MODEL "SUNW,simba"
#define ROM_PSYCHO_MODEL "SUNW,psycho"
static int
psycho_match(parent, match, aux)
struct device *parent;
struct cfdata *match;
void *aux;
{
struct mainbus_attach_args *ma = aux;
char *model = getpropstring(ma->ma_node, "model");
/* match on a name of "pci" and a sabre or a psycho */
if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0 &&
(strcmp(model, ROM_SABRE_MODEL) == 0 ||
strcmp(model, ROM_PSYCHO_MODEL) == 0))
return (1);
return (0);
}
static void
psycho_attach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct psycho_softc *sc = (struct psycho_softc *)self;
struct pcibus_attach_args pba;
struct mainbus_attach_args *ma = aux;
bus_space_handle_t bh;
char *model = getpropstring(ma->ma_node, "model");
printf("\n");
sc->sc_node = ma->ma_node;
sc->sc_bustag = ma->ma_bustag;
sc->sc_dmatag = ma->ma_dmatag;
/*
* pull in all the information about the psycho as we can.
*/
/*
* XXX use the prom address for the psycho registers? we do so far.
*/
sc->sc_regs = (struct psychoreg *)(u_long)ma->ma_address[0];
sc->sc_basepaddr = (paddr_t)ma->ma_reg[0].ur_paddr;
/*
* call the model-specific initialisation routine.
*/
if (strcmp(model, ROM_SABRE_MODEL) == 0)
sabre_init(sc, &pba);
else if (strcmp(model, ROM_PSYCHO_MODEL) == 0)
psycho_init(sc, &pba);
#ifdef DIAGNOSTIC
else
panic("psycho_attach: unknown model %s?", model);
#endif
/*
* get us a config space tag, and punch in the physical address
* of the PCI configuration space. note that we use unmapped
* access to PCI configuration space, relying on the bus space
* macros to provide the proper ASI based on the bus tag.
*/
sc->sc_configtag = psycho_alloc_config_tag(sc->sc_simba_a);
#if 0
sc->sc_configaddr = (paddr_t)sc->sc_basepaddr + 0x01000000;
#else
if (bus_space_map2(ma->ma_bustag,
PCI_CONFIG_BUS_SPACE,
sc->sc_basepaddr + 0x01000000,
0x0100000,
0,
0,
&bh))
panic("could not map sabre PCI configuration space");
sc->sc_configaddr = (paddr_t)bh;
#endif
/*
* attach the pci.. note we pass PCI A tags, etc., for the sabre here.
*/
pba.pba_busname = "pci";
pba.pba_flags = sc->sc_psycho_this->pp_flags;
pba.pba_dmat = sc->sc_psycho_this->pp_dmat;
pba.pba_iot = sc->sc_psycho_this->pp_iot;
pba.pba_memt = sc->sc_psycho_this->pp_memt;
config_found(self, &pba, psycho_print);
}
static int
psycho_print(aux, p)
void *aux;
const char *p;
{
if (p == NULL)
return (UNCONF);
return (QUIET);
}
/*
* SUNW,sabre initialisation ..
* - get the sabre's ranges. this are used for both simba's.
* - find the two SUNW,simba's underneath (a and b)
* - work out which simba is which via the bus-range property
* - get each simba's interrupt-map and interrupt-map-mask.
* - turn on the iommu
*/
static void
sabre_init(sc, pba)
struct psycho_softc *sc;
struct pcibus_attach_args *pba;
{
struct psycho_pbm *pp;
u_int64_t csr;
int node;
int sabre_br[2], simba_br[2];
/* who? said a voice, incredulous */
sc->sc_mode = PSYCHO_MODE_SABRE;
printf("sabre: ");
/* setup the PCI control register; there is only one for the sabre */
csr = bus_space_read_8(sc->sc_bustag, &sc->sc_regs->psy_pcictl[0].pci_csr, 0);
csr = PCICTL_SERR | PCICTL_ARB_PARK | PCICTL_ERRINTEN | PCICTL_4ENABLE;
bus_space_write_8(sc->sc_bustag, &sc->sc_regs->psy_pcictl[0].pci_csr, 0, csr);
/* allocate a pair of psycho_pbm's for our simba's */
sc->sc_sabre = malloc(sizeof *pp, M_DEVBUF, M_NOWAIT);
sc->sc_simba_a = malloc(sizeof *pp, M_DEVBUF, M_NOWAIT);
sc->sc_simba_b = malloc(sizeof *pp, M_DEVBUF, M_NOWAIT);
if (sc->sc_simba_a == NULL || sc->sc_simba_b == NULL)
panic("could not allocate simba pbm's");
memset(sc->sc_sabre, 0, sizeof *pp);
memset(sc->sc_simba_a, 0, sizeof *pp);
memset(sc->sc_simba_b, 0, sizeof *pp);
/* grab the sabre ranges; use them for both simba's */
psycho_get_ranges(sc->sc_node, &sc->sc_sabre->pp_range,
&sc->sc_sabre->pp_nrange);
sc->sc_simba_b->pp_range = sc->sc_simba_a->pp_range =
sc->sc_sabre->pp_range;
sc->sc_simba_b->pp_nrange = sc->sc_simba_a->pp_nrange =
sc->sc_sabre->pp_nrange;
/* get the bus-range for the sabre. we expect 0..2 */
psycho_get_bus_range(sc->sc_node, sabre_br);
pba->pba_bus = sabre_br[0];
printf("bus range %u to %u", sabre_br[0], sabre_br[1]);
for (node = firstchild(sc->sc_node); node; node = nextsibling(node)) {
char *name = getpropstring(node, "name");
char *model, who;
if (strcmp(name, ROM_PCI_NAME) != 0)
continue;
model = getpropstring(node, "model");
if (strcmp(model, ROM_SIMBA_MODEL) != 0)
continue;
psycho_get_bus_range(node, simba_br);
if (simba_br[0] == 1) { /* PCI B */
pp = sc->sc_simba_b;
pp->pp_pcictl = &sc->sc_regs->psy_pcictl[1];
pp->pp_sb_diag = &sc->sc_regs->psy_strbufdiag[1];
who = 'b';
} else { /* PCI A */
pp = sc->sc_simba_a;
pp->pp_pcictl = &sc->sc_regs->psy_pcictl[0];
pp->pp_sb_diag = &sc->sc_regs->psy_strbufdiag[0];
who = 'a';
}
/* link us in .. */
pp->pp_sc = sc;
printf("; simba %c, PCI bus %d", who, simba_br[0]);
/* grab the simba registers, interrupt map and map mask */
psycho_get_registers(node, &pp->pp_regs, &pp->pp_nregs);
psycho_get_intmap(node, &pp->pp_intmap, &pp->pp_nintmap);
psycho_get_intmapmask(node, &pp->pp_intmapmask);
/* allocate our tags */
pp->pp_memt = psycho_alloc_mem_tag(pp);
pp->pp_iot = psycho_alloc_io_tag(pp);
pp->pp_dmat = psycho_alloc_dma_tag(pp);
pp->pp_flags = (pp->pp_memt ? PCI_FLAGS_MEM_ENABLED : 0) |
(pp->pp_iot ? PCI_FLAGS_IO_ENABLED : 0);
/* allocate a chipset for this */
pp->pp_pc = psycho_alloc_chipset(pp, node, &_sparc_pci_chipset);
}
/* setup the rest of the sabre pbm */
pp = sc->sc_sabre;
pp->pp_sc = sc;
pp->pp_memt = sc->sc_psycho_this->pp_memt;
pp->pp_iot = sc->sc_psycho_this->pp_iot;
pp->pp_dmat = sc->sc_psycho_this->pp_dmat;
pp->pp_flags = sc->sc_psycho_this->pp_flags;
pp->pp_intmap = NULL;
pp->pp_regs = NULL;
pp->pp_pcictl = sc->sc_psycho_this->pp_pcictl;
pp->pp_sb_diag = sc->sc_psycho_this->pp_sb_diag;
pba->pba_pc = psycho_alloc_chipset(pp, sc->sc_node,
sc->sc_psycho_this->pp_pc);
printf("\n");
/* and finally start up the IOMMU ... */
psycho_iommu_init(sc);
}
/*
* SUNW,psycho initialisation ..
* - XXX what do we do here?
*
* i think that an attaching psycho should here find it's partner psycho
* and if they haven't been attached yet, allocate both psycho_pbm's and
* fill them both in here, and when the partner attaches, there is little
* to do... perhaps keep a static array of what psycho have been found so
* far (or perhaps those that have not yet been finished). .mrg.
* note that the partner can be found via matching `ranges' properties.
*/
static void
psycho_init(sc, pba)
struct psycho_softc *sc;
struct pcibus_attach_args *pba;
{
/*
* ok, we are a psycho.
*/
panic("can't do SUNW,psycho yet");
}
/*
* PCI bus support
*/
/*
* allocate a PCI chipset tag and set it's cookie.
*/
static pci_chipset_tag_t
psycho_alloc_chipset(pp, node, pc)
struct psycho_pbm *pp;
int node;
pci_chipset_tag_t pc;
{
pci_chipset_tag_t npc;
npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT);
if (npc == NULL)
panic("could not allocate pci_chipset_tag_t");
memcpy(npc, pc, sizeof *pc);
npc->cookie = pp;
npc->node = node;
return (npc);
}
/*
* grovel the OBP for various psycho properties
*/
static void
psycho_get_bus_range(node, brp)
int node;
int *brp;
{
int n;
if (getprop(node, "bus-range", sizeof(*brp), &n, (void **)&brp))
panic("could not get psycho bus-range");
if (n != 2)
panic("broken psycho bus-range");
DPRINTF(PDB_PROM, ("psycho debug: got `bus-range' for node %08x: %u - %u\n", node, brp[0], brp[1]));
}
static void
psycho_get_ranges(node, rp, np)
int node;
struct psycho_ranges **rp;
int *np;
{
if (getprop(node, "ranges", sizeof(**rp), np, (void **)rp))
panic("could not get psycho ranges");
DPRINTF(PDB_PROM, ("psycho debug: got `ranges' for node %08x: %d entries\n", node, *np));
}
static void
psycho_get_registers(node, rp, np)
int node;
struct psycho_registers **rp;
int *np;
{
if (getprop(node, "reg", sizeof(**rp), np, (void **)rp))
panic("could not get psycho registers");
DPRINTF(PDB_PROM, ("psycho debug: got `reg' for node %08x: %d entries\n", node, *np));
}
static void
psycho_get_intmap(node, imp, np)
int node;
struct psycho_interrupt_map **imp;
int *np;
{
if (getprop(node, "interrupt-map", sizeof(**imp), np, (void **)imp))
panic("could not get psycho interrupt-map");
DPRINTF(PDB_PROM, ("psycho debug: got `interupt-map' for node %08x\n", node));
}
static void
psycho_get_intmapmask(node, immp)
int node;
struct psycho_interrupt_map_mask *immp;
{
int n;
if (getprop(node, "interrupt-map-mask", sizeof(*immp), &n,
(void **)&immp))
panic("could not get psycho interrupt-map-mask");
if (n != 1)
panic("broken psycho interrupt-map-mask");
DPRINTF(PDB_PROM, ("psycho debug: got `interrupt-map-mask' for node %08x\n", node));
}
/*
* IOMMU code
*/
/*
* initialise the IOMMU..
*/
void
psycho_iommu_init(sc)
struct psycho_softc *sc;
{
char *name;
/* punch in our copies */
sc->sc_is.is_bustag = sc->sc_bustag;
sc->sc_is.is_iommu = &sc->sc_regs->psy_iommu;
sc->sc_is.is_sb = &sc->sc_regs->psy_iommu_strbuf;
/* give us a nice name.. */
name = (char *)malloc(32, M_DEVBUF, M_NOWAIT);
if (name == 0)
panic("couldn't malloc iommu name");
snprintf(name, 32, "%s dvma", sc->sc_dev.dv_xname);
DPRINTF(PDB_IOMMU, ("psycho base %p phys %p\n", (long)sc->sc_regs, (long)pmap_extract(pmap_kernel(), (vaddr_t)sc->sc_regs)));
/* XXX XXX XXX FIX ME tsbsize XXX XXX XXX */
iommu_init(name, &sc->sc_is, 0);
}

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sys/arch/sparc64/dev/psycho_bus.c Normal file
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/* $NetBSD: psychoreg.h,v 1.1 1999/06/04 13:42:15 mrg Exp $ */
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
* contributed to Berkeley.
*
* All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Lawrence Berkeley Laboratory.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)sbusreg.h 8.1 (Berkeley) 6/11/93
*/
#ifndef _SPARC64_DEV_PSYCHOREG_H_
#define _SPARC64_DEV_PSYCHOREG_H_
/*
* Sun4u PCI definitions. Here's where we deal w/the machine
* dependencies of psycho and the PCI controller on the UltraIIi.
*
* All PCI registers are bit-swapped, however they are not byte-swapped.
* This means that they must be accessed using little-endian access modes,
* either map the pages little-endian or use little-endian ASIs.
*
* PSYCHO implements two PCI buses, A and B.
*/
struct psychoreg {
struct upareg {
u_int64_t upa_portid; /* UPA port ID register */ /* 1fe.0000.0000 */
u_int64_t upa_config; /* UPA config register */ /* 1fe.0000.0008 */
} sys_upa;
u_int64_t psy_csr; /* PSYCHO control/status register */ /* 1fe.0000.0010 */
u_int64_t pad0;
u_int64_t psy_ecccr; /* ECC control register */ /* 1fe.0000.0020 */
u_int64_t reserved; /* 1fe.0000.0028 */
u_int64_t psy_ue_afsr; /* Uncorrectable Error AFSR */ /* 1fe.0000.0030 */
u_int64_t psy_ue_afar; /* Uncorrectable Error AFAR */ /* 1fe.0000.0038 */
u_int64_t psy_ce_afsr; /* Correctable Error AFSR */ /* 1fe.0000.0040 */
u_int64_t psy_ce_afar; /* Correctable Error AFAR */ /* 1fe.0000.0048 */
u_int64_t pad1[22];
struct perfmon {
u_int64_t pm_cr; /* Performance monitor control reg */ /* 1fe.0000.0100 */
u_int64_t pm_count; /* Performance monitor counter reg */ /* 1fe.0000.0108 */
} psy_pm;
u_int64_t pad2[30];
struct iommureg psy_iommu; /* 1fe.0000.0200,0210 */
u_int64_t pad3[317];
u_int64_t pcia_slot0_int; /* PCI bus a slot 0 irq map reg */ /* 1fe.0000.0c00 */
u_int64_t pcia_slot1_int; /* PCI bus a slot 1 irq map reg */ /* 1fe.0000.0c08 */
u_int64_t pcia_slot2_int; /* PCI bus a slot 2 irq map reg (IIi)*/ /* 1fe.0000.0c10 */
u_int64_t pcia_slot3_int; /* PCI bus a slot 3 irq map reg (IIi)*/ /* 1fe.0000.0c18 */
u_int64_t pcib_slot0_int; /* PCI bus b slot 0 irq map reg */ /* 1fe.0000.0c20 */
u_int64_t pcib_slot1_int; /* PCI bus b slot 1 irq map reg */ /* 1fe.0000.0c28 */
u_int64_t pcib_slot2_int; /* PCI bus b slot 1 irq map reg */ /* 1fe.0000.0c30 */
u_int64_t pcib_slot3_int; /* PCI bus b slot 1 irq map reg */ /* 1fe.0000.0c38 */
u_int64_t pad5[120];
u_int64_t scsi_int_map; /* SCSI interrupt map reg */ /* 1fe.0000.1000 */
u_int64_t ether_int_map; /* ethernet interrupt map reg */ /* 1fe.0000.1008 */
u_int64_t bpp_int_map; /* parallel interrupt map reg */ /* 1fe.0000.1010 */
u_int64_t audior_int_map; /* audio record interrupt map reg */ /* 1fe.0000.1018 */
u_int64_t audiop_int_map; /* audio playback interrupt map reg */ /* 1fe.0000.1020 */
u_int64_t power_int_map; /* power fail interrupt map reg */ /* 1fe.0000.1028 */
u_int64_t ser_kbd_ms_int_map; /* serial/kbd/mouse interrupt map reg *//* 1fe.0000.1030 */
u_int64_t fd_int_map; /* floppy interrupt map reg */ /* 1fe.0000.1038 */
u_int64_t spare_int_map; /* spare interrupt map reg */ /* 1fe.0000.1040 */
u_int64_t kbd_int_map; /* kbd [unused] interrupt map reg */ /* 1fe.0000.1048 */
u_int64_t mouse_int_map; /* mouse [unused] interrupt map reg */ /* 1fe.0000.1050 */
u_int64_t serial_int_map; /* second serial interrupt map reg */ /* 1fe.0000.1058 */
u_int64_t timer0_int_map; /* timer 0 interrupt map reg */ /* 1fe.0000.1060 */
u_int64_t timer1_int_map; /* timer 1 interrupt map reg */ /* 1fe.0000.1068 */
u_int64_t ue_int_map; /* UE interrupt map reg */ /* 1fe.0000.1070 */
u_int64_t ce_int_map; /* CE interrupt map reg */ /* 1fe.0000.1078 */
u_int64_t pciaerr_int_map; /* PCI bus a error interrupt map reg */ /* 1fe.0000.1080 */
u_int64_t pciberr_int_map; /* PCI bus b error interrupt map reg */ /* 1fe.0000.1088 */
u_int64_t pwrmgt_int_map; /* power mgmt wake interrupt map reg */ /* 1fe.0000.1090 */
u_int64_t ffb0_int_map; /* FFB0 graphics interrupt map reg */ /* 1fe.0000.1098 */
u_int64_t ffb1_int_map; /* FFB1 graphics interrupt map reg */ /* 1fe.0000.10a0 */
u_int64_t pad6[107];
/* Note: clear interrupt 0 registers are not really used */
u_int64_t pcia0_clr_int[4]; /* PCI a slot 0 clear int regs 0..7 */ /* 1fe.0000.1400-1418 */
u_int64_t pcia1_clr_int[4]; /* PCI a slot 1 clear int regs 0..7 */ /* 1fe.0000.1420-1438 */
u_int64_t pcia2_clr_int[4]; /* PCI a slot 2 clear int regs 0..7 */ /* 1fe.0000.1440-1458 */
u_int64_t pcia3_clr_int[4]; /* PCI a slot 3 clear int regs 0..7 */ /* 1fe.0000.1480-1478 */
u_int64_t pcib0_clr_int[4]; /* PCI b slot 0 clear int regs 0..7 */ /* 1fe.0000.1480-1498 */
u_int64_t pcib1_clr_int[4]; /* PCI b slot 1 clear int regs 0..7 */ /* 1fe.0000.14a0-14b8 */
u_int64_t pcib2_clr_int[4]; /* PCI b slot 2 clear int regs 0..7 */ /* 1fe.0000.14c0-14d8 */
u_int64_t pcib3_clr_int[4]; /* PCI b slot 3 clear int regs 0..7 */ /* 1fe.0000.14d0-14f8 */
u_int64_t pad8[96];
u_int64_t scsi_clr_int; /* SCSI clear int reg */ /* 1fe.0000.1800 */
u_int64_t ether_clr_int; /* ethernet clear int reg */ /* 1fe.0000.1808 */
u_int64_t bpp_clr_int; /* parallel clear int reg */ /* 1fe.0000.1810 */
u_int64_t audior_clr_int; /* audio record clear int reg */ /* 1fe.0000.1818 */
u_int64_t audiop_clr_int; /* audio playback clear int reg */ /* 1fe.0000.1820 */
u_int64_t power_clr_int; /* power fail clear int reg */ /* 1fe.0000.1828 */
u_int64_t ser_kb_ms_clr_int; /* serial/kbd/mouse clear int reg */ /* 1fe.0000.1830 */
u_int64_t fd_clr_int; /* floppy clear int reg */ /* 1fe.0000.1838 */
u_int64_t spare_clr_int; /* spare clear int reg */ /* 1fe.0000.1840 */
u_int64_t kbd_clr_int; /* kbd [unused] clear int reg */ /* 1fe.0000.1848 */
u_int64_t mouse_clr_int; /* mouse [unused] clear int reg */ /* 1fe.0000.1850 */
u_int64_t serial_clr_int; /* second serial clear int reg */ /* 1fe.0000.1858 */
u_int64_t timer0_clr_int; /* timer 0 clear int reg */ /* 1fe.0000.1860 */
u_int64_t timer1_clr_int; /* timer 1 clear int reg */ /* 1fe.0000.1868 */
u_int64_t ue_clr_int; /* UE clear int reg */ /* 1fe.0000.1870 */
u_int64_t ce_clr_int; /* CE clear int reg */ /* 1fe.0000.1878 */
u_int64_t pciaerr_clr_int; /* PCI bus a error clear int reg */ /* 1fe.0000.1880 */
u_int64_t pciberr_clr_int; /* PCI bus b error clear int reg */ /* 1fe.0000.1888 */
u_int64_t pwrmgt_clr_int; /* power mgmt wake clr interrupt reg */ /* 1fe.0000.1890 */
u_int64_t pad9[45];
u_int64_t intr_retry_timer; /* interrupt retry timer */ /* 1fe.0000.1a00 */
u_int64_t pad10[63];
struct timer_counter {
u_int64_t tc_count; /* timer/counter 0/1 count register */ /* 1fe.0000.1c00,1c10 */
u_int64_t tc_limit; /* timer/counter 0/1 limit register */ /* 1fe.0000.1c08,1c18 */
} tc[2];
u_int64_t pci_dma_write_sync; /* PCI DMA write sync register (IIi) */ /* 1fe.0000.1c20 */
u_int64_t pad11[123];
struct pci_ctl {
u_int64_t pci_csr; /* PCI a/b control/status register */ /* 1fe.0000.2000,4000 */
u_int64_t pci_afsr; /* PCI a/b AFSR register */ /* 1fe.0000.2010,4010 */
u_int64_t pci_afar; /* PCI a/b AFAR register */ /* 1fe.0000.2018,4018 */
u_int64_t pci_diag; /* PCI a/b diagnostic register */ /* 1fe.0000.2020,4020 */
u_int64_t pci_tasr; /* PCI target address space reg (IIi)*/ /* 1fe.0000.2020,4028 */
u_int64_t pad12[250];
/* This is really the IOMMU's, not the PCI bus's */
struct iommu_strbuf pci_strbuf; /* 1fe.0000.2800-210 */
#define psy_iommu_strbuf psy_pcictl[0].pci_strbuf
u_int64_t pad13[765];
} psy_pcictl[2]; /* For PCI a and b */
/* NB: FFB0 and FFB1 intr map regs also appear at 1fe.0000.6000 and 1fe.0000.8000 respectively */
u_int64_t pad14[2048];
u_int64_t dma_scb_diag0; /* DMA scoreboard diag reg 0 */ /* 1fe.0000.a000 */
u_int64_t dma_scb_diag1; /* DMA scoreboard diag reg 1 */ /* 1fe.0000.a008 */
u_int64_t pad15[126];
u_int64_t iommu_svadiag; /* IOMMU virtual addr diag reg */ /* 1fe.0000.a400 */
u_int64_t iommu_tlb_comp_diag; /* IOMMU TLB tag compare diag reg */ /* 1fe.0000.a408 */
u_int64_t pad16[30];
u_int64_t iommu_queue_diag[16]; /* IOMMU LRU queue diag */ /* 1fe.0000.a500-a578 */
u_int64_t tlb_tag_diag[16]; /* TLB tag diag */ /* 1fe.0000.a580-a5f8 */
u_int64_t tlb_data_diag[16]; /* TLB data RAM diag */ /* 1fe.0000.a600-a678 */
u_int64_t pad17[48];
u_int64_t pci_int_diag; /* SBUS int state diag reg */ /* 1fe.0000.a800 */
u_int64_t obio_int_diag; /* OBIO and misc int state diag reg */ /* 1fe.0000.a808 */
u_int64_t pad18[254];
struct strbuf_diag {
u_int64_t strbuf_data_diag[128]; /* streaming buffer data RAM diag */ /* 1fe.0000.b000-b3f8 */
u_int64_t strbuf_error_diag[128]; /* streaming buffer error status diag *//* 1fe.0000.b400-b7f8 */
u_int64_t strbuf_pg_tag_diag[16]; /* streaming buffer page tag diag */ /* 1fe.0000.b800-b878 */
u_int64_t pad19[16];
u_int64_t strbuf_ln_tag_diag[16]; /* streaming buffer line tag diag */ /* 1fe.0000.b900-b978 */
u_int64_t pad20[208];
} psy_strbufdiag[2]; /* For PCI a and b */
/*
* Here is the rest of the map, which we're not specifying:
*
* 1fe.0100.0000 - 1fe.01ff.ffff PCI configuration space
* 1fe.0100.0000 - 1fe.0100.00ff PCI B configuration header
* 1fe.0101.0000 - 1fe.0101.00ff PCI A configuration header
* 1fe.0200.0000 - 1fe.0200.ffff PCI A I/O space
* 1fe.0201.0000 - 1fe.0201.ffff PCI B I/O space
* 1ff.0000.0000 - 1ff.7fff.ffff PCI A memory space
* 1ff.8000.0000 - 1ff.ffff.ffff PCI B memory space
*
* NB: config and I/O space can use 1-4 byte accesses, not 8 byte accesses.
* Memory space can use any sized accesses.
*
* Note that the SUNW,sabre (APB) has slightly differrent addresses
* than the above. This is mostly due to the fact that the APB is
* a multi-function PCI device with two PCI bridges, and the U2P is
* two separate PCI devices (also PCI bridges). It uses the same
* PCI configuration space, though the configuration header for each
* PCI bus is located differently due to the SUNW,simba PCI busses
* being function 0 and function 1 of the APB, whereas the psycho's
* are each their own PCI device. The I/O and memory spaces are each
* split into 8 equally sized areas (8x2MB blocks for I/O space, and
* 8x512MB blocks for memory space). These are allocated in to either
* PCI A or PCI B, or neither in the APB's `I/O Address Map Register
* A/B' (0xde) and `Memory Address Map Register A/B' (0xdf) registers
* of each simba. We must ensure that both of the following are
* correct (the prom should do this for us):
*
* (PCI A Memory Address Map) & (PCI B Memory Address Map) == 0
*
* (PCI A I/O Address Map) & (PCI B I/O Address Map) == 0
*
* 1fe.0100.0000 - 1fe.01ff.ffff PCI configuration space
* 1fe.0100.0800 - 1fe.0100.08ff PCI B configuration header
* 1fe.0100.0900 - 1fe.0100.09ff PCI A configuration header
* 1fe.0200.0000 - 1fe.02ff.ffff PCI I/O space (divided)
* 1ff.0000.0000 - 1ff.ffff.ffff PCI memory space (divided)
*/
};
/* what the bits mean! */
/* PCI [a|b] control/status register */
/* note that the sabre only has one set of PCI control/status registers */
#define PCICTL_SERR 0x0000000400000000 /* SERR asserted; W1C */
#define PCICTL_ARB_PARK 0x0000000000200000 /* PCI arbitration parking */
#define PCICTL_ERRINTEN 0x0000000000000100 /* PCI error interrupt enable */
#define PCICTL_4ENABLE 0x000000000000000f /* enable 4 PCI slots */
#define PCICTL_6ENABLE 0x000000000000003f /* enable 6 PCI slots */
/*
* these are the PROM structures we grovel
*/
/*
* For the physical adddresses split into 3 32 bit values, we deocde them
* like the following (PCI Bus binding 2.0, 2.2.1.1 Numerical Representation)
*
* phys.hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr
* phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
* phys.lo cell: llllllll llllllll llllllll llllllll
*
* where these bits affect the address' properties:
* n not-relocatable
* p prefetchable
* t aliased (non-relocatable IO), below 1MB (memory) or
* below 64KB (reloc. IO)
* ss address space code:
* 00 - configuration space
* 01 - I/O space
* 10 - 32 bit memory space
* 11 - 64 bit memory space
* bb..bb 8 bit bus number
* ddddd 5 bit device number
* fff 3 bit function number
* rr..rr 8 bit register number
* hh..hh 32 bit unsigned value
* ll..ll 32 bit unsigned value
* the values of hh..hh and ll..ll are combined to form a larger number.
*
* For config space, we don't have to do much special. For I/O space,
* hh..hh must be zero, and if n == 0 ll..ll is the offset from the
* start of I/O space, otherwise ll..ll is the I/O space. For memory
* space, hh..hh must be zero for the 32 bit space, and is the high 32
* bits in 64 bit space, with ll..ll being the low 32 bits in both cases,
* with offset handling being driver via `n == 0' as for I/O space.
*/
struct psycho_registers {
u_int32_t phys_hi;
u_int32_t phys_mid;
u_int32_t phys_lo;
u_int32_t size_hi;
u_int32_t size_lo;
};
struct psycho_ranges {
u_int32_t cspace;
u_int32_t child_hi;
u_int32_t child_lo;
u_int32_t phys_hi;
u_int32_t phys_lo;
u_int32_t size_hi;
u_int32_t size_lo;
};
struct psycho_interrupt_map {
u_int32_t phys_hi;
u_int32_t phys_mid;
u_int32_t phys_lo;
u_int32_t intr;
int32_t child_node;
u_int32_t child_intr;
};
struct psycho_interrupt_map_mask {
u_int32_t phys_hi;
u_int32_t phys_mid;
u_int32_t phys_lo;
u_int32_t intr;
};
#endif /* _SPARC64_DEV_PSYCHOREG_H_ */

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/* $NetBSD: psychovar.h,v 1.1 1999/06/04 13:42:15 mrg Exp $ */
/*
* Copyright (c) 1999 Matthew R. Green
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _SPARC64_DEV_PSYCHOVAR_H_
#define _SPARC64_DEV_PSYCHOVAR_H_
/* per real PCI bus info */
struct psycho_softc;
struct psycho_pbm {
/* link to mum */
struct psycho_softc *pp_sc;
/*
* note that the sabre really only has one ranges property,
* used for both simba a and simba b (but the ranges for
* real psychos are the same for PCI A and PCI B anyway).
*/
struct psycho_registers *pp_regs;
struct psycho_ranges *pp_range;
struct psycho_interrupt_map *pp_intmap;
struct psycho_interrupt_map_mask pp_intmapmask;
/* counts of above */
int pp_nregs;
int pp_nrange;
int pp_nintmap;
/* chipset tag for this instance */
pci_chipset_tag_t pp_pc;
/* our tags */
bus_space_tag_t pp_memt;
bus_space_tag_t pp_iot;
bus_dma_tag_t pp_dmat;
int pp_flags;
/* and pointers into the psycho regs for our bits */
struct pci_ctl *pp_pcictl;
struct strbuf_diag *pp_sb_diag;
};
/*
* per-PCI bus on mainbus softc structure; one for sabre, or two
* per pair of psycho's.
*/
struct psycho_softc {
struct device sc_dev;
/*
* one sabre has two simba's. psycho's are separately attached,
* with the `other' psycho_pbm allocated at the first's attach.
*/
struct psycho_pbm *sc_sabre;
struct psycho_pbm *__sc_psycho_this;
struct psycho_pbm *__sc_psycho_other;
#define sc_simba_a __sc_psycho_this
#define sc_simba_b __sc_psycho_other
#define sc_psycho_this __sc_psycho_this
#define sc_psycho_other __sc_psycho_other
/*
* PSYCHO register. we record the base physical address of these
* also as it is the base of the entire PSYCHO
*/
struct psychoreg *sc_regs;
paddr_t sc_basepaddr;
/* our tags (from parent) */
bus_space_tag_t sc_bustag;
bus_dma_tag_t sc_dmatag;
/* config space */
bus_space_tag_t sc_configtag;
paddr_t sc_configaddr;
int sc_clockfreq;
int sc_node; /* prom node */
int sc_mode; /* (whatareya?) */
#define PSYCHO_MODE_SABRE 1 /* i'm a sabre (yob) */
#define PSYCHO_MODE_PSYCHO_A 2 /* i'm a psycho (w*nker) */
#define PSYCHO_MODE_PSYCHO_B 3 /* i'm another psycho (w*nker) */
struct iommu_state sc_is;
};
/* config space is per-psycho. mem/io/dma are per-pci bus */
bus_dma_tag_t psycho_alloc_dma_tag __P((struct psycho_pbm *));
bus_space_tag_t psycho_alloc_bus_tag __P((struct psycho_pbm *, int));
#define psycho_alloc_config_tag(pp) psycho_alloc_bus_tag((pp), PCI_CONFIG_BUS_SPACE)
#define psycho_alloc_mem_tag(pp) psycho_alloc_bus_tag((pp), PCI_MEMORY_BUS_SPACE)
#define psycho_alloc_io_tag(pp) psycho_alloc_bus_tag((pp), PCI_IO_BUS_SPACE)
int psycho_intr_map __P((pcitag_t, int, int, pci_intr_handle_t *));
#endif /* _SPARC64_DEV_PSYCHOVAR_H_ */

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sys/arch/sparc64/dev/simba.c Normal file
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/* $NetBSD: simba.c,v 1.1 1999/06/04 13:42:15 mrg Exp $ */
/*
* Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Christopher G. Demetriou
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* from: NetBSD: ppb.c,v 1.18 1998/06/08 06:55:57 thorpej Exp
*/
/*
* this is a copy of the pci/ppb driver slightly modified to
* work with the SUNW,simba PCI bus.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/device.h>
#define _SPARC_BUS_DMA_PRIVATE
#include <machine/bus.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcidevs.h>
#include <sparc64/dev/iommureg.h>
#include <sparc64/dev/iommuvar.h>
#include <sparc64/dev/psychoreg.h>
#include <sparc64/dev/psychovar.h>
#include <sparc64/dev/simbareg.h>
static int simba_match __P((struct device *, struct cfdata *, void *));
static void simba_attach __P((struct device *, struct device *, void *));
static int simba_print __P((void *, const char *pnp));
extern struct sparc_pci_chipset sparc_simba_pci_chipset;
struct cfattach simba_ca = {
sizeof(struct device), simba_match, simba_attach
};
static int
simba_match(parent, match, aux)
struct device *parent;
struct cfdata *match;
void *aux;
{
struct pci_attach_args *pa = aux;
if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN &&
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_SIMBA)
return (1);
return (0);
}
/*
* XXX
*
* this code depends on the parent PCI bus's parent being the sabre!
*/
static void
simba_attach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct pci_attach_args *pa = aux;
struct psycho_softc *sc = (struct psycho_softc *)parent->dv_parent; /* XXX */
struct psycho_pbm *pp;
pci_chipset_tag_t pc = pa->pa_pc;
struct pcibus_attach_args pba;
pcireg_t busdata;
char devinfo[256];
pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo);
printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class));
busdata = pci_conf_read(pc, pa->pa_tag, PPB_REG_BUSINFO);
/*
* this uses the generic PCI bus value's, rather than the `bus-range'
* property; that's cuz this code was stolen from dev/pci/ppb.c. we
* might need to change to that yet. getting the prom-node might be
* fun, but we *do* have pa->pa_pc->cookie->...
*
* perhaps it would be all better to probe the simba's and get all
* the info ourselves.. we'll see.
*/
switch (PPB_BUSINFO_SECONDARY(busdata)) {
default:
printf("%s: not configured by system firmware (bus %d)\n",
self->dv_xname, PPB_BUSINFO_SECONDARY(busdata));
return;
case 1: /* PCI B */
pp = sc->sc_simba_b;
break;
case 2: /* PCI A */
pp = sc->sc_simba_a;
break;
}
/*
* attach the PCI bus than hangs off of it. we use the
* per-psycho values.
*/
pba.pba_busname = "pci";
pba.pba_iot = pp->pp_iot;
pba.pba_memt = pp->pp_memt;
pba.pba_dmat = pp->pp_dmat;
pba.pba_pc = pp->pp_pc;
pba.pba_flags = pp->pp_flags;
pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata);
pba.pba_intrswiz = pa->pa_intrswiz;
pba.pba_intrtag = pa->pa_intrtag;
config_found(self, &pba, simba_print);
}
static int
simba_print(aux, p)
void *aux;
const char *p;
{
struct pcibus_attach_args *pba = aux;
/* only PCIs can attach to sabre's; easy. */
if (p)
printf("pci at %s", p);
printf(" bus %d", pba->pba_bus);
return (UNCONF);
}

74
sys/arch/sparc64/dev/simbareg.h Normal file
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/* $NetBSD: simbareg.h,v 1.1 1999/06/04 13:42:15 mrg Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Christopher G. Demetriou
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* from: NetBSD: ppbreg.h,v 1.2 1996/03/14 02:35:35 cgd Exp
*/
/*
* PCI-PCI Bridge chip register definitions and macros.
* Derived from information found in the ``PCI to PCI Bridge
* Architecture Specification, Revision 1.0, April 5, 1994.''
*
* XXX much is missing.
*/
/*
* Register offsets
*/
#define PPB_REG_BASE0 0x10 /* Base Addr Reg. 0 */
#define PPB_REG_BASE1 0x14 /* Base Addr Reg. 1 */
#define PPB_REG_BUSINFO 0x18 /* Bus information */
#define PPB_REG_IOSTATUS 0x1c /* I/O base+lim & sec stat */
#define PPB_REG_MEM 0x20 /* Memory base/limit */
#define PPB_REG_PREFMEM 0x24 /* Pref Mem base/limit */
#define PPB_REG_PREFBASE_HI32 0x28 /* Pref Mem base high bits */
#define PPB_REG_PREFLIM_HI32 0x2c /* Pref Mem lim high bits */
#define PPB_REG_IO_HI 0x30 /* I/O base+lim high bits */
#define PPB_REG_BRIDGECONTROL PCI_INTERRUPT_REG /* bridge control register */
/*
* Macros to extract the contents of the "Bus Info" register.
*/
#define PPB_BUSINFO_PRIMARY(bir) \
((bir >> 0) & 0xff)
#define PPB_BUSINFO_SECONDARY(bir) \
((bir >> 8) & 0xff)
#define PPB_BUSINFO_SUBORDINATE(bir) \
((bir >> 16) & 0xff)
#define PPB_BUSINFO_SECLAT(bir) \
((bir >> 24) & 0xff)
/*
* Routine to translate between secondary bus interrupt pin/device number and
* primary bus interrupt pin number.
*/
#define PPB_INTERRUPT_SWIZZLE(pin, device) \
((((pin) + (device) - 1) % 4) + 1)

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/* $NetBSD: pci_machdep.h,v 1.1 1999/06/04 13:42:15 mrg Exp $ */
/*
* Copyright (c) 1999 Matthew R. Green
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE_PCI_MACHDEP_H_
#define _MACHINE_PCI_MACHDEP_H_
/*
* define some bits used to glue into the common PCI code.
*/
typedef struct sparc_pci_chipset *pci_chipset_tag_t;
typedef u_int pcitag_t;
typedef u_int pci_intr_handle_t;
struct sparc_pci_chipset {
void *cookie; /* psycho_pbm, but sssh! */
int node; /* OFW node */
/* do we need any more here? */
};
void pci_attach_hook __P((struct device *, struct device *,
struct pcibus_attach_args *));
int pci_bus_maxdevs __P((pci_chipset_tag_t, int));
pcitag_t pci_make_tag __P((pci_chipset_tag_t, int, int, int));
pcireg_t pci_conf_read __P((pci_chipset_tag_t, pcitag_t, int));
void pci_conf_write __P((pci_chipset_tag_t, pcitag_t, int,
pcireg_t));
int pci_intr_map __P((pci_chipset_tag_t, pcitag_t, int, int,
pci_intr_handle_t *));
const char *pci_intr_string __P((pci_chipset_tag_t, pci_intr_handle_t));
void *pci_intr_establish __P((pci_chipset_tag_t, pci_intr_handle_t,
int, int (*)(void *), void *));
void pci_intr_disestablish __P((pci_chipset_tag_t, void *));
#endif /* _MACHINE_PCI_MACHDEP_H_ */