- Rework spl(9) implementation. Use _spl*() processor mask manipulating
routines now reside in locore.S. No functional difference is expected. - Replace abused splx() abuse with _splset() to change MIPS processor interrupt mask bit. 'mips/trap.c' side will be fixed soon.
This commit is contained in:
nisimura
parent
789c9e7c48
commit
014ba724c0
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@ -1,4 +1,4 @@
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/* $NetBSD: intr.h,v 1.5 1998/08/25 01:55:40 nisimura Exp $ */
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/* $NetBSD: intr.h,v 1.6 1999/05/25 04:17:58 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -46,27 +46,53 @@
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#ifdef _KERNEL
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#ifndef _LOCORE
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typedef int spl_t;
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extern spl_t splx __P((spl_t));
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extern spl_t splsoftnet __P((void)), splsoftclock __P((void));
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extern spl_t splhigh __P((void));
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extern spl_t spl0 __P((void)); /* XXX should not enable TC on 3min */
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#include <mips/cpuregs.h>
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extern void setsoftnet __P((void)), clearsoftnet __P((void));
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extern void setsoftclock __P((void)), clearsoftclock __P((void));
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extern int _splraise __P((int));
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extern int _spllower __P((int));
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extern int _splset __P((int));
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extern int _splget __P((void));
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extern void _setsoftintr __P((int));
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extern void _clrsoftintr __P((int));
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#define setsoftclock() _setsoftintr(MIPS_SOFT_INT_MASK_0)
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#define setsoftnet() _setsoftintr(MIPS_SOFT_INT_MASK_1)
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#define clearsoftclock() _clrsoftintr(MIPS_SOFT_INT_MASK_0)
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#define clearsoftnet() _clrsoftintr(MIPS_SOFT_INT_MASK_1)
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extern int (*Mach_splnet) __P((void)), (*Mach_splbio) __P((void)),
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(*Mach_splimp) __P((void)), (*Mach_spltty) __P((void)),
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(*Mach_splclock) __P((void)), (*Mach_splstatclock) __P((void)),
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(*Mach_splnone) __P((void));
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#define splhigh() _splraise(MIPS_INT_MASK)
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#define spl0() (void)_spllower(0)
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#define splx(s) (void)_splset(s)
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#define splbio() (_splraise(splvec.splbio))
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#define splnet() (_splraise(splvec.splnet))
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#define spltty() (_splraise(splvec.spltty))
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#define splimp() (_splraise(splvec.splimp))
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#define splpmap() (_splraise(splvec.splimp))
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#define splclock() (_splraise(splvec.splclock))
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#define splstatclock() (_splraise(splvec.splstatclock))
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#define splsoftclock() _spllower(MIPS_SOFT_INT_MASK_0)
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#define splsoftnet() _splraise(MIPS_SOFT_INT_MASK_1)
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#define splnet() (*Mach_splnet)()
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#define splbio() (*Mach_splbio)()
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#define splimp() (*Mach_splimp)()
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#define spltty() (*Mach_spltty)()
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#define splclock() (*Mach_splclock)()
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#define splstatclock() (*Mach_splstatclock)()
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struct splvec {
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int splbio;
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int splnet;
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int spltty;
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int splimp;
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int splclock;
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int splstatclock;
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};
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extern struct splvec splvec;
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/* Conventionals ... */
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#define MIPS_SPLHIGH (MIPS_INT_MASK)
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#define MIPS_SPL0 (MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
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#define MIPS_SPL1 (MIPS_INT_MASK_1|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
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#define MIPS_SPL3 (MIPS_INT_MASK_3|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
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#define MIPS_SPL_0_1 (MIPS_INT_MASK_1|MIPS_SPL0)
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#define MIPS_SPL_0_1_2 (MIPS_INT_MASK_2|MIPS_SPL_0_1)
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#define MIPS_SPL_0_1_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1)
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#define MIPS_SPL_0_1_2_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1_2)
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/*
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* Index into intrcnt[], which is defined in locore
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@ -1,4 +1,4 @@
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/* $NetBSD: dec_3100.c,v 1.10 1999/04/26 09:23:21 nisimura Exp $ */
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/* $NetBSD: dec_3100.c,v 1.11 1999/05/25 04:17:57 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -128,8 +128,7 @@ extern unsigned (*clkread) __P((void));
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void
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dec_3100_init()
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{
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platform.iobus = "ibus";
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platform.iobus = "baseboard";
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platform.os_init = dec_3100_os_init;
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platform.bus_reset = dec_3100_bus_reset;
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@ -150,19 +149,20 @@ dec_3100_os_init()
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*/
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mips_hardware_intr = dec_3100_intr;
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tc_enable_interrupt = dec_3100_enable_intr; /*XXX*/
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Mach_splbio = cpu_spl0;
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Mach_splnet = cpu_spl1;
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Mach_spltty = cpu_spl2;
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Mach_splimp = splhigh; /*XXX Mach_spl1(), if not for malloc()*/
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Mach_splclock = cpu_spl3;
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Mach_splstatclock = cpu_spl3;
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mcclock_addr = (volatile struct chiptime *)
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MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK);
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mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_3);
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/* no high resolution timer circuit; possibly never called */
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clkread = nullclkread;
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splvec.splbio = MIPS_SPL0;
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splvec.splnet = MIPS_SPL_0_1;
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splvec.spltty = MIPS_SPL_0_1_2;
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splvec.splimp = MIPS_SPLHIGH; /* ??? */
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splvec.splclock = MIPS_SPL_0_1_2_3;
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splvec.splstatclock = MIPS_SPL_0_1_2_3;
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mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_3);
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}
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}
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/* If clock interrupts were enabled, re-enable them ASAP. */
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splx(MIPS_SR_INT_IE | (statusReg & MIPS_INT_MASK_3));
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_splset(MIPS_SR_INT_IE | (statusReg & MIPS_INT_MASK_3));
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#if NSII > 0
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if (mask & MIPS_INT_MASK_0) {
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@ -1,4 +1,4 @@
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/* $NetBSD: dec_3max.c,v 1.11 1999/05/21 01:09:50 nisimura Exp $ */
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/* $NetBSD: dec_3max.c,v 1.12 1999/05/25 04:17:57 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -73,7 +73,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: dec_3max.c,v 1.11 1999/05/21 01:09:50 nisimura Exp $");
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__KERNEL_RCSID(0, "$NetBSD: dec_3max.c,v 1.12 1999/05/25 04:17:57 nisimura Exp $");
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#include <sys/types.h>
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#include <sys/systm.h>
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@ -123,8 +123,7 @@ extern unsigned (*clkread) __P((void));
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void
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dec_3max_init()
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{
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platform.iobus = "tcbus";
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platform.iobus = "tc3max";
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platform.os_init = dec_3max_os_init;
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platform.bus_reset = dec_3max_bus_reset;
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@ -140,10 +139,7 @@ dec_3max_init()
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void
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dec_3max_os_init()
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{
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int i;
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volatile int *csr_addr =
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(volatile int *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
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u_int32_t csr;
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/* clear any memory errors from new-config probes */
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*(volatile u_int *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0;
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* Enable ECC memory correction, turn off LEDs, and
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* disable all TURBOchannel interrupts.
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*/
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i = *csr_addr;
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*csr_addr = (i & ~(KN02_CSR_WRESERVED | KN02_CSR_IOINTEN)) |
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KN02_CSR_CORRECT | 0xff;
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csr = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
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csr &= ~(KN02_CSR_WRESERVED|KN02_CSR_IOINTEN|KN02_CSR_CORRECT|0xff);
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*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) = csr;
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mips_hardware_intr = dec_3max_intr;
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tc_enable_interrupt = dec_3max_enable_intr;
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Mach_splbio = Mach_spl0;
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Mach_splnet = Mach_spl0;
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Mach_spltty = Mach_spl0;
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Mach_splimp = Mach_spl0;
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Mach_splclock = cpu_spl1;
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Mach_splstatclock = cpu_spl1;
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mcclock_addr = (volatile struct chiptime *)
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MIPS_PHYS_TO_KSEG1(KN02_SYS_CLOCK);
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mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_1);
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/* no high resolution timer circuit; possibly never called */
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clkread = nullclkread;
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splvec.splbio = MIPS_SPL0;
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splvec.splnet = MIPS_SPL0;
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splvec.spltty = MIPS_SPL0;
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splvec.splimp = MIPS_SPL0;
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splvec.splclock = MIPS_SPL_0_1;
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splvec.splstatclock = MIPS_SPL_0_1;
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mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_1);
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}
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/*
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}
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slotno = 1 << (slotno + KN02_CSR_IOINTEN_SHIFT);
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s = Mach_spl0();
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s = splhigh();
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csr = *p_csr & ~(KN02_CSR_WRESERVED | 0xFF);
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if (on)
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*p_csr = csr | slotno;
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}
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/* If clock interrups were enabled, re-enable them ASAP. */
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splx(MIPS_SR_INT_IE | (statusReg & MIPS_INT_MASK_1));
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_splset(MIPS_SR_INT_IE | (statusReg & MIPS_INT_MASK_1));
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if (mask & MIPS_INT_MASK_0) {
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static int intr_map[8] = { SLOT0_INTR, SLOT1_INTR, SLOT2_INTR,
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@ -1,4 +1,4 @@
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/* $NetBSD: dec_3maxplus.c,v 1.17 1999/05/21 01:09:49 nisimura Exp $ */
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/* $NetBSD: dec_3maxplus.c,v 1.18 1999/05/25 04:17:57 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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@ -73,7 +73,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: dec_3maxplus.c,v 1.17 1999/05/21 01:09:49 nisimura Exp $");
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__KERNEL_RCSID(0, "$NetBSD: dec_3maxplus.c,v 1.18 1999/05/25 04:17:57 nisimura Exp $");
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#include <sys/types.h>
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#include <sys/systm.h>
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@ -141,7 +141,7 @@ dec_3maxplus_init()
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(volatile u_int *) MIPS_PHYS_TO_KSEG1(KN03_REG_INTR);
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u_int intr;
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platform.iobus = "tcioasic";
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platform.iobus = "tc3maxplus";
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platform.os_init = dec_3maxplus_os_init;
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platform.bus_reset = dec_3maxplus_bus_reset;
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@ -166,39 +166,32 @@ dec_3maxplus_init()
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void
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dec_3maxplus_os_init()
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{
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ioasic_base = MIPS_PHYS_TO_KSEG1(KN03_SYS_ASIC);
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mips_hardware_intr = dec_3maxplus_intr;
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tc_enable_interrupt = dec_3maxplus_enable_intr;
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/* clear any pending memory errors. */
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*(volatile u_int *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
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kn03_wbflush();
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/*
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* Reset interrupts.
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*/
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Mach_splbio = Mach_spl0;
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Mach_splnet = Mach_spl0;
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Mach_spltty = Mach_spl0;
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Mach_splimp = Mach_spl0; /* XXX */
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/*
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* Clock interrupts at hw priority 1 must block bio,net,tty
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* at hw priority 0.
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*/
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Mach_splclock = cpu_spl1;
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Mach_splstatclock = cpu_spl1;
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ioasic_base = MIPS_PHYS_TO_KSEG1(KN03_SYS_ASIC);
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mips_hardware_intr = dec_3maxplus_intr;
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tc_enable_interrupt = dec_3maxplus_enable_intr;
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mcclock_addr = (volatile struct chiptime *)
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MIPS_PHYS_TO_KSEG1(KN03_SYS_CLOCK);
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mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_1);
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/* 3MAX+ has IOASIC free-running high resolution timer */
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clkread = kn03_clkread;
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/*
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* Initialize interrupts.
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* 3MAX+ IOASIC interrupts come through INT 0, while
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* clock interrupt does via INT 1. splclock and splstatclock
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* should block IOASIC activities.
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*/
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kn03_tc3_imask = KN03_IM0 &
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~(KN03_INTR_TC_0|KN03_INTR_TC_1|KN03_INTR_TC_2);
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*(u_int *)IOASIC_REG_IMSK(ioasic_base) = kn03_tc3_imask;
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*(u_int *)IOASIC_REG_INTR(ioasic_base) = 0;
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kn03_wbflush();
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splvec.splbio = MIPS_SPL0;
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splvec.splnet = MIPS_SPL0;
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splvec.spltty = MIPS_SPL0;
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splvec.splimp = MIPS_SPL0;
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splvec.splclock = MIPS_SPL_0_1;
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splvec.splstatclock = MIPS_SPL_0_1;
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mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_1);
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*(volatile u_int *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3;
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*(volatile u_int *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe;
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@ -214,8 +207,14 @@ dec_3maxplus_os_init()
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*(volatile u_int *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
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kn03_wbflush();
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/* 3MAX+ has IOASIC free-running high resolution timer */
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clkread = kn03_clkread;
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/*
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* Initialize interrupts.
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*/
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kn03_tc3_imask = KN03_IM0 &
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~(KN03_INTR_TC_0|KN03_INTR_TC_1|KN03_INTR_TC_2);
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*(volatile u_int *)IOASIC_REG_IMSK(ioasic_base) = kn03_tc3_imask;
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*(volatile u_int *)IOASIC_REG_INTR(ioasic_base) = 0;
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kn03_wbflush();
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}
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@ -230,10 +229,10 @@ dec_3maxplus_bus_reset()
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*/
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*(volatile u_int *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
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wbflush();
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kn03_wbflush();
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*(volatile u_int *)IOASIC_REG_INTR(ioasic_base) = 0;
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wbflush();
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kn03_wbflush();
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}
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@ -319,7 +318,7 @@ dec_3maxplus_enable_intr(slotno, handler, sc, on)
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}
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done:
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*(u_int *)IOASIC_REG_IMSK(ioasic_base) = kn03_tc3_imask;
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wbflush();
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kn03_wbflush();
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}
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@ -366,7 +365,7 @@ dec_3maxplus_intr(mask, pc, statusReg, causeReg)
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}
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/* If clock interrups were enabled, re-enable them ASAP. */
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splx(MIPS_SR_INT_ENA_CUR | (statusReg & MIPS_INT_MASK_1));
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_splset(MIPS_SR_INT_IE | (statusReg & MIPS_INT_MASK_1));
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/*
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* Check for late clock interrupts (allow 10% slop). Be careful
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@ -490,7 +489,7 @@ dec_3maxplus_intr(mask, pc, statusReg, causeReg)
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if (mask & MIPS_INT_MASK_3)
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dec_3maxplus_errintr();
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return ((statusReg & ~causeReg & MIPS_HARD_INT_MASK) |
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MIPS_SR_INT_ENA_CUR);
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MIPS_SR_INT_IE);
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}
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@ -508,7 +507,7 @@ dec_3maxplus_errintr()
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erradr = *(u_int *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR);
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errsyn = MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRSYN);
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*(u_int *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
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wbflush();
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kn03_wbflush();
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/* Send to kn02/kn03 memory subsystem handler */
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dec_mtasic_err(erradr, errsyn);
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@ -1,4 +1,4 @@
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/* $NetBSD: dec_3min.c,v 1.15 1999/05/21 01:09:50 nisimura Exp $ */
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/* $NetBSD: dec_3min.c,v 1.16 1999/05/25 04:17:57 nisimura Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
|
||||
|
|
@ -73,7 +73,7 @@
|
|||
|
||||
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
|
||||
|
||||
__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.15 1999/05/21 01:09:50 nisimura Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.16 1999/05/25 04:17:57 nisimura Exp $");
|
||||
|
||||
|
||||
#include <sys/types.h>
|
||||
|
|
@ -140,8 +140,7 @@ extern unsigned (*clkread) __P((void));
|
|||
void
|
||||
dec_3min_init()
|
||||
{
|
||||
|
||||
platform.iobus = "tcbus";
|
||||
platform.iobus = "tc3min";
|
||||
|
||||
platform.os_init = dec_3min_os_init;
|
||||
platform.bus_reset = dec_3min_bus_reset;
|
||||
|
|
@ -170,7 +169,6 @@ dec_3min_bus_reset()
|
|||
|
||||
*(volatile u_int *)IOASIC_REG_INTR(ioasic_base) = 0;
|
||||
kn02ba_wbflush();
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -182,6 +180,11 @@ dec_3min_os_init()
|
|||
tc_enable_interrupt = dec_3min_enable_intr;
|
||||
kmin_tc3_imask = (KMIN_INTR_CLOCK | KMIN_INTR_PSWARN |
|
||||
KMIN_INTR_TIMEOUT);
|
||||
mcclock_addr = (volatile struct chiptime *)
|
||||
MIPS_PHYS_TO_KSEG1(KMIN_SYS_CLOCK);
|
||||
|
||||
/* R4000 3MIN can ultilize on-chip counter */
|
||||
clkread = kn02ba_clkread;
|
||||
|
||||
/*
|
||||
* All the baseboard interrupts come through the I/O ASIC
|
||||
|
|
@ -189,14 +192,13 @@ dec_3min_os_init()
|
|||
* Since we don't know what kinds of devices are in the
|
||||
* turbochannel option slots, just block them all.
|
||||
*/
|
||||
Mach_splbio = cpu_spl3;
|
||||
Mach_splnet = cpu_spl3;
|
||||
Mach_spltty = cpu_spl3;
|
||||
Mach_splimp = cpu_spl3;
|
||||
Mach_splclock = cpu_spl3;
|
||||
Mach_splstatclock = cpu_spl3;
|
||||
mcclock_addr = (volatile struct chiptime *)
|
||||
MIPS_PHYS_TO_KSEG1(KMIN_SYS_CLOCK);
|
||||
splvec.splbio = MIPS_SPL_0_1_2_3;
|
||||
splvec.splnet = MIPS_SPL_0_1_2_3;
|
||||
splvec.spltty = MIPS_SPL_0_1_2_3;
|
||||
splvec.splimp = MIPS_SPL_0_1_2_3;
|
||||
splvec.splclock = MIPS_SPL_0_1_2_3;
|
||||
splvec.splstatclock = MIPS_SPL_0_1_2_3;
|
||||
|
||||
dec_3min_mcclock_cpuspeed(mcclock_addr, MIPS_INT_MASK_3);
|
||||
|
||||
*(volatile u_int *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3;
|
||||
|
|
@ -209,8 +211,8 @@ dec_3min_os_init()
|
|||
/*
|
||||
* Initialize interrupts.
|
||||
*/
|
||||
*(u_int *)IOASIC_REG_IMSK(ioasic_base) = KMIN_IM0;
|
||||
*(u_int *)IOASIC_REG_INTR(ioasic_base) = 0;
|
||||
*(volatile u_int *)IOASIC_REG_IMSK(ioasic_base) = KMIN_IM0;
|
||||
*(volatile u_int *)IOASIC_REG_INTR(ioasic_base) = 0;
|
||||
|
||||
/* clear any memory errors from probes */
|
||||
|
||||
|
|
@ -229,12 +231,9 @@ dec_3min_os_init()
|
|||
physmem_boardmax = physmem_boardmax >> 2;
|
||||
physmem_boardmax = MIPS_PHYS_TO_KSEG1(physmem_boardmax);
|
||||
|
||||
* (volatile u_int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_IMSK) =
|
||||
*(volatile u_int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_IMSK) =
|
||||
kmin_tc3_imask |
|
||||
(KMIN_IM0 & ~(KN03_INTR_TC_0|KN03_INTR_TC_1|KN03_INTR_TC_2));
|
||||
|
||||
/* R4000 3MIN can ultilize on-chip counter */
|
||||
clkread = kn02ba_clkread;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -416,7 +415,7 @@ dec_3min_intr(mask, pc, statusReg, causeReg)
|
|||
~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 |
|
||||
IOASIC_INTR_LANCE|IOASIC_INTR_SCSI);
|
||||
kn02ba_wbflush();
|
||||
splx(MIPS_SR_INT_IE | (statusReg & MIPS_INT_MASK_3));
|
||||
_splset(MIPS_SR_INT_IE | (statusReg & MIPS_INT_MASK_3));
|
||||
}
|
||||
|
||||
if (intr_depth > 1)
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: dec_5100.c,v 1.6 1999/04/26 09:23:22 nisimura Exp $ */
|
||||
/* $NetBSD: dec_5100.c,v 1.7 1999/05/25 04:17:57 nisimura Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
|
||||
|
|
@ -86,7 +86,7 @@ void dec_5100_intr_establish __P((void * cookie, int level,
|
|||
int (*handler) __P((intr_arg_t)), intr_arg_t arg));
|
||||
void dec_5100_intr_disestablish __P((struct ibus_attach_args *ia));
|
||||
|
||||
extern void dec_mips1_wbflush __P((void));
|
||||
extern void kn230_wbflush __P((void));
|
||||
|
||||
extern unsigned nullclkread __P((void));
|
||||
extern unsigned (*clkread) __P((void));
|
||||
|
|
@ -98,8 +98,7 @@ extern unsigned (*clkread) __P((void));
|
|||
void
|
||||
dec_5100_init()
|
||||
{
|
||||
|
||||
platform.iobus = "ibus";
|
||||
platform.iobus = "baseboard";
|
||||
|
||||
platform.os_init = dec_5100_os_init;
|
||||
platform.bus_reset = dec_5100_bus_reset;
|
||||
|
|
@ -107,6 +106,7 @@ dec_5100_init()
|
|||
platform.device_register = dec_5100_device_register;
|
||||
|
||||
dec_5100_os_init();
|
||||
|
||||
sprintf(cpu_model, "DECsystem 5100 (MIPSMATE)");
|
||||
}
|
||||
|
||||
|
|
@ -115,29 +115,27 @@ dec_5100_os_init()
|
|||
{
|
||||
|
||||
/* set correct wbflush routine for this motherboard */
|
||||
mips_set_wbflush(dec_mips1_wbflush);
|
||||
mips_set_wbflush(kn230_wbflush);
|
||||
|
||||
/*
|
||||
* Set up interrupt handling and I/O addresses.
|
||||
*/
|
||||
mips_hardware_intr = dec_5100_intr;
|
||||
tc_enable_interrupt = dec_5100_enable_intr; /*XXX*/
|
||||
|
||||
/* NB: note inversion, ether, disk on hard int 1, tty on hard int 0 */
|
||||
Mach_splbio = Mach_spl1; /* just block hard int 1 */
|
||||
Mach_splnet = Mach_spl1; /* just block hard int 1 */
|
||||
Mach_spltty = cpu_spl1; /* block hard int 0 and 1 */
|
||||
Mach_splimp = cpu_spl3; /* block 0,1,2 */
|
||||
/* XXX blocks out reset button? */
|
||||
Mach_splclock = cpu_spl2;
|
||||
Mach_splstatclock = cpu_spl2;
|
||||
|
||||
mcclock_addr = (volatile struct chiptime *)
|
||||
MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK);
|
||||
mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_2);
|
||||
|
||||
/* no high resolution timer circuit; possibly never called */
|
||||
clkread = nullclkread;
|
||||
|
||||
splvec.splbio = MIPS_SPL1;
|
||||
splvec.splnet = MIPS_SPL1;
|
||||
splvec.spltty = MIPS_SPL_0_1;
|
||||
splvec.splimp = MIPS_SPL_0_1_2;
|
||||
splvec.splclock = MIPS_SPL_0_1_2;
|
||||
splvec.splstatclock = MIPS_SPL_0_1_2;
|
||||
|
||||
mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_2);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -153,7 +151,7 @@ dec_5100_bus_reset()
|
|||
*icsr_addr |= KN230_CSR_INTR_WMERR ;
|
||||
|
||||
/* nothing else to do */
|
||||
dec_mips1_wbflush();
|
||||
kn230_wbflush();
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -257,7 +255,7 @@ dec_5100_intr(mask, pc, statusReg, causeReg)
|
|||
}
|
||||
|
||||
/* If clock interrupts were enabled, re-enable them ASAP. */
|
||||
splx(MIPS_SR_INT_ENA_CUR | (statusReg & MIPS_INT_MASK_2));
|
||||
_splset(MIPS_SR_INT_IE | (statusReg & MIPS_INT_MASK_2));
|
||||
|
||||
#define CALLINTR(slot, icnt) \
|
||||
if (tc_slot_info[slot].intr) { \
|
||||
|
|
@ -291,7 +289,7 @@ dec_5100_intr(mask, pc, statusReg, causeReg)
|
|||
}
|
||||
|
||||
return ((statusReg & ~causeReg & MIPS_HARD_INT_MASK) |
|
||||
MIPS_SR_INT_ENA_CUR);
|
||||
MIPS_SR_INT_IE);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -313,7 +311,7 @@ dec_5100_memintr()
|
|||
/* read icsr and clear error */
|
||||
icsr = *icsr_addr;
|
||||
*icsr_addr = icsr | KN230_CSR_INTR_WMERR;
|
||||
dec_mips1_wbflush();
|
||||
kn230_wbflush();
|
||||
|
||||
#ifdef DIAGNOSTIC
|
||||
printf("\nMemory interrupt\n");
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: dec_maxine.c,v 1.11 1999/05/21 01:09:50 nisimura Exp $ */
|
||||
/* $NetBSD: dec_maxine.c,v 1.12 1999/05/25 04:17:57 nisimura Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
|
||||
|
|
@ -73,7 +73,7 @@
|
|||
|
||||
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
|
||||
|
||||
__KERNEL_RCSID(0, "$NetBSD: dec_maxine.c,v 1.11 1999/05/21 01:09:50 nisimura Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: dec_maxine.c,v 1.12 1999/05/25 04:17:57 nisimura Exp $");
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <sys/systm.h>
|
||||
|
|
@ -137,7 +137,7 @@ void
|
|||
dec_maxine_init()
|
||||
{
|
||||
|
||||
platform.iobus = "tcbus";
|
||||
platform.iobus = "tcmaxine";
|
||||
|
||||
platform.os_init = dec_maxine_os_init;
|
||||
platform.bus_reset = dec_maxine_bus_reset;
|
||||
|
|
@ -157,32 +157,25 @@ void
|
|||
dec_maxine_os_init()
|
||||
{
|
||||
/* clear any memory errors from probes */
|
||||
*(volatile u_int*)MIPS_PHYS_TO_KSEG1(XINE_REG_TIMEOUT) = 0;
|
||||
wbflush();
|
||||
*(volatile u_int *)MIPS_PHYS_TO_KSEG1(XINE_REG_TIMEOUT) = 0;
|
||||
kn02ca_wbflush();
|
||||
|
||||
ioasic_base = MIPS_PHYS_TO_KSEG1(XINE_SYS_ASIC);
|
||||
mips_hardware_intr = dec_maxine_intr;
|
||||
tc_enable_interrupt = dec_maxine_enable_intr;
|
||||
|
||||
/* On the MAXINE ioasic interrupts at level 3. */
|
||||
Mach_splbio = Mach_spl3;
|
||||
Mach_splnet = Mach_spl3;
|
||||
Mach_spltty = Mach_spl3;
|
||||
Mach_splimp = Mach_spl3;
|
||||
|
||||
/*
|
||||
* Note priority inversion of ioasic and clock:
|
||||
* clock interrupts are at hw priority 1, and when blocking
|
||||
* clock interrups we we must block hw priority 3
|
||||
* (bio,net,tty) also.
|
||||
*
|
||||
* XXX hw priority 2 is used for memory errors, we
|
||||
* should not disable memory errors during clock interrupts!
|
||||
*/
|
||||
Mach_splclock = cpu_spl3;
|
||||
Mach_splstatclock = cpu_spl3;
|
||||
mcclock_addr = (volatile struct chiptime *)
|
||||
MIPS_PHYS_TO_KSEG1(XINE_SYS_CLOCK);
|
||||
|
||||
/* MAXINE has 1 microsec. free-running high resolution timer */
|
||||
clkread = kn02ca_clkread;
|
||||
|
||||
splvec.splbio = MIPS_SPL3;
|
||||
splvec.splnet = MIPS_SPL3;
|
||||
splvec.spltty = MIPS_SPL3;
|
||||
splvec.splimp = MIPS_SPL3;
|
||||
splvec.splclock = MIPS_SPL_0_1_3;
|
||||
splvec.splstatclock = MIPS_SPL_0_1_3;
|
||||
|
||||
mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_1);
|
||||
|
||||
*(volatile u_int *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3;
|
||||
|
|
@ -196,11 +189,8 @@ dec_maxine_os_init()
|
|||
/*
|
||||
* Initialize interrupts.
|
||||
*/
|
||||
*(u_int *)IOASIC_REG_IMSK(ioasic_base) = XINE_IM0;
|
||||
*(u_int *)IOASIC_REG_INTR(ioasic_base) = 0;
|
||||
|
||||
/* MAXINE has 1 microsec. free-running high resolution timer */
|
||||
clkread = kn02ca_clkread;
|
||||
*(volatile u_int *)IOASIC_REG_IMSK(ioasic_base) = XINE_IM0;
|
||||
*(volatile u_int *)IOASIC_REG_INTR(ioasic_base) = 0;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -344,7 +334,7 @@ dec_maxine_intr(mask, pc, statusReg, causeReg)
|
|||
}
|
||||
|
||||
/* If clock interrups were enabled, re-enable them ASAP. */
|
||||
splx(MIPS_SR_INT_IE | (statusReg & MIPS_INT_MASK_1));
|
||||
_splset(MIPS_SR_INT_IE | (statusReg & MIPS_INT_MASK_1));
|
||||
|
||||
if (mask & MIPS_INT_MASK_3) {
|
||||
intr = *intrp;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: locore_machdep.S,v 1.11 1999/05/07 06:18:56 nisimura Exp $ */
|
||||
/* $NetBSD: locore_machdep.S,v 1.12 1999/05/25 04:17:57 nisimura Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
|
|
@ -148,6 +148,8 @@ END(CopyFromBuffer)
|
|||
*/
|
||||
#if defined(DEC_5100) || defined(DEC_5400)
|
||||
LEAF(dec_mips1_wbflush)
|
||||
ALEAF(kn230_wbflush)
|
||||
ALEAF(kn210_wbflush)
|
||||
mfc0 v0, MIPS_COP_0_STATUS_REG # save original SR in v0
|
||||
li t0, 0x80000000 # set CU3 bit
|
||||
or v1, v0 ,t0 # v1 = v0 | 0x80000000
|
||||
|
|
@ -167,284 +169,6 @@ LEAF(dec_mips1_wbflush)
|
|||
END(dec_mips1_wbflush)
|
||||
#endif /* defined(DEC_5100) || defined(DEC_5400) */
|
||||
|
||||
/*
|
||||
* Set/clear software interrupt routines.
|
||||
*/
|
||||
|
||||
LEAF(setsoftclock)
|
||||
mfc0 v1, MIPS_COP_0_STATUS_REG # save status register
|
||||
mtc0 zero, MIPS_COP_0_STATUS_REG # disable interrupts (2 cycles)
|
||||
nop
|
||||
mfc0 v0, MIPS_COP_0_CAUSE_REG # read cause register
|
||||
nop
|
||||
or v0, v0, MIPS_SOFT_INT_MASK_0 # set soft clock interrupt
|
||||
mtc0 v0, MIPS_COP_0_CAUSE_REG # save it
|
||||
mtc0 v1, MIPS_COP_0_STATUS_REG
|
||||
j ra
|
||||
nop
|
||||
END(setsoftclock)
|
||||
|
||||
LEAF(clearsoftclock)
|
||||
mfc0 v1, MIPS_COP_0_STATUS_REG # save status register
|
||||
mtc0 zero, MIPS_COP_0_STATUS_REG # disable interrupts (2 cycles)
|
||||
nop
|
||||
nop
|
||||
mfc0 v0, MIPS_COP_0_CAUSE_REG # read cause register
|
||||
nop
|
||||
and v0, v0, ~MIPS_SOFT_INT_MASK_0 # clear soft clock interrupt
|
||||
mtc0 v0, MIPS_COP_0_CAUSE_REG # save it
|
||||
mtc0 v1, MIPS_COP_0_STATUS_REG
|
||||
j ra
|
||||
nop
|
||||
END(clearsoftclock)
|
||||
|
||||
LEAF(setsoftnet)
|
||||
mfc0 v1, MIPS_COP_0_STATUS_REG # save status register
|
||||
mtc0 zero, MIPS_COP_0_STATUS_REG # disable interrupts (2 cycles)
|
||||
nop
|
||||
nop
|
||||
mfc0 v0, MIPS_COP_0_CAUSE_REG # read cause register
|
||||
nop
|
||||
or v0, v0, MIPS_SOFT_INT_MASK_1 # set soft net interrupt
|
||||
mtc0 v0, MIPS_COP_0_CAUSE_REG # save it
|
||||
mtc0 v1, MIPS_COP_0_STATUS_REG
|
||||
j ra
|
||||
nop
|
||||
END(setsoftnet)
|
||||
|
||||
LEAF(clearsoftnet)
|
||||
mfc0 v1, MIPS_COP_0_STATUS_REG # save status register
|
||||
mtc0 zero, MIPS_COP_0_STATUS_REG # disable interrupts (2 cycles)
|
||||
nop
|
||||
nop
|
||||
mfc0 v0, MIPS_COP_0_CAUSE_REG # read cause register
|
||||
nop
|
||||
and v0, v0, ~MIPS_SOFT_INT_MASK_1 # clear soft net interrupt
|
||||
mtc0 v0, MIPS_COP_0_CAUSE_REG # save it
|
||||
mtc0 v1, MIPS_COP_0_STATUS_REG
|
||||
j ra
|
||||
nop
|
||||
END(clearsoftnet)
|
||||
|
||||
/*
|
||||
* Set/change interrupt priority routines.
|
||||
*/
|
||||
|
||||
LEAF(spl0)
|
||||
ALEAF(spllow)
|
||||
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
|
||||
nop
|
||||
or t0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
|
||||
mtc0 t0, MIPS_COP_0_STATUS_REG # enable all interrupts
|
||||
j ra
|
||||
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
|
||||
END(spl0)
|
||||
|
||||
LEAF(splsoftclock)
|
||||
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
|
||||
li t0, ~MIPS_SOFT_INT_MASK_0 # disable soft clock
|
||||
and t0, t0, v0
|
||||
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
|
||||
nop # 3 ins to disable on r4x00
|
||||
j ra
|
||||
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
|
||||
END(splsoftclock)
|
||||
|
||||
LEAF(splsoftnet)
|
||||
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
|
||||
li t0, ~(MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
|
||||
and t0, t0, v0
|
||||
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
|
||||
j ra
|
||||
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
|
||||
END(splsoftnet)
|
||||
|
||||
/*
|
||||
* nesting interrupt masks.
|
||||
*/
|
||||
#define MIPS_INT_MASK_SPL_SOFT0 MIPS_SOFT_INT_MASK_0
|
||||
#define MIPS_INT_MASK_SPL_SOFT1 (MIPS_SOFT_INT_MASK_1|MIPS_INT_MASK_SPL_SOFT0)
|
||||
#define MIPS_INT_MASK_SPL0 (MIPS_INT_MASK_0|MIPS_INT_MASK_SPL_SOFT1)
|
||||
#define MIPS_INT_MASK_SPL1 (MIPS_INT_MASK_1|MIPS_INT_MASK_SPL0)
|
||||
#define MIPS_INT_MASK_SPL2 (MIPS_INT_MASK_2|MIPS_INT_MASK_SPL1)
|
||||
#define MIPS_INT_MASK_SPL3 (MIPS_INT_MASK_3|MIPS_INT_MASK_SPL2)
|
||||
#define MIPS_INT_MASK_SPL4 (MIPS_INT_MASK_4|MIPS_INT_MASK_SPL3)
|
||||
#define MIPS_INT_MASK_SPL5 (MIPS_INT_MASK_5|MIPS_INT_MASK_SPL4)
|
||||
|
||||
/*
|
||||
* hardware-level spls for hardware where the device interrupt priorites
|
||||
* are ordered, and map onto mips interrupt pins in increasing priority.
|
||||
* This maps directly onto BSD spl levels.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Block out int2 (hardware interrupt 0) and lower mips levels.
|
||||
*/
|
||||
LEAF(cpu_spl0)
|
||||
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
|
||||
li t0, ~(MIPS_INT_MASK_SPL0)
|
||||
and t0, t0, v0
|
||||
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
|
||||
nop # 3 ins to disable on r4x00
|
||||
j ra
|
||||
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
|
||||
END(cpu_spl0)
|
||||
|
||||
/*
|
||||
* Block out Int3 (hardware interrupt 1) and lower mips levels.
|
||||
*/
|
||||
LEAF(cpu_spl1)
|
||||
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
|
||||
li t0, ~(MIPS_INT_MASK_SPL1)
|
||||
and t0, t0, v0
|
||||
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
|
||||
nop # 3 ins to disable on r4x00
|
||||
j ra
|
||||
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
|
||||
END(cpu_spl1)
|
||||
|
||||
LEAF(cpu_spl2)
|
||||
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
|
||||
li t0, ~(MIPS_INT_MASK_SPL2)
|
||||
and t0, t0, v0
|
||||
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
|
||||
nop # 3 ins to disable on r4x00
|
||||
j ra
|
||||
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
|
||||
END(cpu_spl2)
|
||||
|
||||
LEAF(cpu_spl3)
|
||||
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
|
||||
li t0, ~(MIPS_INT_MASK_SPL3)
|
||||
and t0, t0, v0
|
||||
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
|
||||
nop # 3 ins to disable on r4x00
|
||||
j ra
|
||||
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
|
||||
END(cpu_spl3)
|
||||
|
||||
LEAF(cpu_spl4)
|
||||
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
|
||||
li t0, ~(MIPS_INT_MASK_SPL4)
|
||||
|
||||
and t0, t0, v0
|
||||
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
|
||||
nop # 3 ins to disable
|
||||
j ra
|
||||
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
|
||||
END(cpu_spl4)
|
||||
|
||||
LEAF(cpu_spl5)
|
||||
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
|
||||
li t0, ~(MIPS_INT_MASK_SPL5)
|
||||
and t0, t0, v0
|
||||
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
|
||||
nop # 3 ins to disable
|
||||
j ra
|
||||
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
|
||||
END(cpu_spl5)
|
||||
|
||||
/*
|
||||
* hardware-level spls for hardware where the interrupt priorites
|
||||
* DO NOT map onto levels.
|
||||
*
|
||||
* For now, that means DECstations that use only two distinct CPU
|
||||
* levels, one for TOD clock interrupts, and a second for all other
|
||||
* external devices (via an external controller.
|
||||
* XXX the spl handling really needs re-writing from scratch.
|
||||
*/
|
||||
LEAF(Mach_spl0)
|
||||
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
|
||||
li t0, ~(MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
|
||||
and t0, t0, v0
|
||||
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
|
||||
nop # 3 ins to disable on r4x00
|
||||
j ra
|
||||
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
|
||||
END(Mach_spl0)
|
||||
|
||||
LEAF(Mach_spl1)
|
||||
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
|
||||
li t0, ~(MIPS_INT_MASK_1|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
|
||||
and t0, t0, v0
|
||||
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
|
||||
nop # 3 ins to disable on r4x00
|
||||
j ra
|
||||
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
|
||||
END(Mach_spl1)
|
||||
|
||||
LEAF(Mach_spl2)
|
||||
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
|
||||
li t0, ~(MIPS_INT_MASK_2|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
|
||||
and t0, t0, v0
|
||||
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
|
||||
nop # 3 ins to disable on r4x00
|
||||
j ra
|
||||
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
|
||||
END(Mach_spl2)
|
||||
|
||||
LEAF(Mach_spl3)
|
||||
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
|
||||
li t0, ~(MIPS_INT_MASK_3|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
|
||||
and t0, t0, v0
|
||||
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
|
||||
nop # 3 ins to disable on r4x00
|
||||
j ra
|
||||
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
|
||||
END(Mach_spl3)
|
||||
|
||||
LEAF(Mach_spl4)
|
||||
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
|
||||
li t0, ~(MIPS_INT_MASK_4|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
|
||||
and t0, t0, v0
|
||||
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
|
||||
nop # 3 ins to disable
|
||||
j ra
|
||||
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
|
||||
END(Mach_spl4)
|
||||
|
||||
LEAF(Mach_spl5)
|
||||
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
|
||||
li t0, ~(MIPS_INT_MASK_5|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
|
||||
and t0, t0, v0
|
||||
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
|
||||
nop # 3 ins to disable
|
||||
j ra
|
||||
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
|
||||
END(Mach_spl5)
|
||||
|
||||
|
||||
/*
|
||||
* We define an alternate entry point after mcount is called so it
|
||||
* can be used in mcount without causeing a recursive loop.
|
||||
*/
|
||||
LEAF(splhigh)
|
||||
ALEAF(_splhigh)
|
||||
mfc0 v0, MIPS_COP_0_STATUS_REG # read status register
|
||||
li t0, ~MIPS_SR_INT_IE # disable all interrupts
|
||||
and t0, t0, v0
|
||||
mtc0 t0, MIPS_COP_0_STATUS_REG # save it
|
||||
nop # 3 ins to disable on r4x00
|
||||
j ra
|
||||
and v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
|
||||
END(splhigh)
|
||||
|
||||
/*
|
||||
* Restore saved interrupt mask.
|
||||
*/
|
||||
LEAF(splx)
|
||||
ALEAF(_splx)
|
||||
mfc0 v0, MIPS_COP_0_STATUS_REG
|
||||
li t0, ~(MIPS_INT_MASK | MIPS_SR_INT_IE)
|
||||
and t0, t0, v0
|
||||
or t0, t0, a0
|
||||
mtc0 t0, MIPS_COP_0_STATUS_REG
|
||||
nop # 3 ins to disable
|
||||
j ra
|
||||
nop
|
||||
.globl _C_LABEL(splx_end)
|
||||
_C_LABEL(splx_end):
|
||||
END(splx)
|
||||
/*
|
||||
* Interrupt counters for vmstat.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: machdep.c,v 1.143 1999/05/20 08:21:46 lukem Exp $ */
|
||||
/* $NetBSD: machdep.c,v 1.144 1999/05/25 04:17:57 nisimura Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1988 University of Utah.
|
||||
|
|
@ -43,7 +43,7 @@
|
|||
|
||||
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
|
||||
|
||||
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.143 1999/05/20 08:21:46 lukem Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.144 1999/05/25 04:17:57 nisimura Exp $");
|
||||
|
||||
/* from: Utah Hdr: machdep.c 1.63 91/04/24 */
|
||||
|
||||
|
|
@ -126,6 +126,8 @@ phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX];
|
|||
*/
|
||||
int safepri = MIPS3_PSL_LOWIPL; /* XXX */
|
||||
|
||||
struct splvec splvec; /* XXX will go XXX */
|
||||
|
||||
void mach_init __P((int, char *[], int, int, u_int, char *));
|
||||
|
||||
unsigned (*clkread) __P((void)); /* high resolution timer if available */
|
||||
|
|
@ -145,20 +147,6 @@ void (*tc_enable_interrupt)
|
|||
__P ((u_int slotno, int (*handler) __P((void *sc)),
|
||||
void *sc, int onoff));
|
||||
|
||||
#include <pmax/pmax/machdep.h> /* splXXX() function pointer hack */
|
||||
/*
|
||||
* pmax still doesnt have code to build spl masks for both CPU hard-interrupt
|
||||
* register and baseboard interrupt-control registers at runtime.
|
||||
* Instead, we declare the standard splXXX names as function pointers,
|
||||
* and initialie them to point to the above functions to match
|
||||
* the way a specific motherboard is wired up.
|
||||
*/
|
||||
int (*Mach_splbio) __P((void)) = splhigh;
|
||||
int (*Mach_splnet)__P((void)) = splhigh;
|
||||
int (*Mach_spltty)__P((void)) = splhigh;
|
||||
int (*Mach_splimp)__P((void)) = splhigh;
|
||||
int (*Mach_splclock)__P((void)) = splhigh;
|
||||
int (*Mach_splstatclock)__P((void)) = splhigh;
|
||||
volatile struct chiptime *mcclock_addr;
|
||||
/*XXXjrs*/
|
||||
const struct callback *callv; /* pointer to PROM entry points */
|
||||
|
|
|
|||
Loading…
Reference in New Issue