Re-write ASI load/stores to use full 64-bit addresses so we can use device
register addresses with MMU bypass ASIs.
This commit is contained in:
eeh
parent
c2f2c064c0
commit
cd53dbd506
@ -1,4 +1,4 @@
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/* $NetBSD: ctlreg.h,v 1.8 1999/05/22 20:25:49 eeh Exp $ */
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/* $NetBSD: ctlreg.h,v 1.9 1999/05/30 19:11:33 eeh Exp $ */
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/*
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* Copyright (c) 1996
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@ -375,6 +375,7 @@
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#define SET_SOFTINT %asr20 /* Sets these bits */
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#define CLEAR_SOFTINT %asr21 /* Clears these bits */
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#define SOFTINT %asr22 /* Reads the register */
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#define TICK_CMPR %asr23
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#define TICK_INT 0x01 /* level-14 clock tick */
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#define SOFTINT1 (0x1<<1)
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@ -456,6 +457,7 @@
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/* DCACHE_BUG forces a flush of the D$ line on every ASI load */
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#define DCACHE_BUG
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#ifdef __arch64__
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/* load byte from alternate address space */
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#ifdef DCACHE_BUG
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#define lduba(loc, asi) ({ \
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@ -463,11 +465,11 @@
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if (asi == ASI_PHYS_CACHED) { \
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__asm __volatile("wr %2,%%g0,%%asi; " \
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" andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \
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" lduba [%1]%%asi,%0" : "=r" (_lduba_v) : \
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" lduba [%1]%%asi,%0" : "=&r" (_lduba_v) : \
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"r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \
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} else { \
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__asm __volatile("wr %2,%%g0,%%asi; lduba [%1]%%asi,%0" : \
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"=r" (_lduba_v) : "r" ((long)(loc)), "r" (asi)); \
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__asm __volatile("wr %2,%%g0,%%asi; lduba [%1]%%asi,%0" : "=r" (_lduba_v) : \
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"r" ((long)(loc)), "r" (asi)); \
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} \
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_lduba_v; \
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})
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@ -479,7 +481,38 @@
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_lduba_v; \
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})
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#endif
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#else
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/* load byte from alternate address space */
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#ifdef DCACHE_BUG
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#define lduba(loc, asi) ({ \
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register int _lduba_v, _loc_hi; \
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_loc_hi = (((u_int64_t)loc)>>32); \
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if (asi == ASI_PHYS_CACHED) { \
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__asm __volatile("wr %3,%%g0,%%asi; " \
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" andn %1,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " \
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" sllx %2,32,%0; or %0,%1,%0; lduba [%0]%%asi,%0" : "=&r" (_lduba_v) : \
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"r" ((long)(loc)), "r" (_loc_hi), \
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"r" (asi), "n" (ASI_DCACHE_TAG)); \
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} else { \
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__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
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" or %0,%1,%0; lduba [%0]%%asi,%0" : "=&r" (_lduba_v) : \
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"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
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} \
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_lduba_v; \
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})
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#else
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#define lduba(loc, asi) ({ \
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register int _lduba_v, _loc_hi; \
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_loc_hi = (((u_int64_t)loc)>>32); \
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__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
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" or %0,%1,%0; lduba [%0]%%asi,%0" : "=&r" (_lduba_v) : \
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"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
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_lduba_v; \
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})
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#endif
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#endif
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#ifdef __arch64__
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/* load half-word from alternate address space */
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#ifdef DCACHE_BUG
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#define lduha(loc, asi) ({ \
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@ -487,7 +520,7 @@
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if (asi == ASI_PHYS_CACHED) { \
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__asm __volatile("wr %2,%%g0,%%asi; " \
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" andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \
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" lduha [%1]%%asi,%0" : "=r" (_lduha_v) : \
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" lduha [%1]%%asi,%0" : "=&r" (_lduha_v) : \
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"r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \
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} else { \
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__asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0" : "=r" (_lduha_v) : \
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@ -503,7 +536,38 @@
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_lduha_v; \
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})
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#endif
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#else
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/* load half-word from alternate address space */
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#ifdef DCACHE_BUG
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#define lduha(loc, asi) ({ \
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register int _lduha_v, _loc_hi; \
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_loc_hi = (((u_int64_t)loc)>>32); \
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if (asi == ASI_PHYS_CACHED) { \
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__asm __volatile("wr %3,%%g0,%%asi; " \
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" andn %1,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " \
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" sllx %2,32,%0; or %0,%1,%0; lduha [%0]%%asi,%0" : "=&r" (_lduha_v) : \
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"r" ((long)(loc)), "r" (_loc_hi), \
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"r" (asi), "n" (ASI_DCACHE_TAG)); \
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} else { \
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__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
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" or %0,%1,%0; lduha [%0]%%asi,%0" : "=&r" (_lduha_v) : \
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"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
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} \
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_lduha_v; \
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})
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#else
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#define lduha(loc, asi) ({ \
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register int _lduha_v, _loc_hi; \
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_loc_hi = (((u_int64_t)loc)>>32); \
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__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
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" or %0,%1,%0; lduha [%0]%%asi,%0" : "=&r" (_lduha_v) : \
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"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
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_lduha_v; \
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})
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#endif
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#endif
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#ifdef __arch64__
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/* load unsigned int from alternate address space */
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#ifdef DCACHE_BUG
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#define lda(loc, asi) ({ \
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@ -511,7 +575,7 @@
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if (asi == ASI_PHYS_CACHED) { \
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__asm __volatile("wr %2,%%g0,%%asi; " \
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" andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \
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" lda [%1]%%asi,%0" : "=r" (_lda_v) : \
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" lda [%1]%%asi,%0" : "=&r" (_lda_v) : \
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"r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \
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} else { \
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__asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" : "=r" (_lda_v) : \
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@ -526,7 +590,7 @@
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if (asi == ASI_PHYS_CACHED) { \
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__asm __volatile("wr %2,%%g0,%%asi; " \
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" andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \
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" ldswa [%1]%%asi,%0" : "=r" (_lda_v) : \
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" ldswa [%1]%%asi,%0" : "=&r" (_lda_v) : \
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"r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \
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} else { \
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__asm __volatile("wr %2,%%g0,%%asi; ldswa [%1]%%asi,%0" : "=r" (_lda_v) : \
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@ -549,16 +613,74 @@
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_lda_v; \
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})
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#endif
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#else /* __arch64__ */
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/* load unsigned int from alternate address space */
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#ifdef DCACHE_BUG
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#define lda(loc, asi) ({ \
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register int _lda_v, _loc_hi; \
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_loc_hi = (((u_int64_t)loc)>>32); \
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if (asi == ASI_PHYS_CACHED) { \
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__asm __volatile("wr %3,%%g0,%%asi; " \
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" andn %1,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " \
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" sllx %2,32,%0; or %0,%1,%0; lda [%1]%%asi,%0" : "=&r" (_lda_v) : \
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"r" ((long)(loc)), "r" (_loc_hi), \
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"r" (asi), "n" (ASI_DCACHE_TAG)); \
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} else { \
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__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
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" or %0,%1,%0; lda [%0]%%asi,%0" : "=&r" (_lda_v) : \
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"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
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} \
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_lda_v; \
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})
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/* load signed int from alternate address space */
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#define ldswa(loc, asi) ({ \
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register int _lda_v, _loc_hi; \
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_loc_hi = (((u_int64_t)loc)>>32); \
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if (asi == ASI_PHYS_CACHED) { \
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__asm __volatile("wr %3,%%g0,%%asi; " \
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" andn %1,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " \
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" sllx %2,32,%0; or %0,%1,%0; ldswa [%1]%%asi,%0" : "=&r" (_lda_v) : \
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"r" ((long)(loc)), "r" (_loc_hi), \
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"r" (asi), "n" (ASI_DCACHE_TAG)); \
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} else { \
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__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
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" or %0,%1,%0; ldswa [%0]%%asi,%0" : "=&r" (_lda_v) : \
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"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
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} \
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_lda_v; \
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})
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#else
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#define lda(loc, asi) ({ \
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register int _lda_v, _loc_hi; \
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_loc_hi = (((u_int64_t)loc)>>32); \
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__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
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" or %0,%1,%0; lda [%0]%%asi,%0" : "=&r" (_lda_v) : \
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"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
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_lda_v; \
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})
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#define ldswa(loc, asi) ({ \
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register int _lda_v, _loc_hi; \
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_loc_hi = (((u_int64_t)loc)>>32); \
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__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
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" or %0,%1,%0; ldswa [%0]%%asi,%0" : "=&r" (_lda_v) : \
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"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
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_lda_v; \
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})
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#endif
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#endif /* __arch64__ */
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#ifdef DCACHE_BUG
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#ifdef __arch64__
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/* load 64-bit int from alternate address space */
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#define ldda(loc, asi) ({ \
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register long long _lda_v; \
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if (asi == ASI_PHYS_CACHED) { \
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__asm __volatile("wr %2,%%g0,%%asi; " \
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" andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \
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" ldda [%1]%%asi,%0" : "=r" (_lda_v) : \
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" ldda [%1]%%asi,%0" : "=&r" (_lda_v) : \
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"r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \
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} else { \
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__asm __volatile("wr %2,%%g0,%%asi; ldda [%1]%%asi,%0" : "=r" (_lda_v) : \
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@ -566,6 +688,24 @@
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} \
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_lda_v; \
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})
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#else
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/* load 64-bit int from alternate address space */
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#define ldda(loc, asi) ({ \
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register long long _lda_v, _loc_hi; \
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_loc_hi = (((u_int64_t)loc)>>32); \
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if (asi == ASI_PHYS_CACHED) { \
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__asm __volatile("wr %3,%%g0,%%asi; " \
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" andn %1,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " \
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" sllx %2,32,%0; or %0,%1,%0; ldda [%0]%%asi,%0" : "=&r" (_lda_v) : \
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"r" ((long)(loc)), "r" (_loc_hi), "r" (asi), "n" (ASI_DCACHE_TAG)); \
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} else { \
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__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
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" or %0,%1,%0; ldda [%0]%%asi,%0" : "=&r" (_lda_v) : \
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"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
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} \
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_lda_v; \
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})
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#endif
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#ifdef __arch64__
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/* native load 64-bit int from alternate address space w/64-bit compiler*/
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@ -574,7 +714,7 @@
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if (asi == ASI_PHYS_CACHED) { \
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__asm __volatile("wr %2,%%g0,%%asi; "\
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" andn %1,0x1f,%0; stxa %%g0,[%0] %3; membar #Sync; " \
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" ldxa [%1]%%asi,%0" : "=r" (_lda_v) : \
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" ldxa [%1]%%asi,%0" : "=&r" (_lda_v) : \
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"r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \
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} else { \
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__asm __volatile("wr %2,%%g0,%%asi; ldxa [%1]%%asi,%0" : "=r" (_lda_v) : \
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@ -585,17 +725,21 @@
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#else
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/* native load 64-bit int from alternate address space w/32-bit compiler*/
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#define ldxa(loc, asi) ({ \
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volatile register long _ldxa_lo, _ldxa_hi; \
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volatile register long _ldxa_lo, _ldxa_hi, _loc_hi; \
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_loc_hi = (((u_int64_t)loc)>>32); \
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if (asi == ASI_PHYS_CACHED) { \
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__asm __volatile("wr %3,%%g0,%%asi; " \
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" andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; " \
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" ldxa [%2]%%asi,%0; srlx %0,32,%1; srl %0,0,%0" : \
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"=r" (_ldxa_lo), "=r" (_ldxa_hi) : \
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"r" ((long)(loc)), "r" (asi), "n" (ASI_DCACHE_TAG)); \
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__asm __volatile("wr %4,%%g0,%%asi; " \
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" andn %2,0x1f,%0; stxa %%g0,[%0] %5; membar #Sync; " \
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" sllx %2,32,%0; or %0,%1,%0; ldxa [%0]%%asi,%0; " \
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" srlx %0,32,%1; srl %0,0,%0" : \
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"=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \
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"r" ((long)(loc)), "r" (_loc_hi), \
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"r" (asi), "n" (ASI_DCACHE_TAG)); \
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} else { \
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__asm __volatile("wr %3,%%g0,%%asi; ldxa [%2]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \
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"=r" (_ldxa_lo), "=r" (_ldxa_hi) : \
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"r" ((long)(loc)), "r" (asi)); \
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__asm __volatile("wr %4,%%g0,%%asi; sllx %2,32,%0; " \
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" or %0,%1,%0; ldxa [%2]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \
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"=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \
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"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
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} \
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((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); \
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})
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@ -603,6 +747,7 @@
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#else
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#ifdef __arch64__
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/* load 64-bit int from alternate address space */
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#define ldda(loc, asi) ({ \
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register long long _lda_v; \
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@ -610,6 +755,16 @@
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"r" ((long)(loc)), "r" (asi)); \
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_lda_v; \
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})
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#else
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#define ldda(loc, asi) ({ \
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register long long _lda_v, _loc_hi; \
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_loc_hi = (((u_int64_t)loc)>>32); \
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__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
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" or %0,%1,%0; ldda [%0]%%asi,%0" : "=&r" (_lda_v) : \
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"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
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_lda_v; \
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})
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#endif
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#ifdef __arch64__
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/* native load 64-bit int from alternate address space w/64-bit compiler*/
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@ -622,10 +777,12 @@
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#else
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/* native load 64-bit int from alternate address space w/32-bit compiler*/
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#define ldxa(loc, asi) ({ \
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volatile register long _ldxa_lo, _ldxa_hi; \
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__asm __volatile("wr %3,%%g0,%%asi; ldxa [%2]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \
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"=r" (_ldxa_lo), "=r" (_ldxa_hi) : \
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"r" ((long)(loc)), "r" (asi)); \
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volatile register long _ldxa_lo, _ldxa_hi, _loc_hi; \
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_loc_hi = (((u_int64_t)loc)>>32); \
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__asm __volatile("wr %4,%%g0,%%asi; sllx %2,32,%0; " \
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" or %0,%1,%0; ldxa [%2]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \
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"=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \
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"r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
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((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); \
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})
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#endif
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@ -633,28 +790,68 @@
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/* store byte to alternate address space */
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#ifdef __arch64__
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#define stba(loc, asi, value) ({ \
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__asm __volatile("wr %2,%%g0,%%asi; stba %0,[%1]%%asi" : : \
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"r" ((int)(value)), "r" ((long)(loc)), "r" (asi)); \
|
||||
})
|
||||
#else
|
||||
#define stba(loc, asi, value) ({ \
|
||||
register int _loc_hi; \
|
||||
_loc_hi = (((u_int64_t)loc)>>32); \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
|
||||
" or %2,%0,%0; stba %1,[%0]%%asi" : "=&r" (_loc_hi) : \
|
||||
"r" ((int)(value)), "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
})
|
||||
#endif
|
||||
|
||||
/* store half-word to alternate address space */
|
||||
#ifdef __arch64__
|
||||
#define stha(loc, asi, value) ({ \
|
||||
__asm __volatile("wr %2,%%g0,%%asi; stha %0,[%1]%%asi" : : \
|
||||
"r" ((int)(value)), "r" ((long)(loc)), "r" (asi)); \
|
||||
})
|
||||
#else
|
||||
#define stha(loc, asi, value) ({ \
|
||||
register int _loc_hi; \
|
||||
_loc_hi = (((u_int64_t)loc)>>32); \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
|
||||
" or %2,%0,%0; stha %1,[%0]%%asi" : "=&r" (_loc_hi) : \
|
||||
"r" ((int)(value)), "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
})
|
||||
#endif
|
||||
|
||||
/* store int to alternate address space */
|
||||
#ifdef __arch64__
|
||||
#define sta(loc, asi, value) ({ \
|
||||
__asm __volatile("wr %2,%%g0,%%asi; sta %0,[%1]%%asi" : : \
|
||||
"r" ((int)(value)), "r" ((long)(loc)), "r" (asi)); \
|
||||
})
|
||||
#else
|
||||
#define sta(loc, asi, value) ({ \
|
||||
register int _loc_hi; \
|
||||
_loc_hi = (((u_int64_t)loc)>>32); \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
|
||||
" or %2,%0,%0; sta %1,[%0]%%asi" : "=&r" (_loc_hi) : \
|
||||
"r" ((int)(value)), "r" ((int)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
})
|
||||
#endif
|
||||
|
||||
/* store 64-bit int to alternate address space */
|
||||
#ifdef __arch64__
|
||||
#define stda(loc, asi, value) ({ \
|
||||
__asm __volatile("wr %2,%%g0,%%asi; stda %0,[%1]%%asi" : : \
|
||||
"r" ((long long)(value)), "r" ((long)(loc)), "r" (asi)); \
|
||||
})
|
||||
#else
|
||||
#define stda(loc, asi, value) ({ \
|
||||
register int _loc_hi; \
|
||||
_loc_hi = (((u_int64_t)loc)>>32); \
|
||||
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
|
||||
" or %2,%0,%0; stda %1,[%0]%%asi" : "=&r" (_loc_hi) : \
|
||||
"r" ((long long)(value)), "r" ((int)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
})
|
||||
#endif
|
||||
|
||||
#ifdef __arch64__
|
||||
/* native store 64-bit int to alternate address space w/64-bit compiler*/
|
||||
@ -665,11 +862,14 @@
|
||||
#else
|
||||
/* native store 64-bit int to alternate address space w/32-bit compiler*/
|
||||
#define stxa(loc, asi, value) ({ \
|
||||
int64_t _stxa_v; \
|
||||
int64_t *_stxa_a = &_stxa_v; \
|
||||
_stxa_v = value; \
|
||||
__asm __volatile("wr %2,%%g0,%%asi; ldx [%0],%3; stxa %3,[%1]%%asi" : : \
|
||||
"r" ((long)(_stxa_a)), "r" ((long)(loc)), "r" (asi), "r" ((long)(_stxa_v))); \
|
||||
int _stxa_lo, _stxa_hi, _loc_hi; \
|
||||
_stxa_lo = value; _stxa_hi = ((u_int64_t)value)>>32; \
|
||||
_loc_hi = (((u_int64_t)loc)>>32); \
|
||||
__asm __volatile("wr %6,%%g0,%%asi; sllx %3,32,%1; sllx %5,32,%0; " \
|
||||
" or %1,%2,%1; or %0,%4,%0; stxa %1,[%0]%%asi" : \
|
||||
"=&r" (_loc_hi), "=&r" (_stxa_hi) : \
|
||||
"r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), \
|
||||
"r" ((int)(loc)), "r" (_loc_hi), "r" (asi)); \
|
||||
})
|
||||
#endif
|
||||
|
||||
@ -727,7 +927,7 @@
|
||||
_tick_tmp; \
|
||||
})
|
||||
#else
|
||||
/* native load 64-bit int from alternate address space w/32-bit compiler*/
|
||||
/* read 64-bit %tick register on 32-bit system */
|
||||
#define tick() ({ \
|
||||
volatile register u_long _tick_tmp = 0; \
|
||||
volatile u_int64_t _tick_v; \
|
||||
@ -738,3 +938,6 @@
|
||||
})
|
||||
#endif
|
||||
|
||||
#ifndef _LOCORE
|
||||
extern next_tick __P((long));
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user