If TLB entries need to be flushed, make sure to do this after any necessary
cache flushes, since on VIPT machines the cache flush may induce a TLB load.
This commit is contained in:
pk
parent
4655ae1230
commit
1040b9e209
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.144 1999/05/16 16:48:59 pk Exp $ */
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/* $NetBSD: pmap.c,v 1.145 1999/05/20 10:03:12 pk Exp $ */
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/*
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* Copyright (c) 1996
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@ -524,7 +524,7 @@ void (*pmap_rmu_p) __P((struct pmap *, vaddr_t, vaddr_t, int, int));
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* Macros which implement SRMMU TLB flushing/invalidation
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*/
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#define tlb_flush_page(va) \
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sta(((va) & ~0xfff) | ASI_SRMMUFP_L3, ASI_SRMMUFP, 0)
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sta(((vaddr_t)(va) & ~0xfff) | ASI_SRMMUFP_L3, ASI_SRMMUFP, 0)
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#define tlb_flush_segment(vr, vs) \
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sta(((vr)<<RGSHIFT) | ((vs)<<SGSHIFT) | ASI_SRMMUFP_L2, ASI_SRMMUFP,0)
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@ -628,6 +628,7 @@ setpgt4m(ptep, pte)
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#endif
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}
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/*
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* Set the page table entry for va to pte. Only affects software MMU page-
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* tables (the in-core pagetables read by the MMU). Ignores TLB, and
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@ -1714,11 +1715,17 @@ mmu_pagein(pm, va, prot)
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#ifdef DEBUG
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if (pm == pmap_kernel())
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printf("mmu_pagein: kernel wants map at va 0x%x, vr %d, vs %d\n", va, vr, vs);
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#endif
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#if 0
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#if defined(SUN4_MMU3L)
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printf("mmu_pagein: pm=%p, va 0x%x, vr %d, vs %d, rp=%p, segmap=%p\n", pm, va, vr, vs, rp, rp->rg_segmap);
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#endif
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#endif
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/* return 0 if we have no PMEGs to load */
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if (rp->rg_segmap == NULL)
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return (0);
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#if defined(SUN4_MMU3L)
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if (HASSUN4_MMU3L && rp->rg_smeg == reginval) {
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smeg_t smeg;
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@ -2472,8 +2479,13 @@ pv_syncflags4m(pv0)
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flags |= MR4M(tpte);
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if (pm->pm_ctx && (tpte & SRMMU_PG_M)) {
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cache_flush_page(va); /* XXX: do we need this?*/
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tlb_flush_page(va); /* paranoid? */
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/* Only do this for write-back caches? */
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cache_flush_page(va);
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/*
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* VIPT caches might use the TLB when
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* flushing, so we flush the TLB again.
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*/
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tlb_flush_page(va);
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}
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/* Clear mod/ref bits from PTE and write it back */
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@ -2641,6 +2653,10 @@ pv_flushcache(pv)
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if (pm->pm_ctx) {
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setcontext(pm->pm_ctxnum);
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cache_flush_page(pv->pv_va);
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#if defined(SUN4M)
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if (CPU_ISSUN4M)
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tlb_flush_page(pv->pv_va);
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#endif
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}
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pv = pv->pv_next;
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if (pv == NULL)
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@ -4229,7 +4245,7 @@ pmap_rmk4m(pm, va, endva, vr, vs)
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}
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/* if we're done with a region, leave it wired */
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}
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#endif /* sun4m */
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#endif /* SUN4M */
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/*
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* Just like pmap_rmk_magic, but we have a different threshold.
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* Note that this may well deserve further tuning work.
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@ -4459,9 +4475,6 @@ pmap_rmu4m(pm, va, endva, vr, vs)
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for (; va < endva; va += NBPG) {
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int tpte;
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if (pm->pm_ctx)
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tlb_flush_page(va);
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tpte = pte0[VA_SUN4M_VPG(va)];
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if ((tpte & SRMMU_TETYPE) != SRMMU_TEPTE) {
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@ -4492,6 +4505,9 @@ pmap_rmu4m(pm, va, endva, vr, vs)
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panic("pmap_rmu: too many PTEs in segment; "
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"va 0x%lx; endva 0x%lx", va, endva);
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#endif
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if (pm->pm_ctx)
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tlb_flush_page(va);
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setpgt4m(&pte0[VA_SUN4M_VPG(va)], SRMMU_TEINVALID);
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}
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@ -5072,8 +5088,8 @@ pmap_protect4m(pm, sva, eva, prot)
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vaddr_t sva, eva;
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vm_prot_t prot;
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{
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int va, nva, vr, vs;
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int s, ctx;
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vaddr_t va, nva;
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int s, ctx, vr, vs;
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struct regmap *rp;
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struct segmap *sp;
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@ -5085,6 +5101,13 @@ pmap_protect4m(pm, sva, eva, prot)
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return;
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}
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#ifdef DEBUG
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if (pmapdebug & PDB_CHANGEPROT)
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printf("pmap_protect[curpid %d, ctx %d](%lx, %lx, %x)\n",
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curproc==NULL ? -1 : curproc->p_pid,
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pm->pm_ctx ? pm->pm_ctxnum : -1, sva, eva, prot);
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#endif
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write_user_windows();
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ctx = getcontext4m();
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s = splpmap();
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@ -5116,7 +5139,9 @@ pmap_protect4m(pm, sva, eva, prot)
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if (sp->sg_pte == NULL)
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panic("pmap_protect: no pages");
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#endif
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/* pages loaded: take away write bits from MMU PTEs */
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/*
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* pages loaded: take away write bits from MMU PTEs
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*/
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if (pm->pm_ctx)
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setcontext4m(pm->pm_ctxnum);
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@ -5124,11 +5149,6 @@ pmap_protect4m(pm, sva, eva, prot)
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for (; va < nva; va += NBPG) {
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int tpte;
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if (pm->pm_ctx) {
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/* Flush TLB entry */
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tlb_flush_page(va);
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}
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tpte = sp->sg_pte[VA_SUN4M_VPG(va)];
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/*
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* Flush cache so that any existing cache
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@ -5140,6 +5160,8 @@ pmap_protect4m(pm, sva, eva, prot)
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pmap_stats.ps_npg_prot_actual++;
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if (pm->pm_ctx) {
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cache_flush_page(va);
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/* Flush TLB entry */
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tlb_flush_page(va);
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}
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setpgt4m(&sp->sg_pte[VA_SUN4M_VPG(va)],
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tpte & ~PPROT_WRITE);
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@ -5188,14 +5210,7 @@ pmap_changeprot4m(pm, va, prot, wired)
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rp = &pm->pm_regmap[VA_VREG(va)];
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sp = &rp->rg_segmap[VA_VSEG(va)];
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ctx = getcontext4m();
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if (pm->pm_ctx) {
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/* Flush TLB entry */
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setcontext4m(pm->pm_ctxnum);
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tlb_flush_page(va);
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}
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pte = sp->sg_pte[VA_SUN4M_VPG(va)];
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if ((pte & SRMMU_PROT_MASK) == newprot) {
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/* only wiring changed, and we ignore wiring */
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pmap_stats.ps_useless_changeprots++;
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@ -5208,18 +5223,24 @@ pmap_changeprot4m(pm, va, prot, wired)
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* Flush cache if page has been referenced to
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* avoid stale protection bits in the cache tags.
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*/
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ctx = getcontext4m();
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setcontext4m(pm->pm_ctxnum);
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if ((pte & (SRMMU_PG_C|SRMMU_PGTYPE)) ==
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(SRMMU_PG_C|PG_SUN4M_OBMEM))
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cache_flush_page(va);
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tlb_flush_page(va);
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setcontext4m(ctx);
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}
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setpgt4m(&sp->sg_pte[VA_SUN4M_VPG(va)],
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(pte & ~SRMMU_PROT_MASK) | newprot);
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out:
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setcontext4m(ctx);
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splx(s);
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}
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#endif /* 4m */
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#endif /* SUN4M */
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/*
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* Insert (MI) physical page pa at virtual address va in the given pmap.
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@ -5473,6 +5494,7 @@ printf("pmap_enter: segment filled during sleep\n"); /* can this happen? */
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rp->rg_nsegmap = 0;
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for (i = NSEGRG; --i >= 0;)
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sp++->sg_pmeg = seginval;
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#if defined(SUN4_MMU3L)
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/*
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* XXX - preallocate the region MMU cookies.
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@ -5640,8 +5662,11 @@ pmap_enter4m(pm, va, pa, prot, wired, access_type)
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#ifdef DEBUG
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if (pmapdebug & PDB_ENTER)
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printf("pmap_enter(%p, 0x%lx, 0x%lx, 0x%x, 0x%x)\n",
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pm, va, pa, prot, wired);
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printf("pmap_enter[curpid %d, ctx %d]"
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"(%p, 0x%lx, 0x%lx, 0x%x, 0x%x)\n",
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curproc==NULL ? -1 : curproc->p_pid,
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pm->pm_ctx==NULL ? -1 : pm->pm_ctxnum,
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pm, va, pa, prot, wired);
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#endif
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/* Initialise pteproto with cache bit */
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@ -5928,7 +5953,7 @@ printf("%s[%d]: pmap_enu: changing existing va 0x%x: pte 0x%x=>0x%x\n",
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splx(s);
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}
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#endif /* sun4m */
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#endif /* SUN4M */
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/*
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* Change the wiring attribute for a map/virtual-address pair.
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@ -6045,7 +6070,7 @@ pmap_extract4m(pm, va)
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if ((rm = pm->pm_regmap) == NULL) {
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#ifdef DEBUG
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if (pmapdebug & PDB_FOLLOW)
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printf("pmap_extract: no regmap entry");
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printf("pmap_extract: no regmap entry\n");
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#endif
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return (0);
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}
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@ -6054,7 +6079,7 @@ pmap_extract4m(pm, va)
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if ((sm = rm->rg_segmap) == NULL) {
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#ifdef DEBUG
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if (pmapdebug & PDB_FOLLOW)
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panic("pmap_extract: no segmap");
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printf("pmap_extract: no segmap\n");
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#endif
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return (0);
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}
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@ -6063,7 +6088,7 @@ pmap_extract4m(pm, va)
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if (sm->sg_pte == NULL) {
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#ifdef DEBUG
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if (pmapdebug & PDB_FOLLOW)
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panic("pmap_extract: no ptes");
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printf("pmap_extract: no ptes\n");
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#endif
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return (0);
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}
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@ -6410,7 +6435,7 @@ pmap_copy_page4_4c(src, dst)
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setpte4(sva, spte);
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setpte4(dva, dpte);
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qcopy(sva, dva, NBPG); /* loads cache, so we must ... */
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cache_flush_page((int)sva);
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cache_flush_page((vaddr_t)sva);
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setpte4(sva, 0);
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setpte4(dva, 0);
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}
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@ -6423,6 +6448,7 @@ pmap_copy_page4_4c(src, dst)
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* We avoid stomping on the cache.
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* XXX might be faster to use destination's context and allow cache to fill?
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*/
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int xxxdebug = 0;
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void
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pmap_zero_page4m(pa)
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paddr_t pa;
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@ -6439,18 +6465,15 @@ pmap_zero_page4m(pa)
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if (CACHEINFO.c_vactype != VAC_NONE)
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pv_flushcache(pvhead(pa));
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}
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pte = (SRMMU_TEPTE | PPROT_S | PPROT_WRITE |
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(atop(pa) << SRMMU_PPNSHIFT));
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pte = SRMMU_TEPTE | PPROT_N_RWX | (atop(pa) << SRMMU_PPNSHIFT);
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if (cpuinfo.flags & CPUFLG_CACHE_MANDATORY)
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pte |= SRMMU_PG_C;
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else
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pte &= ~SRMMU_PG_C;
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va = vpage[0];
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setpgt4m(vpage_pte[0], pte);
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qzero(va, NBPG);
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/* Remove temporary mapping */
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tlb_flush_page((int)va);
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tlb_flush_page(va);
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setpgt4m(vpage_pte[0], SRMMU_TEINVALID);
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}
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@ -6474,7 +6497,8 @@ pmap_copy_page4m(src, dst)
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if (CACHEINFO.c_vactype == VAC_WRITEBACK)
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pv_flushcache(pvhead(src));
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}
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spte = SRMMU_TEPTE | SRMMU_PG_C | PPROT_S |
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spte = SRMMU_TEPTE | SRMMU_PG_C | PPROT_N_RX |
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(atop(src) << SRMMU_PPNSHIFT);
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if (managed(dst)) {
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@ -6482,22 +6506,20 @@ pmap_copy_page4m(src, dst)
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if (CACHEINFO.c_vactype != VAC_NONE)
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pv_flushcache(pvhead(dst));
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}
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dpte = (SRMMU_TEPTE | PPROT_S | PPROT_WRITE |
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(atop(dst) << SRMMU_PPNSHIFT));
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dpte = SRMMU_TEPTE | PPROT_N_RWX | (atop(dst) << SRMMU_PPNSHIFT);
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if (cpuinfo.flags & CPUFLG_CACHE_MANDATORY)
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dpte |= SRMMU_PG_C;
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else
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dpte &= ~SRMMU_PG_C;
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sva = vpage[0];
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dva = vpage[1];
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setpgt4m(vpage_pte[0], spte);
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setpgt4m(vpage_pte[1], dpte);
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qcopy(sva, dva, NBPG); /* loads cache, so we must ... */
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cache_flush_page((int)sva);
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tlb_flush_page((int)sva);
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cache_flush_page((vaddr_t)sva);
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tlb_flush_page(sva);
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setpgt4m(vpage_pte[0], SRMMU_TEINVALID);
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tlb_flush_page((int)dva);
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tlb_flush_page(dva);
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setpgt4m(vpage_pte[1], SRMMU_TEINVALID);
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}
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#endif /* SUN4M */
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