- Add mips32 and mips64 locore function prototypes.
- Add mips3_lw_a64() and mips3_sw_a64() for access data at any
64bit address (from Broadcom Corp).
- Add Broadcom and Sandcraft CPU company ids.
COP0_SYNC
In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
IPL_ICU_MASK
mask interrupt directly ICU instead of SR.IM.
I've added this feature to support software interrupt for R5900.
and this option may be useful for platform which has cascaded ICU.
there are just far too many combinations to handle with magic
#ifdefs in any sane way. Also, add a HitFlushDCache op to the
"locoresw", and fill it in as appropriate (it's NULL on MIPS-I,
so watch out).
These changes ensure that my R4600 Indy (with 2-way cache) gets
the correct cache ops when the kernel is built with only MIPS3
support, resulting in a kernel that is significantly more stable.
for mips_read_statusreg (which was apparently never implemented).
Provide prototypes and implementations for mips_cp0_cause_write,
mips_cp0_status_read, and mips_cp0_status_write. (Writing can, of
course, be quite dangerous.)
for mips3 (and later) 'ld' and 'sd' instructions. These currently
only are properly implemented for the _MIPS_BSD_API_LP32 and
_MIPS_BSD_API_LP32_64CLEAN 'API's. They're pretty messy, but when you
need them, you really need them.
and data cache sizes). R4000 uses 2^(12+IC) and 2^(12+DC). IDT32364
uses 2^(9+IC) and 2^(9+DC).
abstract around the problem by making the base a parameter to the
MIPS3_CONFIG_CACHE_SIZE macro. we pass the base down from mips_vector_init
to mips3_vector_init and to mips3_ConfigCache (where it is used).
XXX: someone with an MIPS3_4100 should switch to this and get rid
of the ugly ifdefs in cpuregs.h
implementation of locore routines between MIPS1 and MIPS3. It's
independent from mips_locore_jumpvec_t which is for cache/TLB
manipulating routines peculiar to processor designs. mips_locore_jumpvec_t
will be replaced with "processor closures" encapsulating implementation
parameters (cpuinfo) and pointers to conventaion routines (cpuops),
eventually.
ALPHA; mips1_TBIA, mips1_TBIAP, mips1_TBIS.
- Make sure TBIA and TBIAP ops to have an argument for the size of TLB
which varies across even for MIPS1 implementations.
- Nuke the unused cpu_isa field from processor personality list.
- XXX XXX XXX
it's less-than-optimal and likely a mistake to have TLBUpdate().
It's costy to try to invalidate a single TLB entry whenver a certain
PTE is going to be modified by traversing the entire TLB looking
for the modified PTE because the PTE in question is not in TLB in
most cases. ASID bump could do the invalidation smartly. Solution
is planned for now.
Support VR4100.
Support 16KB page.
Support CPU without FPU.
Fix virtual alias problem(physio() case).
[new options]
options MIPS3_4100 /* VR4100 core */
options MIPS_16K_PAGE /* enable kernel support for 16k pages */
options SOFTFLOAT /* No FPU; avoid touching FPU registers */
* Add the correct version of locore_mips1.S [ See previous revision for
description of changes ]
* Use defopt'ed MIPS3_L2CACHE_ABSENT in mips_machdep.c and pmap.c
to avoid generating extraneous code.
* GC pmap_set_referenced in pmap.c
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.
* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.
* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.
* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
thorpej