Commit Graph

476 Commits

Author SHA1 Message Date
Christophe Lyon
51e3930fc7 target-arm: fix unsigned 64 bit right shifts.
Fix range of shift amounts which always give 0 as result.

Signed-off-by: Christophe Lyon <christophe.lyon@st.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20 17:43:01 +01:00
Christophe Lyon
b6c63b9891 target-arm: Fix unsigned VRSHL.s8 and .s16 right shifts by type width
Fix handling of unsigned VRSHL.s8 and .s16 right shifts by the type
width.

Signed-off-by: Christophe Lyon <christophe.lyon@st.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20 17:43:01 +01:00
Peter Maydell
0670a7b65b target-arm: Fix signed VRSHL by large shift counts
Correctly handle VRSHL of signed values by a shift count of the
width of the data type or larger, which must be special-cased in the
rshl_s* helper functions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20 17:43:01 +01:00
Christophe Lyon
4bd4ee072c target-arm: Fix rounding constant addition for Neon shifts
Handle cases where adding the rounding constant could overflow in Neon
shift instructions: VRSHR, VRSRA, VQRSHRN, VQRSHRUN, VRSHRN.

Signed-off-by: Christophe Lyon <christophe.lyon@st.com>
[peter.maydell@linaro.org: fix handling of large shifts in rshl_s32,
calculate signed saturated value as other functions do.]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20 17:43:01 +01:00
Peter Maydell
d68a6f3a6d target-arm: Move Neon VZIP to helper functions
Move the implementation of the Neon VUZP unzip instruction from inline
code to helper functions. (At 50+ TCG ops it was well over the
recommended limit for coding inline.) The helper implementations also
give the correct answers where the inline implementation did not.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20 17:31:53 +01:00
Peter Maydell
02acedf93d target-arm: Move Neon VUZP to helper functions
Move the implementation of the Neon VUZP unzip instruction from inline
code to helper functions. (At 50+ TCG ops it was well over the
recommended limit for coding inline.) The helper implementations also
fix the handling of the quadword version of the instruction.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20 17:31:52 +01:00
Juha Riihimäki
f06053e3c3 target-arm: Correct conversion of Thumb Neon dp encodings into ARM
We handle Thumb Neon data processing instructions by converting them
into the equivalent ARM encoding, as the two are very close. However
the ARM encoding should have bit 28 set, not clear. This wasn't causing
any problems because we don't actually look at that bit during decode;
however it is better to do the conversion correctly to avoid problems
later if we add checks to UNDEF on SBZ/SBO bits.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20 17:30:09 +01:00
Peter Maydell
4dc064e66e target-arm: Fix Neon VQDMLSL instruction
For VQDMLSL, negation has to occur after saturation, not before.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20 17:28:39 +01:00
Peter Maydell
ebcd88ceb5 target-arm: Refactor handling of VQDMULL
Refactor the handling of VQDMULL so that it is dealt with in
its own if() case rather than together with the accumulating
instructions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20 17:28:37 +01:00
Peter Maydell
e5ca24cba9 target-arm: Implement VMULL.P8
Implement VMULL.P8 (the 32x32->64 version of the polynomial multiply
instruction).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20 17:26:15 +01:00
Dmitry Eremin-Solenikov
3213883efa arm: drop unused irq-related part of CPUARMState
These two fields were added as a part of ARMv7 support patch (back in
2007), were never used by any code, so can be dropped.

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-02-11 01:10:13 +01:00
Peter Maydell
f2f27b9f9b target-arm: Remove stray #include from middle of neon_helper.c
Remove a stray #include <stdio.h> from the middle of neon_helper.c:
it was harmless but pointless since we include stdio.h at the top
of the file anyway.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-10 21:21:30 +01:00
Peter Maydell
2d981da77d target-arm: Use standard FPSCR for Neon half-precision operations
The Neon half-precision conversion operations (VCVT.F16.F32 and
VCVT.F32.F16) use ARM standard floating-point arithmetic, unlike
the VFP versions (VCVTB and VCVTT).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-10 18:28:30 +01:00
Peter Maydell
fb91678d2c target-arm: Silence NaNs resulting from half-precision conversions
Silence the NaNs that may result from half-precision conversion,
as we do for the other conversions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-10 18:28:30 +01:00
Peter Maydell
bb4d4bb376 softfloat: Add float16 type and float16 NaN handling functions
Add a float16 type to softfloat, rather than using bits16 directly.
Also add the missing functions float16_is_quiet_nan(),
float16_is_signaling_nan() and float16_maybe_silence_nan(),
which are needed for the float16 conversion routines.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-10 18:28:09 +01:00
Christophe Lyon
923e65097d target-arm: implement vsli.64, vsri.64
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-09 19:48:48 +01:00
Christophe Lyon
acdf01effa target-arm: fix VSHLL Neon instruction.
Fix bit mask used when widening the result of shift on narrow input.

Signed-off-by: Christophe Lyon <christophe.lyon@st.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-09 19:47:20 +01:00
Peter Maydell
cc2212c2f8 target-arm: Fix 32 bit signed saturating narrow
The returned value when doing saturating signed 64->32 bit
conversion of a negative number was incorrect due to a missing cast.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-09 19:37:48 +01:00
Juha Riihimäki
af1bbf30c4 target-arm: Fix VQMOVUN Neon instruction.
VQMOVUN does a signed-to-unsigned saturating conversion. This is
different from both the signed-to-signed and unsigned-to-unsigned
conversions already implemented, so we need a new set of helper
functions (neon_unarrow_sat*).

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-09 19:37:47 +01:00
Peter Maydell
a2fdc8907b target-arm: Fix decoding of Thumb preload and hint space
Refine the decoding of the Thumb preload and hint space, so we
UNDEF on the patterns that are supposed to UNDEF rather than NOP.
We also move the tests for this space earlier, so we don't emit
harmless but unnecessary address generation code for preload
hints (which by their nature are likely to be in hot code paths).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-04 21:30:15 +01:00
Peter Maydell
3d185e5dd4 target-arm: Fix decoding of preload and memory hint space
Correct the decoding of the ARM preload and memory hint space,
by adding decoding of PLI, PLDW and the v7MP unallocated hint
space. This commit also corrects a slightly overexuberant
decoding of PLD(register) which was not checking that bit 4
was one.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-04 21:30:15 +01:00
Peter Maydell
607b4b0876 target-arm: Clean up handling of MPIDR
The ARM cp15 register 0,c0,c0,5 is standardised in the v7 architecture
as the MPIDR. Clean up its implementation to remove A9 specific handling.

This commit includes fixing an error in the value returned for the
MPIDR on A9, where we were erroneously claiming a cluster ID of 9.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-04 21:30:15 +01:00
Peter Maydell
e1bbf44636 target-arm: Add CPU feature flag for v7MP
Add a CPU feature flag for v7MP (the multiprocessing extensions); some
instructions exist only for v7MP and not for the base v7 architecture.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-04 21:30:14 +01:00
Christophe Lyon
72902672dc Set the right overflow bit for neon 32 and 64 bit saturating add/sub.
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-04 20:57:41 +01:00
Christophe Lyon
5371cb8140 target-arm: Fix Neon vsra instructions.
This patch fixes the errors reported by my tests in VSRA.

Signed-off-by: Christophe Lyon <christophe.lyon@st.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-04 20:48:41 +01:00
Juha Riihimäki
46eece9d89 target-arm: Fix Neon VQ(R)DMULH.S16 instructions
Correct an error in the implementation of the 16 bit
forms of VQ(R)DMULH, bringing them into line with the
32 bit implementation.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-29 15:16:29 +01:00
Peter Maydell
0fad6efce5 target-arm: Fix loading of scalar value for Neon multiply-by-scalar
Fix the register and part of register we get the scalar from in
the various "multiply vector by scalar" ops (VMUL by scalar
and friends).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-26 14:30:24 +01:00
Christophe Lyon
c6067f04c5 target-arm: Fix garbage collection of temporaries in Neon emulation.
Fix garbage collection of temporaries in Neon emulation.

Signed-off-by: Christophe Lyon <christophe.lyon@st.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-26 14:30:24 +01:00
Christophe Lyon
40d3c43360 Support saturation with shift=0.
This patch fixes corner-case saturations, when the target range is
zero. It merely removes the guard against (sh == 0), and makes:
__ssat(0x87654321, 1) return 0xffffffff and set the saturation flag
__usat(0x87654321, 0) return 0 and set the saturation flag

Signed-off-by: Christophe Lyon <christophe.lyon@st.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-26 14:30:24 +01:00
Peter Maydell
5642463aee target-arm: Log instruction start in TCG code
Add support for logging the start of instructions in TCG
code debug dumps for ARM targets.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-01-18 15:23:44 +01:00
Peter Maydell
e12ce78d4a target-arm: Restore IT bits when resuming after an exception
We were not correctly restoring the IT bits when resuming execution
after taking an unexpected exception in the middle of an IT block.
Fix this by tracking them along with PC changes and restoring in
gen_pc_load().

This fixes bug https://bugs.launchpad.net/qemu/+bug/581335

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:19 +01:00
Peter Maydell
bc4a0de0a2 target-arm: Refactor translation of exception generating instructions
Create a new function which does the common sequence of gen_set_condexec,
gen_set_pc_im, gen_exception, set is_jmp to DISAS_JUMP.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:19 +01:00
Peter Maydell
5de3a9d3b7 target-arm: Remove redundant setting of IT bits before Thumb SWI
Remove a redundant call to gen_set_condexec() in the translation of Thumb
mode SWI. (SWI and WFI generate "exceptions" which happen after the
execution of the instruction, ie when PC and IT bits have updated.
So the condexec bits at this point are not correct. However, the code
that handles finishing the translation of the TB will write the correct
value of the condexec bits later, so the only effect was that a conditional
Thumb SWI would generate slightly worse code than necessary.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:19 +01:00
Peter Maydell
61f74d6a29 target-arm: Translate with user-state from TB flags, not CPUState
When translating, get the user/priv state from the TB flags, not
the CPUState.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:19 +01:00
Peter Maydell
05ed9a9919 target-arm: Set privileged bit in TB flags correctly for M profile
M profile ARM cores don't have a CPSR mode field. Set the bit in the
TB flags that indicates non-user mode correctly for these cores.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:19 +01:00
Peter Maydell
98eac7cab4 target-arm: Translate with condexec bits from TB flags, not CPUState
When translating, the condexec bits for the TB are in the TB flags;
the CPUState condexec bits may be different.

This patch fixes https://bugs.launchpad.net/bugs/604872 where we might
segfault if we took an exception in the middle of a TB with an IT
block, because when we came to retranslate in cpu_restore_state()
the CPUState condexec bits would have advanced compared to the start
of the TB and we would generate different (wrong) code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:19 +01:00
Peter Maydell
7204ab889f target-arm: Translate with Thumb state from TB flags, not CPUState
The Thumb/ARM state for the TB being translated should come from
the TB flags, not the CPUState.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:19 +01:00
Peter Maydell
69d1fc221a target-arm: Translate with VFP len/stride from TB flags, not CPUState
When translating, the VFP vector length and stride for this TB are encoded
in the TB flags; the CPUState copies may be different and must not be used.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:19 +01:00
Peter Maydell
5df8bac1d3 target-arm: Translate with VFP-enabled from TB flags, not CPUState
When translating code, whether the VFP unit is enabled for this TB
is stored in a bit in the TB flags. Use this rather than incorrectly
reading the FPEXC from the CPUState passed to translation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:19 +01:00
Peter Maydell
a170576856 target-arm: Add symbolic constants for bitfields in TB flags
Add symbolic constants for the bitfields we use in the TB flags.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:18 +01:00
Peter Maydell
39ea3d4eaf target-arm: Don't generate code specific to current CPU mode for SRS
When translating the SRS instruction, handle the "store registers
to stack of current mode" case in the helper function rather than
inline. This means the generated code does not make assumptions
about the current CPU mode which might not be valid when the TB
is executed later.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:18 +01:00
Peter Maydell
718269667a target-arm: Use the standard FPSCR value for VRSQRTS
VSQRTS always uses the standard FPSCR value as it is a Neon instruction.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:18 +01:00
Peter Maydell
3a492f3a60 target-arm: Add support for 'Standard FPSCR Value' as used by Neon
Add support to the ARM helper routines for a second fp_status value
which should be used for operations which the ARM ARM indicates use
"ARM standard floating-point arithmetic" rather than being controlled
by the rounding/flush/NaN settings in the FPSCR.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:18 +01:00
Peter Maydell
9ea62f571c target-arm: Fix implementation of VRSQRTS
The implementation of the ARM VRSQRTS instruction (which calculates
(3 - op1 * op2) / 2) was missing the division operation. It also
did not handle the special cases of (0,inf) and (inf,0).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:18 +01:00
Peter Maydell
0322b26e2d ARM: Fix decoding of VQSHL/VQSHLU immediate forms
Fix errors in the decoding of ARM VQSHL/VQSHLU immediate forms,
including using the new VQSHLU helper functions where appropriate.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-12 00:06:06 +01:00
Juha Riihimäki
4ca4502c93 ARM: add neon helpers for VQSHLU
Add neon helper functions to implement VQSHLU, which is a
signed-to-unsigned version of VQSHL available only as an
immediate form.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-12 00:06:06 +01:00
Peter Maydell
cecd8504b8 target-arm: wire up the softfloat flush_input_to_zero flag
Wire up the new softfloat support for flushing input denormals
to zero on ARM. The FPSCR FZ bit enables flush-to-zero for
both inputs and outputs, but the reporting of when inputs are
flushed to zero is via a separate IDC bit rather than the UFC
(underflow) bit used when output denormals are flushed to zero.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-06 22:16:59 +01:00
Peter Maydell
b12c390b91 target-arm: Set softfloat cumulative exc flags from correct FPSCR bits
When handling a write to the ARM FPSCR, set the softfloat cumulative
exception flags from the cumulative flags in the FPSCR, not the
exception-enable bits. Also don't apply a mask: vfp_exceptbits_to_host
will only look at the correct bits anyway.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-06 22:16:59 +01:00
Aurelien Jarno
838fa72d0b target-arm: fix SMMLA/SMMLS instructions
SMMLA and SMMLS are broken on both in normal and thumb mode, that is
both (different) implementations are wrong. They try to avoid a 64-bit
add for the rounding, which is not trivial if you want to support both
SMMLA and SMMLS with the same code.

The code below uses the same implementation for both modes, using the
code from the ARM manual. It also fixes the thumb decoding that was a
mix between normal and thumb mode.

This fixes the issues reported in
https://bugs.launchpad.net/qemu/+bug/629298

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-06 22:16:46 +01:00
Aurelien Jarno
8aac08b10b target-arm: fix UMAAL instruction
UMAAL should use unsigned multiply instead of signed.

This patch fixes this issue by handling UMAAL separately from
UMULL/UMLAL/SMULL/SMLAL as these instructions are different
enough. It also explicitly list instructions in case and catch
nonexistent instruction as illegal. Also fixes a few style issues.

This fixes the issues reported in
https://bugs.launchpad.net/qemu/+bug/696015

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-31 22:22:26 +01:00
Juha Riihimäki
16440c5fa0 target-arm: correct cp15 c1_sys reset value for arm1136 and cortex-a9
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27 21:21:17 +01:00
Mattias Holm
9c486ad6e4 target-arm: correct cp15 c1_sys reset value for cortex-a8
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27 21:21:17 +01:00
Juha Riihimäki
c003432809 target-arm: fix vmsav6 access control
Override access control checks (including execute) for mmu translation
table descriptors assigned to manager domains.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27 21:21:16 +01:00
Peter Maydell
a5d88f3e03 target-arm: Correct result in saturating cases for VQSHL of s8/16/32
Where VQSHL of a signed 8/16/32 bit value saturated, the result
value was not being calculated correctly (it should be either
the minimum or maximum value for the size of the signed type).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27 21:07:24 +01:00
Juha Riihimäki
620d791e34 target-arm: remove pointless else clause in VQSHL of u64
Remove a pointless else clause in the neon_qshl_u64 helper.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27 21:07:16 +01:00
Peter Maydell
eb7a3d7964 target-arm: Fix VQSHL of signed 64 bit values by shift counts >= 64
VQSHL of a signed 64 bit non-zero value by a shift count >= 64 should
saturate; return the correct value in this case.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27 21:07:10 +01:00
Juha Riihimäki
4c9b70aeca target-arm: Fix VQSHL of signed 64 bit values
Add a missing '-' which meant that we were misinterpreting the shift
argument for VQSHL of 64 bit signed values and treating almost every
shift value as if it were an extremely large right shift.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27 21:07:03 +01:00
Juha Riihimäki
def126ce37 target-arm: Fix arguments passed to VQSHL helpers
Correct the arguments passed when generating neon qshl_{u,s}64()
helpers so that we use the correct registers.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27 21:06:55 +01:00
Aurelien Jarno
1a855029af target-arm: fix bug in translation of REVSH
The translation of REVSH shifted the low byte 8 steps left before performing
an 8-bit sign extend, causing this part of the expression to alwas be 0.

Reported-by: Johan Bengtsson <teofrastius@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27 19:56:43 +01:00
Peter Maydell
72f24d155c ARM: Implement VCVT to 16 bit integer using new softfloat routines
Use the softfloat conversion routines for conversion to 16 bit
integers, because just casting to a 16 bit type truncates the
value rather than saturating it at 16-bit MAXINT/MININT.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07 15:37:34 +00:00
Peter Maydell
26a5e69aaf ARM: Ignore top 16 bits when doing VCVT from 16 bit fixed point
VCVT of 16 bit fixed point to float should ignore the top 16 bits
of the source register. Cast to int16_t and friends rather than
int16 -- the former is guaranteed exactly 16 bits wide where the
latter is merely at least 16 bits wide (and so is usually 32 bits).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07 15:37:34 +00:00
Peter Maydell
2d6277373d ARM: Return correct result for single<->double conversion of NaN
The ARM ARM defines that if the input to a single<->double conversion
is a NaN then the output is always forced to be a quiet NaN by setting
the most significant bit of the fraction part.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07 15:37:34 +00:00
Peter Maydell
09d9487fbb ARM: Return correct result for float-to-integer conversion of NaN
The ARM architecture mandates that converting a NaN value to
integer gives zero (if Invalid Operation FP exceptions are
not being trapped). This isn't the behaviour of the SoftFloat
library, so NaNs must be special-cased.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07 15:37:34 +00:00
Peter Maydell
d3587ef81d ARM: Fix sense of to_integer bit in Neon VCVT float/int conversion
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07 15:37:34 +00:00
Peter Maydell
f73534a56e ARM: Fix decoding of Neon forms of VCVT between float and fixed point
Fix errors in the decoding of the Neon forms of fixed-point VCVT:
 * fixed-point VCVT is op 14 and 15, not 15 and 16
 * the fbits immediate field was being misinterpreted
 * the sense of the to_fixed bit was inverted

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07 15:37:34 +00:00
Peter Maydell
04595bf66f ARM: Fix decoding of VFP forms of VCVT between float and int/fixed
Correct the decoding of source and destination registers
for the VFP forms of the VCVT instructions which convert
between floating point and integer or fixed-point.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07 15:37:34 +00:00
Peter Maydell
2c9adbda72 ARM: fix ldrexd/strexd
Correct ldrexd and strexd code to always read and write the
high word of the 64-bit value from addr+4.
Also make ldrexd and strexd agree that for a 64 bit value the
address in env->exclusive_addr is that of the low word.

This fixes the issues reported in
https://bugs.launchpad.net/qemu/+bug/670883

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07 15:37:34 +00:00
Adam Lackorzynski
49e14940ad target-arm: Handle 'smc' as an undefined instruction
Refine check on bkpt so that smc and undefined instruction encodings are
handled as an undefined instruction and trap.

Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07 12:01:44 +00:00
Johan Bengtsson
4809c612bc target-arm: Fix mixup in decoding of saturating add and sub
The thumb2 decoder contained a mixup between the bit controlling
doubling and the bit controlling if the operation was an add or a sub.

Signed-off-by: Johan Bengtsson <teofrastius@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07 12:01:44 +00:00
Johan Bengtsson
2af9ab7737 target-arm: Add support for PKHxx in thumb2
The PKHxx instructions were not recognized by the thumb2 decoder. The
solution provided in this changeset is identical to the arm-mode
implementation.

Signed-off-by: Johan Bengtsson <teofrastius@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07 12:01:44 +00:00
Peter Maydell
0165329578 ARM: Expose vfp_get_fpscr() and vfp_set_fpscr() to C code
Expose the vfp_get_fpscr() and vfp_set_fpscr() functions to C
code as well as generated code, so we can use them to read and
write the FPSCR when saving and restoring VFP registers across
signal handlers in linux-user mode.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
2010-12-03 15:09:39 +02:00
Peter Maydell
3a807decfa ARM: enable XScale/iWMMXT in linux-user mode
In linux-user mode, the XScale/iWMMXT coprocessors must be enabled
at reset so that we can run code that uses these instructions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2010-12-03 15:09:39 +02:00
Peter Maydell
b0e102dd22 [PATCH] target-arm: remove unused functions cpu_lock(), cpu_unlock()
Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
2010-12-03 15:09:38 +02:00
Stefan Weil
9a78eead0c target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.

Format errors were fixed in
* target-i386/helper.c
* target-mips/translate.c
* target-ppc/translate.c

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-30 08:01:59 +00:00
Paolo Bonzini
a88790a14f remove exec-all.h inclusion from cpu.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03 09:48:24 +03:00
Paolo Bonzini
10eb0cc03c move cpu_pc_from_tb to target-*/exec.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03 09:48:12 +03:00
Chih-Min Chao
4c4fd3f852 target-arm : fix parallel saturated subtraction implementation
Signed-off-by: Chih-Min Chao <cmchao@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-01 23:45:29 +02:00
Chih-Min Chao
ed89a2f1b1 target-arm : fix thumb2 parallel add/sub opcode decoding
Signed-off-by: Chih-Min Chao <cmchao@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-01 23:45:29 +02:00
Chih-Min Chao
bb42e28bdb target-arm: fix addsub/subadd implementation
Signed-off-by: Chih-Min Chao <cmchao@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-01 23:45:29 +02:00
Paul Brook
41ba834146 NEON vldN optimization
When combining multiple values as part of a NEON array load, do explcit
shift/or rather than using gen_bfi.  This voids redundant mask
operations.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-06-11 20:37:51 +01:00
Lars Munch
e03c22a98c arm: fix arm kernel boot for non zero start addr
Booting an arm kernel has been broken a while when booting from non zero start
address. This is due to the order of events: board init loads the kernel and
sets register 15 to the start address and then qemu_system_reset reset the cpu
making register 15 zero again.

This patch fixes the usage of the register 15 start address trick in
combination with arm_load_kernel.

Signed-off-by: Lars Munch <lars@segv.dk>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-31 19:40:41 +02:00
Lars Munch
9ba8c3f41d arm: prevent coprocessor IO reset
This prevent coprocessor IO structure from being reset on cpu reset. This was
a problem for PXA which uses coprocessor 6 and 14.

Signed-off-by: Lars Munch <lars@segv.dk>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-28 21:25:16 +02:00
Blue Swirl
22ed1d3478 arm: remove dead assignments, spotted by clang analyzer
Value stored is never read.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-25 19:31:06 +00:00
Juha Riihimäki
8e31209eea target-arm: fix neon vmon/vmvn with modified immediate
Signed-Off-By: Riku Voipio <riku.voipio@nokia.com>
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 21:12:24 +02:00
Lars Munch
d996882703 target-arm: resource leak fixes for iwmmxt disassemble
This patch fixes few resource leaks in the iwmmxt disassemble.

Signed-off-by: Lars Munch <lars@segv.dk>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 11:11:21 +02:00
Paul Brook
4f78c9ad5a Fix arm-linux-user
Only include hw/loader.h from target-arm/helper.c when building for
system emulation.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-04-05 19:56:34 +01:00
Paul Brook
983fe82611 ARMv7-M reset fixes
Move ARMv7-M PC/SP initialization to the CPU reset routine.  Add a board
reset routine to call this.  Also load values directly from ROM as
images have not been copied yet.

Avoid clearing the NVIC pointer on cpu reset.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-04-05 19:43:12 +01:00
Rabin Vincent
3ad493fc5e target-arm: disable PAGE_EXEC for XN pages
Don't set PAGE_EXEC for XN pages, to avoid a bypass of XN protection
checking if the page is already in the TLB.

Signed-off-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-27 14:14:34 +01:00
Johan Bengtsson
bedd2912c8 target-arm: Fix handling of AL condition in IT instruction
Do not try to insert a conditional jump over next instruction when the
condition code is AL as this will trigger an internal error.

Signed-off-by: Johan Bengtsson <teofrastius@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-23 22:10:45 +01:00
Paul Brook
d4c430a80f Large page TLB flush
QEMU uses a fixed page size for the CPU TLB.  If the guest uses large
pages then we effectively split these into multiple smaller pages, and
populate the corresponding TLB entries on demand.

When the guest invalidates the TLB by virtual address we must invalidate
all entries covered by the large page.  However the address used to
invalidate the entry may not be present in the QEMU TLB, so we do not
know which regions to clear.

Implementing a full vaiable size TLB is hard and slow, so just keep a
simple address/mask pair to record which addresses may have been mapped by
large pages.  If the guest invalidates this region then flush the
whole TLB.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-17 02:44:41 +00:00
Adam Lackorzynski
ea825eeefd target-arm: make RFE usable with any register
The rfe instruction can be used with any register, not just sp. Adjust the
condition check accordingly.

Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 12:01:29 +01:00
Paul Brook
4fcc562bff Remove cpu_get_phys_page_debug from userspace emulation
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12 18:34:25 +00:00
Richard Henderson
5270589032 Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.
Removes a set of ifdefs from exec.c.

Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other
than Alpha.  This will be used for page_find_alloc, which is
supposed to be using virtual addresses in the first place.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2010-03-12 16:28:24 +00:00
Adam Lackorzynski
a990f58fed target-arm: Fix missing 'return' in SRS handling.
There's a return missing in the srs handling which leads to srs always being
treated an an invalid op.

Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-06 23:22:22 +01:00
Juha Riihimäki
30d11a2a01 target-arm: neon vshll instruction fix
implementation only widened the 32bit source vector elements into a
64bit destination vector but forgot to perform the actual shifting
operation.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28 19:30:56 +01:00
Riku Voipio
79b0e534c0 target-arm: neon - fix VRADDHN/VRSUBHN vs VADDHN/VSUBHN
The rounding/truncating options were inverted. truncating
was done when rounding was meant and vice verse.

Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28 19:30:04 +01:00
Paul Brook
c5883be235 ARM CP15 tls fix
Fix temporary handling in cp15 tls register load/store.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-02-23 14:45:16 +00:00
Rabin Vincent
30a8cac139 target-arm: support thumb exception handlers
When handling an exception, switch to the correct mode based on the
Thumb Exception (TE) bit in the SCTLR.

Signed-off-by: Rabin Vincent <rabin@rab.in>
2010-02-19 15:20:21 +00:00
Rabin Vincent
b8b45b68f8 target-arm: implement Thumb-2 exception return
Support the "subs pc, lr" Thumb-2 exception return instruction.

Signed-off-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-02-19 13:38:43 +00:00
Rabin Vincent
fa26df032e target-arm: fix thumb CPS
The Thumb CPS currently does not work correctly: CPSID touches more bits
than the instruction wants to, and CPSIE does nothing.  Fix it by
passing the correct mask (the "affect" bits) and value.

Signed-off-by: Rabin Vincent <rabin@rab.in>
2010-02-19 13:38:32 +00:00
Riku Voipio
3f26c1227e target-arm: refactor cp15.c13 register access
Access the cp15.c13 TLS registers directly with TCG ops instead of with
a slow helper. If the the cp15 read/write was not TLS register access,
fall back to the cp15 helper.

This makes accessing __thread variables in linux-user when apps are compiled
with -mtp=cp15 possible. legal cp15 register to acces from linux-user are
already checked in cp15_user_ok.

While at it, make the cp15.c13 Thread ID registers available only on
ARMv6K and newer.

Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
2010-02-06 17:19:43 +01:00
Paolo Bonzini
49a945a3c0 kill regs_to_env and env_to_regs
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-19 16:31:02 -06:00
Aurelien Jarno
502e64fe23 target-arm: fix strexd
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-24 00:18:23 +01:00
Paul Brook
426f5abcaa ARM atomic ops rewrite
Implement ARMv6 atomic ops (ldrex/strex) using the same trick as PPC.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-11-22 21:35:13 +00:00
Paul Brook
100555620f ARM Cortex-A9 cpu support
Basic Cortex-A9 support.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-11-19 16:45:20 +00:00
Paul Brook
600114988c ARM FP16 support
Implement the ARM VFP half precision floating point extensions.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-11-19 16:45:20 +00:00
Aurelien Jarno
f669df275c target-arm: use native tcg-ops for ror/bic/vorn
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27 09:46:27 +01:00
Juha Riihimäki
50f67e95e2 target-arm: fix neon shift helper functions
Current code is broken at least on recent compilers, comparison
between signed and unsigned types yield incorrect code and render
the neon shift helper functions defunct. This is the third revision
of this patch, casting all comparisons with the sizeof operator to
signed ssize_t type to force comparisons to be between signed integral
types.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27 09:46:26 +01:00
Juha Riihimäki
ca9a32e4f3 target-arm: fix neon vsri, vshl and vsli ops
Shift by immediate value is incorrectly overwritten by a temporary
variable in the processing of NEON vsri, vshl and vsli instructions.
This patch has been revised to also include a fix for the special
case where the code would previously try to shift an integer value
over 31 bits left/right.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27 09:46:26 +01:00
Juha Riihimäki
71b3c3dea2 target-arm: allow modifying vfp fpexc en bit only
All other bits except for the EN in the VFP FPEXC register are defined
as subarchitecture specific and real functionality for any of the
other bits has not been implemented in QEMU. However, current code
allows modifying all bits in the VFP FPEXC register leading to
problems when guest code is writing 1's to the subarchitecture
specific bits and checking whether the bits stay up to verify the
existence of functionality which in fact does not exist in QEMU.
This patch has been revised to include the same behavior change in
the gdb register write function.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27 09:46:26 +01:00
Juha Riihimäki
8449623376 target-arm: add support for neon vld1.64/vst1.64 instructions
Add support for NEON vld1.64 and vst1.64 instructions. This patch is
revised to follow more closely the specification and raises
undefined exception if 64bit element size is used for vld2/vst2 or
vld4/vst4 instructions.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27 09:46:26 +01:00
Juha Riihimäki
2301db4916 target-arm: fix neon vshrn/vrshrn ops
In the existing code shift value is clobbered during the pass loop.
This patch changes the code so that it stores the intermediate
result in the target neon register directly and eliminates the need
to use a temporary to hold the intermediate value thus leaving the
shift value in the temporary variable intact. This is a new patch
in this version of the patch series.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27 09:46:26 +01:00
Juha Riihimäki
25aeb69b8d target-arm: fix incorrect temporary variable freeing
tmp4 and tmp5 temporary variables are allocated using tcg_const_i32
but incorrectly released using dead_tmp which will cause resource
leak tracking to report false leaks.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by:  Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-26 20:36:47 +01:00
Juha.Riihimaki@nokia.com
7b2919a0b4 target-arm: optimize thumb 32-bit multiply
Current implementation of thumb mul instruction is implemented as a
32x32->64 multiply which then uses only 32 least significant bits of
the result. Replace that with a simple 32x32->32 multiply.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23 17:22:13 +02:00
Juha Riihimäki
b75263d653 target-arm: cleanup internal resource leaks
Revised patch for getting rid of tcg temporary variable leaks in
target-arm/translate.c. This version also includes the leak patch for
gen_set_cpsr macro, now converted as a static inline function, which I
sent earlier as a separate patch on top of this patch.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23 17:11:43 +02:00
Aurelien Jarno
686eeb93d5 target-arm: fix sdiv helper
(INT32_MIN / -1) triggers an overflow, and the result depends on the
host architecture (INT32_MIN on arm, -1 on ppc, SIGFPE on x86). Use a
test to output the correct value.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
2009-10-23 00:05:17 +02:00
Aurelien Jarno
7bbcb0afe7 target-arm: use clz32() instead of a for loop
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
2009-10-23 00:05:17 +02:00
Aurelien Jarno
dcc65026c4 target-arm: fix bugs introduced by 1b2b1e547b
Use load_reg_var() instead of accessing cpu_R[rn] directly to generate
correct code when rn = 15.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-18 16:00:18 +02:00
Aurelien Jarno
98a463171b target-arm: fix bugs introduced by 3174f8e91f
Use load_reg_var() instead of accessing cpu_R[rn] directly to generate
correct code when rn = 15.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-18 15:53:28 +02:00
Aurelien Jarno
b567b38c2c target-arm: remove T0 and T1
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:53:08 +02:00
Filip Navara
747a651e8e target-arm: remove cpu_T for ARM once and for all
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:18 +02:00
Filip Navara
312eea9f99 target-arm: convert VFP not to use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
da6b5335d5 target-arm: convert disas_iwmmxt_insn not to use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
3a554c0f20 target-arm: convert disas_dsp_insn not use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
1b2b1e547b target-arm: convert disas_neon_ls_insn not to use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
dd8fbd787e target-arm: convert disas_neon_data_insn and helpers not to use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
3174f8e91f target-arm: convert rest of disas_arm_insn / disas_thumb2_insn not to use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
396e467cb1 target-arm: replace thumb usage of cpu_T registers by proper register allocations
The goal is eventually to get rid of all cpu_T register usage and to use
just short-lived tmp/tmp2 registers. This patch converts all the places where
cpu_T was used in the Thumb code and replaces it with explicit TCG register
allocation.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
15bb4eac12 target-arm: fix TANDC and TORC instructions
Uninitialized register was used instead of proper TCG variable.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
194576157a target-arm: convert NEON VZIP/VUZP/VTRN helper functions to pure TCG
The neon_trn_u8, neon_trn_u16, neon_unzip_u8, neon_zip_u8 and neon_zip_u16
helpers used fixed registers to return values. This patch replaces that with
TCG code, so T0/T1 is no longer directly used by the helper functions.

Bugs in the gen_neon_unzip register load code were also fixed.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
a6445c52aa target-arm: convert gen_lookup_tb not to use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:17 +02:00
Filip Navara
2fbac54be0 target-arm: get rid of gen_set_psr_T0 and replace it by gen_set_psr/gen_set_psr_im
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:16 +02:00
Filip Navara
c67b6b719b target-arm: fix SRS/RFE instructions
The encoding of 'IA' and 'DB' conditions was swapped.
SRS instruction must store banked SPSR instead of CPSR at the specific address.
Missing 'return' statement at the end of RFE handling.
Fixed write-back code to reference correct registers.

From: Hyeonsung Jang <hsjang@ok-labs.com>
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:16 +02:00
Filip Navara
217aff9c76 target-arm: remove unused gen_movl_T2_reg function
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:16 +02:00
Filip Navara
288eebe54f target-arm: remove useless line that sets register that is never used again
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:16 +02:00
Filip Navara
12edd4f269 target-arm: get rid of temporary variable cache
The temporary variable cache in no longer need since tcg_temp_free was introduced.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:16 +02:00
Filip Navara
155c3eacd2 target-arm: use tcg_global_mem_new_i32 to allocate registers
Currently each read/write of ARM register involves a LD/ST TCG operation. This
patch uses TCG memory-backed registers to represent the ARM register set. With
memory-backed registers the LD/ST operations are transparently generated by TCG
and host registers could be used to optimize the generated code.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17 23:52:16 +02:00
Anthony Liguori
c227f0995e Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem.  Something
like this _must_ be presented on the list first so people can provide input
and cope with it.

This reverts commit 99a0949b72.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01 16:12:16 -05:00
malc
99a0949b72 Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <av1474@comtv.ru>
2009-10-01 22:45:02 +04:00
Blue Swirl
72cf2d4f0e Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there are
some additions and it's not entirely compatible. Because of that, there have
been conflicts with system headers on BSD systems. Some hacks have been
introduced in the commits 15cc923584,
f40d753718,
96555a96d7 and
3990d09adf but the fixes were fragile.

Solution: Avoid the conflict entirely by renaming the functions and the
file. Revert the previous hacks.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-12 07:36:22 +00:00
Nathan Froyd
0b5c1ce846 cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal
handle_cpu_signal is very nearly copy-paste code for each target, with a
few minor variations.  This patch sets up appropriate defaults for a
generic handle_cpu_signal and provides overrides for particular targets
that did things differently.  Fixing things like the persistent (XXX:
use sigsetjmp) should now become somewhat easier.

Previous comments on this patch suggest that the "activate soft MMU for
this block" comments refer to defunct functionality.  I have removed
such blocks for the appropriate targets in this patch.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-24 08:21:42 -05:00
Paul Brook
ffe47d331d Save/restore ARMv6 MMU state
Correctly save/restore ARMV6 MMU state.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-07-31 13:19:39 +01:00
Juan Quintela
e2542fe2bc rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-27 14:09:21 -05:00
Blue Swirl
8167ee8839 Update to a hopefully more future proof FSF address
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-16 20:47:01 +00:00
Filip Navara
024589f182 Remove unused gen_bx_T0 function.
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-06-24 09:09:15 -05:00
Anthony Liguori
f80f9ec9a6 Convert machine registration to use module init functions
This cleans up quite a lot of #ifdefs, extern variables, and other ugliness.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-21 08:47:55 -05:00
Juha Riihimäki
21aeb3430c fix ARMv7 data processing instructions
ARMv7 defines a new behavior for ARM data processing instructions
compared to earlier architecture revisions; when the destination
register is R15, a Branch and Exchange operation is executed rather
than a simple Branch to the target address. This patch corrects the
behavior of the emulation for the aforementioned operations. To be
applied after applying the previous patch in this patch set.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-15 03:18:42 +01:00
Juha Riihimäki
e9bb4aa977 fix ARMv7 data processing instructions
Modernize parts of target-arm/translate.c in preparation for the
modifications in the subsequent patch in this patch set. This is done
in order to avoid writing new code to target-arm/translate.c that
would use deprecated methods and/or variables.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-15 02:48:18 +01:00
Paul Brook
4af396115a Syborg (Symbian Virtual Platform) board
A virtual reference platform for SymbianOS development/debugging.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-14 23:11:09 +01:00
Paul Brook
cb76e138d3 Fixe ARM NEON vrshl.
Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-09 23:12:06 +01:00