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softfloat: Add float16 type and float16 NaN handling functions

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Add a float16 type to softfloat, rather than using bits16 directly.
Also add the missing functions float16_is_quiet_nan(),
float16_is_signaling_nan() and float16_maybe_silence_nan(),
which are needed for the float16 conversion routines.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Peter Maydell 2011-02-10 11:28:56 +00:00 committed by Aurelien Jarno
parent d1a1eb7472
commit bb4d4bb376
4 changed files with 118 additions and 12 deletions
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63
fpu/softfloat-specialize.h
View File

@ -56,6 +56,69 @@ typedef struct {
bits64 high, low;
} commonNaNT;
/*----------------------------------------------------------------------------
| The pattern for a default generated half-precision NaN.
*----------------------------------------------------------------------------*/
#if defined(TARGET_ARM)
#define float16_default_nan make_float16(0x7E00)
#elif SNAN_BIT_IS_ONE
#define float16_default_nan make_float16(0x7DFF)
#else
#define float16_default_nan make_float16(0xFE00)
#endif
/*----------------------------------------------------------------------------
| Returns 1 if the half-precision floating-point value `a' is a quiet
| NaN; otherwise returns 0.
*----------------------------------------------------------------------------*/
int float16_is_quiet_nan(float16 a_)
{
uint16_t a = float16_val(a_);
#if SNAN_BIT_IS_ONE
return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
#else
return ((a & ~0x8000) >= 0x7c80);
#endif
}
/*----------------------------------------------------------------------------
| Returns 1 if the half-precision floating-point value `a' is a signaling
| NaN; otherwise returns 0.
*----------------------------------------------------------------------------*/
int float16_is_signaling_nan(float16 a_)
{
uint16_t a = float16_val(a_);
#if SNAN_BIT_IS_ONE
return ((a & ~0x8000) >= 0x7c80);
#else
return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
#endif
}
/*----------------------------------------------------------------------------
| Returns a quiet NaN if the half-precision floating point value `a' is a
| signaling NaN; otherwise returns `a'.
*----------------------------------------------------------------------------*/
float16 float16_maybe_silence_nan(float16 a_)
{
if (float16_is_signaling_nan(a_)) {
#if SNAN_BIT_IS_ONE
# if defined(TARGET_MIPS) || defined(TARGET_SH4)
return float16_default_nan;
# else
# error Rules for silencing a signaling NaN are target-specific
# endif
#else
uint16_t a = float16_val(a_);
a |= (1 << 9);
return make_float16(a);
#endif
}
return a_;
}
/*----------------------------------------------------------------------------
| The pattern for a default generated single-precision NaN.
*----------------------------------------------------------------------------*/

44
fpu/softfloat.c
View File

@ -66,6 +66,33 @@ void set_floatx80_rounding_precision(int val STATUS_PARAM)
}
#endif
/*----------------------------------------------------------------------------
| Returns the fraction bits of the half-precision floating-point value `a'.
*----------------------------------------------------------------------------*/
INLINE uint32_t extractFloat16Frac(float16 a)
{
return float16_val(a) & 0x3ff;
}
/*----------------------------------------------------------------------------
| Returns the exponent bits of the half-precision floating-point value `a'.
*----------------------------------------------------------------------------*/
INLINE int16 extractFloat16Exp(float16 a)
{
return (float16_val(a) >> 10) & 0x1f;
}
/*----------------------------------------------------------------------------
| Returns the sign bit of the single-precision floating-point value `a'.
*----------------------------------------------------------------------------*/
INLINE flag extractFloat16Sign(float16 a)
{
return float16_val(a)>>15;
}
/*----------------------------------------------------------------------------
| Takes a 64-bit fixed-point value `absZ' with binary point between bits 6
| and 7, and returns the properly rounded 32-bit integer corresponding to the
@ -2713,23 +2740,24 @@ float32 float64_to_float32( float64 a STATUS_PARAM )
| than the desired result exponent whenever `zSig' is a complete, normalized
| significand.
*----------------------------------------------------------------------------*/
static bits16 packFloat16(flag zSign, int16 zExp, bits16 zSig)
static float16 packFloat16(flag zSign, int16 zExp, bits16 zSig)
{
return (((bits32)zSign) << 15) + (((bits32)zExp) << 10) + zSig;
return make_float16(
(((bits32)zSign) << 15) + (((bits32)zExp) << 10) + zSig);
}
/* Half precision floats come in two formats: standard IEEE and "ARM" format.
The latter gains extra exponent range by omitting the NaN/Inf encodings. */
float32 float16_to_float32( bits16 a, flag ieee STATUS_PARAM )
float32 float16_to_float32(float16 a, flag ieee STATUS_PARAM)
{
flag aSign;
int16 aExp;
bits32 aSig;
aSign = a >> 15;
aExp = (a >> 10) & 0x1f;
aSig = a & 0x3ff;
aSign = extractFloat16Sign(a);
aExp = extractFloat16Exp(a);
aSig = extractFloat16Frac(a);
if (aExp == 0x1f && ieee) {
if (aSig) {
@ -2753,7 +2781,7 @@ float32 float16_to_float32( bits16 a, flag ieee STATUS_PARAM )
return packFloat32( aSign, aExp + 0x70, aSig << 13);
}
bits16 float32_to_float16( float32 a, flag ieee STATUS_PARAM)
float16 float32_to_float16(float32 a, flag ieee STATUS_PARAM)
{
flag aSign;
int16 aExp;

19
fpu/softfloat.h
View File

@ -119,6 +119,11 @@ enum {
x86/gcc 3.x seems to struggle a bit, so leave them disabled by default. */
//#define USE_SOFTFLOAT_STRUCT_TYPES
#ifdef USE_SOFTFLOAT_STRUCT_TYPES
typedef struct {
uint16_t v;
} float16;
#define float16_val(x) (((float16)(x)).v)
#define make_float16(x) __extension__ ({ float16 f16_val = {x}; f16_val; })
typedef struct {
uint32_t v;
} float32;
@ -131,10 +136,13 @@ typedef struct {
#define float64_val(x) (((float64)(x)).v)
#define make_float64(x) __extension__ ({ float64 f64_val = {x}; f64_val; })
#else
typedef uint16_t float16;
typedef uint32_t float32;
typedef uint64_t float64;
#define float16_val(x) (x)
#define float32_val(x) (x)
#define float64_val(x) (x)
#define make_float16(x) (x)
#define make_float32(x) (x)
#define make_float64(x) (x)
#endif
@ -253,8 +261,15 @@ float128 int64_to_float128( int64_t STATUS_PARAM );
/*----------------------------------------------------------------------------
| Software half-precision conversion routines.
*----------------------------------------------------------------------------*/
bits16 float32_to_float16( float32, flag STATUS_PARAM );
float32 float16_to_float32( bits16, flag STATUS_PARAM );
float16 float32_to_float16( float32, flag STATUS_PARAM );
float32 float16_to_float32( float16, flag STATUS_PARAM );
/*----------------------------------------------------------------------------
| Software half-precision operations.
*----------------------------------------------------------------------------*/
int float16_is_quiet_nan( float16 );
int float16_is_signaling_nan( float16 );
float16 float16_maybe_silence_nan( float16 );
/*----------------------------------------------------------------------------
| Software IEC/IEEE single-precision conversion routines.

4
target-arm/helper.c
View File

@ -2627,14 +2627,14 @@ float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
{
float_status *s = &env->vfp.fp_status;
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
return float16_to_float32(a, ieee, s);
return float16_to_float32(make_float16(a), ieee, s);
}
uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env)
{
float_status *s = &env->vfp.fp_status;
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
return float32_to_float16(a, ieee, s);
return float16_val(float32_to_float16(a, ieee, s));
}
float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)