Peter Maydell 05ed9a9919 target-arm: Set privileged bit in TB flags correctly for M profile ... M profile ARM cores don't have a CPSR mode field. Set the bit in the TB flags that indicates non-user mode correctly for these cores. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>		2011-01-14 20:39:19 +01:00
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cpu.h	target-arm: Set privileged bit in TB flags correctly for M profile	2011-01-14 20:39:19 +01:00
exec.h	move cpu_pc_from_tb to target-*/exec.h	2010-07-03 09:48:12 +03:00
helper.c	target-arm: Don't generate code specific to current CPU mode for SRS	2011-01-14 20:39:18 +01:00
helpers.h	ARM: add neon helpers for VQSHLU	2011-01-12 00:06:06 +01:00
iwmmxt_helper.c	Update to a hopefully more future proof FSF address	2009-07-16 20:47:01 +00:00
machine.c	Save/restore ARMv6 MMU state	2009-07-31 13:19:39 +01:00
neon_helper.c	ARM: add neon helpers for VQSHLU	2011-01-12 00:06:06 +01:00
op_addsub.h	target-arm: fix addsub/subadd implementation	2010-07-01 23:45:29 +02:00
op_helper.c	[PATCH] target-arm: remove unused functions cpu_lock(), cpu_unlock()	2010-12-03 15:09:38 +02:00
translate.c	target-arm: Translate with condexec bits from TB flags, not CPUState	2011-01-14 20:39:19 +01:00