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target-arm: wire up the softfloat flush_input_to_zero flag 

Wire up the new softfloat support for flushing input denormals
to zero on ARM. The FPSCR FZ bit enables flush-to-zero for
both inputs and outputs, but the reporting of when inputs are
flushed to zero is via a separate IDC bit rather than the UFC
(underflow) bit used when output denormals are flushed to zero.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Peter Maydell 2011-01-06 19:37:55 +00:00 committed by Aurelien Jarno
parent b12c390b91
commit cecd8504b8
1 changed files with 7 additions and 1 deletions
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8
target-arm/helper.c
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@ -2242,6 +2242,8 @@ static inline int vfp_exceptbits_from_host(int host_bits)
target_bits |= 8;
if (host_bits & float_flag_inexact)
target_bits |= 0x10;
if (host_bits & float_flag_input_denormal)
target_bits |= 0x80;
return target_bits;
}
@ -2278,6 +2280,8 @@ static inline int vfp_exceptbits_to_host(int target_bits)
host_bits |= float_flag_underflow;
if (target_bits & 0x10)
host_bits |= float_flag_inexact;
if (target_bits & 0x80)
host_bits |= float_flag_input_denormal;
return host_bits;
}
@ -2310,8 +2314,10 @@ void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
}
set_float_rounding_mode(i, &env->vfp.fp_status);
}
if (changed & (1 << 24))
if (changed & (1 << 24)) {
set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
}
if (changed & (1 << 25))
set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);