Peter Maydell 607b4b0876 target-arm: Clean up handling of MPIDR ... The ARM cp15 register 0,c0,c0,5 is standardised in the v7 architecture as the MPIDR. Clean up its implementation to remove A9 specific handling. This commit includes fixing an error in the value returned for the MPIDR on A9, where we were erroneously claiming a cluster ID of 9. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>		2011-02-04 21:30:15 +01:00
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cpu.h	target-arm: Add CPU feature flag for v7MP	2011-02-04 21:30:14 +01:00
exec.h	move cpu_pc_from_tb to target-*/exec.h	2010-07-03 09:48:12 +03:00
helper.c	target-arm: Clean up handling of MPIDR	2011-02-04 21:30:15 +01:00
helpers.h	Set the right overflow bit for neon 32 and 64 bit saturating add/sub.	2011-02-04 20:57:41 +01:00
iwmmxt_helper.c	Update to a hopefully more future proof FSF address	2009-07-16 20:47:01 +00:00
machine.c	Save/restore ARMv6 MMU state	2009-07-31 13:19:39 +01:00
neon_helper.c	Set the right overflow bit for neon 32 and 64 bit saturating add/sub.	2011-02-04 20:57:41 +01:00
op_addsub.h	target-arm: fix addsub/subadd implementation	2010-07-01 23:45:29 +02:00
op_helper.c	Set the right overflow bit for neon 32 and 64 bit saturating add/sub.	2011-02-04 20:57:41 +01:00
translate.c	Set the right overflow bit for neon 32 and 64 bit saturating add/sub.	2011-02-04 20:57:41 +01:00