qemu/target-arm
Peter Maydell 5de3a9d3b7 target-arm: Remove redundant setting of IT bits before Thumb SWI
Remove a redundant call to gen_set_condexec() in the translation of Thumb
mode SWI. (SWI and WFI generate "exceptions" which happen after the
execution of the instruction, ie when PC and IT bits have updated.
So the condexec bits at this point are not correct. However, the code
that handles finishing the translation of the TB will write the correct
value of the condexec bits later, so the only effect was that a conditional
Thumb SWI would generate slightly worse code than necessary.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 20:39:19 +01:00
..
cpu.h target-arm: Set privileged bit in TB flags correctly for M profile 2011-01-14 20:39:19 +01:00
exec.h move cpu_pc_from_tb to target-*/exec.h 2010-07-03 09:48:12 +03:00
helper.c target-arm: Don't generate code specific to current CPU mode for SRS 2011-01-14 20:39:18 +01:00
helpers.h ARM: add neon helpers for VQSHLU 2011-01-12 00:06:06 +01:00
iwmmxt_helper.c Update to a hopefully more future proof FSF address 2009-07-16 20:47:01 +00:00
machine.c Save/restore ARMv6 MMU state 2009-07-31 13:19:39 +01:00
neon_helper.c ARM: add neon helpers for VQSHLU 2011-01-12 00:06:06 +01:00
op_addsub.h target-arm: fix addsub/subadd implementation 2010-07-01 23:45:29 +02:00
op_helper.c [PATCH] target-arm: remove unused functions cpu_lock(), cpu_unlock() 2010-12-03 15:09:38 +02:00
translate.c target-arm: Remove redundant setting of IT bits before Thumb SWI 2011-01-14 20:39:19 +01:00